[llvm] aee4399 - [M68k] Add subtarget features for M68881/2 FPU

[Min-Yih Hsu via llvm-commits]

Author: Min-Yih Hsu
Date: 2023-04-06T11:09:23-07:00
New Revision: aee4399f58f4826180138fb294b6b0359c892709

URL: https://github.com/llvm/llvm-project/commit/aee4399f58f4826180138fb294b6b0359c892709
DIFF: https://github.com/llvm/llvm-project/commit/aee4399f58f4826180138fb294b6b0359c892709.diff

LOG: [M68k] Add subtarget features for M68881/2 FPU

Note that technically both M68000/010 can use M68881, despite the fact
that usually only M68020 and newer ISAs are equipped with M68881/2.
M68040 and newer processors have builtin M68882.

Differential Revision: https://reviews.llvm.org/D147479

Added: 
    llvm/test/CodeGen/M68k/m6888x-features.ll

Modified: 
    llvm/lib/Target/M68k/M68k.td
    llvm/lib/Target/M68k/M68kInstrInfo.td
    llvm/lib/Target/M68k/M68kSubtarget.cpp
    llvm/lib/Target/M68k/M68kSubtarget.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/M68k/M68k.td b/llvm/lib/Target/M68k/M68k.td
index de7a6c82d1104..dab66d1022955 100644
--- a/llvm/lib/Target/M68k/M68k.td
+++ b/llvm/lib/Target/M68k/M68k.td
@@ -37,10 +37,19 @@ def FeatureISA30
                      "Is M68030 ISA supported",
                      [ FeatureISA20 ]>;
 
+def FeatureISA881
+  : SubtargetFeature<"isa-68881", "FPUKind", "M881",
+                     "Is M68881 (FPU) ISA supported">;
+
+def FeatureISA882
+  : SubtargetFeature<"isa-68882", "FPUKind", "M882",
+                     "Is M68882 (FPU) ISA supported",
+                     [ FeatureISA881 ]>;
+
 def FeatureISA40
   : SubtargetFeature<"isa-68040", "SubtargetKind", "M40",
                      "Is M68040 ISA supported",
-                     [ FeatureISA30 ]>;
+                     [ FeatureISA30, FeatureISA882 ]>;
 
 def FeatureISA60
   : SubtargetFeature<"isa-68060", "SubtargetKind", "M60",

diff  --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index b595d3c6c0385..4a7bea5763fed 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -435,6 +435,10 @@ foreach i = [0,1,2,4,6] in
 def AtLeastM680 # i # "0" : Predicate<"Subtarget->atLeastM680"#i#"0()">,
                             AssemblerPredicate<(all_of
                                                 !cast<SubtargetFeature>("FeatureISA"#i#"0"))>;
+def AtLeastM68881 : Predicate<"Subtarget->atLeastM68881()">,
+                    AssemblerPredicate<(all_of FeatureISA881)>;
+def AtLeastM68882 : Predicate<"Subtarget->atLeastM68882()">,
+                    AssemblerPredicate<(all_of FeatureISA882)>;
 
 //===----------------------------------------------------------------------===//
 // Condition Codes

diff  --git a/llvm/lib/Target/M68k/M68kSubtarget.cpp b/llvm/lib/Target/M68k/M68kSubtarget.cpp
index e5a4d0d2811b6..86e81cd08ea26 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.cpp
+++ b/llvm/lib/Target/M68k/M68kSubtarget.cpp
@@ -84,8 +84,6 @@ bool M68kSubtarget::isPositionIndependent() const {
 
 bool M68kSubtarget::isLegalToCallImmediateAddr() const { return true; }
 
-bool M68kSubtarget::abiUsesSoftFloat() const { return true; }
-
 M68kSubtarget &M68kSubtarget::initializeSubtargetDependencies(
     StringRef CPU, Triple TT, StringRef FS, const M68kTargetMachine &TM) {
   std::string CPUName = selectM68kCPU(TT, CPU).str();

diff  --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index c8331d3f091e3..3fbec2f72fb86 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -51,6 +51,9 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
   enum SubtargetEnum { M00, M10, M20, M30, M40, M60 };
   SubtargetEnum SubtargetKind = M00;
 
+  enum FPKindEnum { M881, M882 };
+  std::optional<FPKindEnum> FPUKind;
+
   std::bitset<M68k::NUM_TARGET_REGS> UserReservedRegister;
 
   InstrItineraryData InstrItins;
@@ -88,9 +91,12 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
   bool atLeastM68040() const { return SubtargetKind >= M40; }
   bool atLeastM68060() const { return SubtargetKind >= M60; }
 
-  bool useSmallSection() const { return UseSmallSection; }
+  /// Floating point support
+  bool hasFPU() const { return FPUKind.has_value(); }
+  bool atLeastM68881() const { return hasFPU() && *FPUKind >= M881; }
+  bool atLeastM68882() const { return hasFPU() && *FPUKind >= M882; }
 
-  bool abiUsesSoftFloat() const;
+  bool useSmallSection() const { return UseSmallSection; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 

diff  --git a/llvm/test/CodeGen/M68k/m6888x-features.ll b/llvm/test/CodeGen/M68k/m6888x-features.ll
new file mode 100644
index 0000000000000..5145d6452e76b
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/m6888x-features.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=m68k -mattr="+isa-68881" %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mtriple=m68k -mattr="+isa-68882" %s -o - 2>&1 | FileCheck %s
+
+define dso_local i32 @f() {
+entry:
+  ret i32 0
+}
+
+; Make sure that all of the features listed are recognized.
+; CHECK-NOT:    is not a recognized feature for this target