[llvm] 2caaec6 - [InstCombine] Regenerate all test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 6 09:38:22 PDT 2023
Author: Nikita Popov
Date: 2023-04-06T18:38:11+02:00
New Revision: 2caaec65c04ea7d0e9568b7895b7a46d6100cb75
URL: https://github.com/llvm/llvm-project/commit/2caaec65c04ea7d0e9568b7895b7a46d6100cb75
DIFF: https://github.com/llvm/llvm-project/commit/2caaec65c04ea7d0e9568b7895b7a46d6100cb75.diff
LOG: [InstCombine] Regenerate all test checks (NFC)
Due to an improvement to name preservation, a lot of InstCombine
tests now show spurious diffs when regenerated.
Rather than regenerating individual files when they get touched,
mass-regenerate all UTC-based InstCombine tests. I have then reset
a number of files showing suspicious diffs where the UTC output
has clearly been manually adjusted. I apologize if I missed
anything in the mass of changes.
Added:
Modified:
llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
llvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
llvm/test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll
llvm/test/Transforms/InstCombine/2008-07-08-ShiftOneAndOne.ll
llvm/test/Transforms/InstCombine/2008-07-10-CastSextBool.ll
llvm/test/Transforms/InstCombine/2010-11-23-Distributed.ll
llvm/test/Transforms/InstCombine/CPP_min_max.ll
llvm/test/Transforms/InstCombine/abs_abs.ll
llvm/test/Transforms/InstCombine/add2.ll
llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
llvm/test/Transforms/InstCombine/align-addr.ll
llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
llvm/test/Transforms/InstCombine/and-or-icmps.ll
llvm/test/Transforms/InstCombine/and-or.ll
llvm/test/Transforms/InstCombine/and-xor-merge.ll
llvm/test/Transforms/InstCombine/and2.ll
llvm/test/Transforms/InstCombine/apint-add.ll
llvm/test/Transforms/InstCombine/apint-select.ll
llvm/test/Transforms/InstCombine/apint-shift.ll
llvm/test/Transforms/InstCombine/apint-sub.ll
llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
llvm/test/Transforms/InstCombine/bcmp-1.ll
llvm/test/Transforms/InstCombine/bcopy.ll
llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
llvm/test/Transforms/InstCombine/bitcast-function.ll
llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll
llvm/test/Transforms/InstCombine/bswap-fold.ll
llvm/test/Transforms/InstCombine/call-callconv.ll
llvm/test/Transforms/InstCombine/call-returned.ll
llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll
llvm/test/Transforms/InstCombine/canonicalize-clamp-with-select-of-constant-threshold-pattern.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll
llvm/test/Transforms/InstCombine/cast-set.ll
llvm/test/Transforms/InstCombine/cast_phi.ll
llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
llvm/test/Transforms/InstCombine/compare-signs.ll
llvm/test/Transforms/InstCombine/compare-udiv.ll
llvm/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
llvm/test/Transforms/InstCombine/copysign.ll
llvm/test/Transforms/InstCombine/cos-1.ll
llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll
llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll
llvm/test/Transforms/InstCombine/ctpop-cttz.ll
llvm/test/Transforms/InstCombine/ctpop-pow2.ll
llvm/test/Transforms/InstCombine/cttz-abs.ll
llvm/test/Transforms/InstCombine/cttz-negative.ll
llvm/test/Transforms/InstCombine/demorgan.ll
llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
llvm/test/Transforms/InstCombine/eq-of-parts.ll
llvm/test/Transforms/InstCombine/exact.ll
llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
llvm/test/Transforms/InstCombine/fabs-copysign.ll
llvm/test/Transforms/InstCombine/fadd.ll
llvm/test/Transforms/InstCombine/fast-basictest.ll
llvm/test/Transforms/InstCombine/fast-math.ll
llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
llvm/test/Transforms/InstCombine/ffs-i16.ll
llvm/test/Transforms/InstCombine/float-shrink-compare.ll
llvm/test/Transforms/InstCombine/fls-i16.ll
llvm/test/Transforms/InstCombine/fmul-exp.ll
llvm/test/Transforms/InstCombine/fmul-exp2.ll
llvm/test/Transforms/InstCombine/fmul-sqrt.ll
llvm/test/Transforms/InstCombine/fneg.ll
llvm/test/Transforms/InstCombine/fold-bin-operand.ll
llvm/test/Transforms/InstCombine/freeze-phi.ll
llvm/test/Transforms/InstCombine/icmp-add.ll
llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
llvm/test/Transforms/InstCombine/icmp-custom-dl.ll
llvm/test/Transforms/InstCombine/icmp-div-constant.ll
llvm/test/Transforms/InstCombine/icmp-dom.ll
llvm/test/Transforms/InstCombine/icmp-mul-and.ll
llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
llvm/test/Transforms/InstCombine/icmp-shl-nuw.ll
llvm/test/Transforms/InstCombine/icmp-xor-signbit.ll
llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
llvm/test/Transforms/InstCombine/intptr2.ll
llvm/test/Transforms/InstCombine/intrinsics.ll
llvm/test/Transforms/InstCombine/invariant.group.ll
llvm/test/Transforms/InstCombine/isascii-i16.ll
llvm/test/Transforms/InstCombine/isdigit-i16.ll
llvm/test/Transforms/InstCombine/ispow2.ll
llvm/test/Transforms/InstCombine/known-non-zero.ll
llvm/test/Transforms/InstCombine/load-bitcast-select.ll
llvm/test/Transforms/InstCombine/load-cmp.ll
llvm/test/Transforms/InstCombine/loadstore-metadata.ll
llvm/test/Transforms/InstCombine/log-pow.ll
llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
llvm/test/Transforms/InstCombine/malloc-free-mismatched.ll
llvm/test/Transforms/InstCombine/malloc-free.ll
llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
llvm/test/Transforms/InstCombine/masked_intrinsics.ll
llvm/test/Transforms/InstCombine/masked_intrinsics_keep_metadata.ll
llvm/test/Transforms/InstCombine/matrix-multiplication-negation.ll
llvm/test/Transforms/InstCombine/max-of-nots.ll
llvm/test/Transforms/InstCombine/max_known_bits.ll
llvm/test/Transforms/InstCombine/maximum.ll
llvm/test/Transforms/InstCombine/maxnum.ll
llvm/test/Transforms/InstCombine/mem-gep-zidx.ll
llvm/test/Transforms/InstCombine/memccpy.ll
llvm/test/Transforms/InstCombine/memchr-10.ll
llvm/test/Transforms/InstCombine/memchr-2.ll
llvm/test/Transforms/InstCombine/memcmp-5.ll
llvm/test/Transforms/InstCombine/memcmp-6.ll
llvm/test/Transforms/InstCombine/memcpy-to-load.ll
llvm/test/Transforms/InstCombine/mempcpy.ll
llvm/test/Transforms/InstCombine/memrchr-7.ll
llvm/test/Transforms/InstCombine/merge-icmp.ll
llvm/test/Transforms/InstCombine/min-positive.ll
llvm/test/Transforms/InstCombine/minimum.ll
llvm/test/Transforms/InstCombine/minmax-demandbits.ll
llvm/test/Transforms/InstCombine/minmax-fp.ll
llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
llvm/test/Transforms/InstCombine/minnum.ll
llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
llvm/test/Transforms/InstCombine/mul.ll
llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
llvm/test/Transforms/InstCombine/narrow-math.ll
llvm/test/Transforms/InstCombine/nested-select.ll
llvm/test/Transforms/InstCombine/onehot_merge.ll
llvm/test/Transforms/InstCombine/or-fcmp.ll
llvm/test/Transforms/InstCombine/or.ll
llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
llvm/test/Transforms/InstCombine/phi-extractvalue.ll
llvm/test/Transforms/InstCombine/phi-int2ptr-fold.ll
llvm/test/Transforms/InstCombine/phi-pointercasts.ll
llvm/test/Transforms/InstCombine/pow-3.ll
llvm/test/Transforms/InstCombine/pow-exp.ll
llvm/test/Transforms/InstCombine/pow-sqrt.ll
llvm/test/Transforms/InstCombine/powi.ll
llvm/test/Transforms/InstCombine/pr17827.ll
llvm/test/Transforms/InstCombine/pr21199.ll
llvm/test/Transforms/InstCombine/pr21651.ll
llvm/test/Transforms/InstCombine/pr25342.ll
llvm/test/Transforms/InstCombine/pr32686.ll
llvm/test/Transforms/InstCombine/pr38897.ll
llvm/test/Transforms/InstCombine/pr38915.ll
llvm/test/Transforms/InstCombine/pr43376-getFlippedStrictnessPredicateAndConstant-assert.ll
llvm/test/Transforms/InstCombine/pr44541.ll
llvm/test/Transforms/InstCombine/preserve-sminmax.ll
llvm/test/Transforms/InstCombine/printf-1.ll
llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll
llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll
llvm/test/Transforms/InstCombine/range-check.ll
llvm/test/Transforms/InstCombine/recurrence.ll
llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll
llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll
llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
llvm/test/Transforms/InstCombine/sadd-with-overflow.ll
llvm/test/Transforms/InstCombine/sadd_sat.ll
llvm/test/Transforms/InstCombine/sdiv-canonicalize.ll
llvm/test/Transforms/InstCombine/sdiv-guard.ll
llvm/test/Transforms/InstCombine/sdiv-of-non-negative-by-negative-power-of-two.ll
llvm/test/Transforms/InstCombine/select-2.ll
llvm/test/Transforms/InstCombine/select-and-or.ll
llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
llvm/test/Transforms/InstCombine/select-gep.ll
llvm/test/Transforms/InstCombine/select-icmp-and.ll
llvm/test/Transforms/InstCombine/select-imm-canon.ll
llvm/test/Transforms/InstCombine/select-min-max.ll
llvm/test/Transforms/InstCombine/select-safe-transforms.ll
llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
llvm/test/Transforms/InstCombine/select_meta.ll
llvm/test/Transforms/InstCombine/set.ll
llvm/test/Transforms/InstCombine/sext.ll
llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
llvm/test/Transforms/InstCombine/shift-sra.ll
llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
llvm/test/Transforms/InstCombine/shuffle_select.ll
llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll
llvm/test/Transforms/InstCombine/signed-comparison.ll
llvm/test/Transforms/InstCombine/sink-into-catchswitch.ll
llvm/test/Transforms/InstCombine/sink_instruction.ll
llvm/test/Transforms/InstCombine/sprintf-1.ll
llvm/test/Transforms/InstCombine/sprintf-3.ll
llvm/test/Transforms/InstCombine/ssub-with-overflow.ll
llvm/test/Transforms/InstCombine/store.ll
llvm/test/Transforms/InstCombine/strcmp-1.ll
llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
llvm/test/Transforms/InstCombine/strlen-1.ll
llvm/test/Transforms/InstCombine/strncmp-1.ll
llvm/test/Transforms/InstCombine/strncmp-5.ll
llvm/test/Transforms/InstCombine/strncmp-6.ll
llvm/test/Transforms/InstCombine/strnlen-1.ll
llvm/test/Transforms/InstCombine/strnlen-3.ll
llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
llvm/test/Transforms/InstCombine/sub-gep.ll
llvm/test/Transforms/InstCombine/sub-not.ll
llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
llvm/test/Transforms/InstCombine/sub-of-negatible.ll
llvm/test/Transforms/InstCombine/subtract-from-one-hand-of-select.ll
llvm/test/Transforms/InstCombine/subtract-of-one-hand-of-select.ll
llvm/test/Transforms/InstCombine/switch-constant-expr.ll
llvm/test/Transforms/InstCombine/trivial-dse-calls.ll
llvm/test/Transforms/InstCombine/truncating-saturate.ll
llvm/test/Transforms/InstCombine/uadd-with-overflow.ll
llvm/test/Transforms/InstCombine/uaddo.ll
llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
llvm/test/Transforms/InstCombine/unordered-fcmp-select.ll
llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-mul-udiv.ll
llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-mul-udiv.ll
llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
llvm/test/Transforms/InstCombine/vector-casts.ll
llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
llvm/test/Transforms/InstCombine/vector-reductions.ll
llvm/test/Transforms/InstCombine/vector-xor.ll
llvm/test/Transforms/InstCombine/vscale_gep.ll
llvm/test/Transforms/InstCombine/vscale_trunc.ll
llvm/test/Transforms/InstCombine/wcslen-3.ll
llvm/test/Transforms/InstCombine/with_overflow.ll
llvm/test/Transforms/InstCombine/xor-and-or.ll
llvm/test/Transforms/InstCombine/xor-icmps.ll
llvm/test/Transforms/InstCombine/xor-of-icmps-with-extra-uses.ll
llvm/test/Transforms/InstCombine/xor.ll
llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll
llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
llvm/test/Transforms/InstCombine/zext-or-icmp.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll b/llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
index 1e64f90de6c66..0c8e2770ec7ae 100644
--- a/llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
+++ b/llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
@@ -19,8 +19,8 @@ define i1 @print_pgm_cond_true(i32 %tmp12.reload, ptr %tmp16.out) {
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr [17 x i32], ptr @r, i32 0, i32 [[TMP12_RELOAD:%.*]]
; CHECK-NEXT: [[TMP16]] = load i32, ptr [[TMP15]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[TMP16]], -32
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], -63
-; CHECK-NEXT: br i1 [[TMP1]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
+; CHECK-NEXT: [[BOTHCOND:%.*]] = icmp ult i32 [[TMP0]], -63
+; CHECK-NEXT: br i1 [[BOTHCOND]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
;
newFuncRoot:
br label %cond_true
@@ -56,8 +56,8 @@ define i1 @print_pgm_cond_true_logical(i32 %tmp12.reload, ptr %tmp16.out) {
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr [17 x i32], ptr @r, i32 0, i32 [[TMP12_RELOAD:%.*]]
; CHECK-NEXT: [[TMP16]] = load i32, ptr [[TMP15]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[TMP16]], -32
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], -63
-; CHECK-NEXT: br i1 [[TMP1]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
+; CHECK-NEXT: [[BOTHCOND:%.*]] = icmp ult i32 [[TMP0]], -63
+; CHECK-NEXT: br i1 [[BOTHCOND]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
;
newFuncRoot:
br label %cond_true
diff --git a/llvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll b/llvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
index 573b651160363..9804d6edadd37 100644
--- a/llvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
+++ b/llvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
@@ -5,8 +5,8 @@
define i1 @test(i32 %c.3.i, i32 %d.292.2.i) {
; CHECK-LABEL: @test(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sle i32 [[C_3_I:%.*]], [[D_292_2_I:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[SEL_TMP80:%.*]] = icmp sle i32 [[C_3_I:%.*]], [[D_292_2_I:%.*]]
+; CHECK-NEXT: ret i1 [[SEL_TMP80]]
;
%tmp266.i = icmp slt i32 %c.3.i, %d.292.2.i
%tmp276.i = icmp eq i32 %c.3.i, %d.292.2.i
@@ -16,8 +16,8 @@ define i1 @test(i32 %c.3.i, i32 %d.292.2.i) {
define i1 @test_logical(i32 %c.3.i, i32 %d.292.2.i) {
; CHECK-LABEL: @test_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sle i32 [[C_3_I:%.*]], [[D_292_2_I:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[SEL_TMP80:%.*]] = icmp sle i32 [[C_3_I:%.*]], [[D_292_2_I:%.*]]
+; CHECK-NEXT: ret i1 [[SEL_TMP80]]
;
%tmp266.i = icmp slt i32 %c.3.i, %d.292.2.i
%tmp276.i = icmp eq i32 %c.3.i, %d.292.2.i
diff --git a/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll b/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
index 2f0a49c4f5e6c..ffc05a40865d3 100644
--- a/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
+++ b/llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
@@ -8,13 +8,13 @@
define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[U:%.*]] = alloca %struct..1anon, align 8
+; CHECK-NEXT: [[U:%.*]] = alloca [[STRUCT__1ANON:%.*]], align 8
; CHECK-NEXT: store double 0x7FF0000000000000, ptr [[U]], align 8
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds %struct..0anon, ptr [[U]], i64 0, i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__0ANON:%.*]], ptr [[U]], i64 0, i32 1
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-; CHECK-NEXT: [[TMP89:%.*]] = and i32 [[TMP6]], 2146435072
-; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[TMP89]], 2146435072
-; CHECK-NEXT: br i1 [[TMP0]], label %cond_false, label %cond_true
+; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[TMP6]], 2146435072
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP0]], 2146435072
+; CHECK-NEXT: br i1 [[DOTNOT]], label [[COND_FALSE:%.*]], label [[COND_TRUE:%.*]]
; CHECK: cond_true:
; CHECK-NEXT: ret i32 0
; CHECK: cond_false:
diff --git a/llvm/test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll b/llvm/test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll
index 11c2ebd3b18ce..a873e02f88725 100644
--- a/llvm/test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll
+++ b/llvm/test/Transforms/InstCombine/2007-12-18-AddSelCmpSub.ll
@@ -4,8 +4,8 @@
define i32 @foo(i32 %a) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: [[T15:%.*]] = sub i32 99, [[A:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[T15]], i32 0)
-; CHECK-NEXT: [[T12:%.*]] = add i32 [[TMP1]], [[A]]
+; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[T15]], i32 0)
+; CHECK-NEXT: [[T12:%.*]] = add i32 [[SMAX]], [[A]]
; CHECK-NEXT: [[T13:%.*]] = add i32 [[T12]], 1
; CHECK-NEXT: ret i32 [[T13]]
;
@@ -20,8 +20,8 @@ define i32 @foo(i32 %a) {
define i32 @bar(i32 %a) {
; CHECK-LABEL: @bar(
; CHECK-NEXT: [[T15:%.*]] = sub i32 99, [[A:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[T15]], i32 0)
-; CHECK-NEXT: [[T12:%.*]] = add i32 [[TMP1]], [[A]]
+; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[T15]], i32 0)
+; CHECK-NEXT: [[T12:%.*]] = add i32 [[SMAX]], [[A]]
; CHECK-NEXT: ret i32 [[T12]]
;
%t15 = sub i32 99, %a
diff --git a/llvm/test/Transforms/InstCombine/2008-07-08-ShiftOneAndOne.ll b/llvm/test/Transforms/InstCombine/2008-07-08-ShiftOneAndOne.ll
index d431132106da9..feff510175f7c 100644
--- a/llvm/test/Transforms/InstCombine/2008-07-08-ShiftOneAndOne.ll
+++ b/llvm/test/Transforms/InstCombine/2008-07-08-ShiftOneAndOne.ll
@@ -3,8 +3,8 @@
define i1 @PR2330(i32 %a) {
; CHECK-LABEL: @PR2330(
-; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 %a, 0
-; CHECK-NEXT: ret i1 [[TOBOOL]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[A:%.*]], 0
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%tmp15 = shl i32 1, %a
%tmp237 = and i32 %tmp15, 1
diff --git a/llvm/test/Transforms/InstCombine/2008-07-10-CastSextBool.ll b/llvm/test/Transforms/InstCombine/2008-07-10-CastSextBool.ll
index 0122defb99016..ac9daeec17364 100644
--- a/llvm/test/Transforms/InstCombine/2008-07-10-CastSextBool.ll
+++ b/llvm/test/Transforms/InstCombine/2008-07-10-CastSextBool.ll
@@ -3,7 +3,7 @@
define i1 @PR2539_A(i1 %A) {
; CHECK-LABEL: @PR2539_A(
-; CHECK-NEXT: [[C:%.*]] = xor i1 %A, true
+; CHECK-NEXT: [[C:%.*]] = xor i1 [[A:%.*]], true
; CHECK-NEXT: ret i1 [[C]]
;
%B = zext i1 %A to i32
diff --git a/llvm/test/Transforms/InstCombine/2010-11-23-Distributed.ll b/llvm/test/Transforms/InstCombine/2010-11-23-Distributed.ll
index bfd3b07f2d0e0..70fd7274f35d4 100644
--- a/llvm/test/Transforms/InstCombine/2010-11-23-Distributed.ll
+++ b/llvm/test/Transforms/InstCombine/2010-11-23-Distributed.ll
@@ -15,8 +15,8 @@ define i32 @foo(i32 %x, i32 %y) {
define i1 @bar(i64 %x, i64 %y) {
; CHECK-LABEL: @bar(
-; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[X:%.*]], -1
-; CHECK-NEXT: [[B:%.*]] = and i64 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[Y1:%.*]] = xor i64 [[X:%.*]], -1
+; CHECK-NEXT: [[B:%.*]] = and i64 [[Y1]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[B]], 0
; CHECK-NEXT: ret i1 [[R]]
;
diff --git a/llvm/test/Transforms/InstCombine/CPP_min_max.ll b/llvm/test/Transforms/InstCombine/CPP_min_max.ll
index 6129087580308..5eeb4e42b4ab4 100644
--- a/llvm/test/Transforms/InstCombine/CPP_min_max.ll
+++ b/llvm/test/Transforms/InstCombine/CPP_min_max.ll
@@ -13,8 +13,8 @@ define void @_Z5test1RiS_(ptr %x, ptr %y) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP_1_I:%.*]] = load i32, ptr [[Y:%.*]], align 4
; CHECK-NEXT: [[TMP_3_I:%.*]] = load i32, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP_1_I]], i32 [[TMP_3_I]])
-; CHECK-NEXT: store i32 [[TMP0]], ptr [[X]], align 4
+; CHECK-NEXT: [[TMP_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP_1_I]], i32 [[TMP_3_I]])
+; CHECK-NEXT: store i32 [[TMP_4]], ptr [[X]], align 4
; CHECK-NEXT: ret void
;
entry:
@@ -32,8 +32,8 @@ define void @_Z5test2RiS_(ptr %x, ptr %y) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP_2:%.*]] = load i32, ptr [[X:%.*]], align 4
; CHECK-NEXT: [[TMP_3_I:%.*]] = load i32, ptr [[Y:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP_2]], i32 [[TMP_3_I]])
-; CHECK-NEXT: store i32 [[TMP0]], ptr [[Y]], align 4
+; CHECK-NEXT: [[TMP_6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP_2]], i32 [[TMP_3_I]])
+; CHECK-NEXT: store i32 [[TMP_6]], ptr [[Y]], align 4
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/abs_abs.ll b/llvm/test/Transforms/InstCombine/abs_abs.ll
index 172f23e9dad99..635ac73ab1703 100644
--- a/llvm/test/Transforms/InstCombine/abs_abs.ll
+++ b/llvm/test/Transforms/InstCombine/abs_abs.ll
@@ -3,8 +3,8 @@
define i32 @abs_abs_x01(i32 %x) {
; CHECK-LABEL: @abs_abs_x01(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, -1
%sub = sub nsw i32 0, %x
@@ -17,8 +17,8 @@ define i32 @abs_abs_x01(i32 %x) {
define <2 x i32> @abs_abs_x01_vec(<2 x i32> %x) {
; CHECK-LABEL: @abs_abs_x01_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: ret <2 x i32> [[COND]]
;
%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
%sub = sub nsw <2 x i32> zeroinitializer, %x
@@ -31,8 +31,8 @@ define <2 x i32> @abs_abs_x01_vec(<2 x i32> %x) {
define i32 @abs_abs_x02(i32 %x) {
; CHECK-LABEL: @abs_abs_x02(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -45,8 +45,8 @@ define i32 @abs_abs_x02(i32 %x) {
define i32 @abs_abs_x03(i32 %x) {
; CHECK-LABEL: @abs_abs_x03(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -59,8 +59,8 @@ define i32 @abs_abs_x03(i32 %x) {
define i32 @abs_abs_x04(i32 %x) {
; CHECK-LABEL: @abs_abs_x04(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 1
%sub = sub nsw i32 0, %x
@@ -73,8 +73,8 @@ define i32 @abs_abs_x04(i32 %x) {
define <2 x i32> @abs_abs_x04_vec(<2 x i32> %x) {
; CHECK-LABEL: @abs_abs_x04_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: ret <2 x i32> [[COND]]
;
%cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
%sub = sub nsw <2 x i32> zeroinitializer, %x
@@ -87,8 +87,8 @@ define <2 x i32> @abs_abs_x04_vec(<2 x i32> %x) {
define i32 @abs_abs_x05(i32 %x) {
; CHECK-LABEL: @abs_abs_x05(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, -1
%sub = sub nsw i32 0, %x
@@ -101,8 +101,8 @@ define i32 @abs_abs_x05(i32 %x) {
define i32 @abs_abs_x06(i32 %x) {
; CHECK-LABEL: @abs_abs_x06(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -115,8 +115,8 @@ define i32 @abs_abs_x06(i32 %x) {
define i32 @abs_abs_x07(i32 %x) {
; CHECK-LABEL: @abs_abs_x07(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -129,8 +129,8 @@ define i32 @abs_abs_x07(i32 %x) {
define i32 @abs_abs_x08(i32 %x) {
; CHECK-LABEL: @abs_abs_x08(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 1
%sub = sub nsw i32 0, %x
@@ -143,8 +143,8 @@ define i32 @abs_abs_x08(i32 %x) {
define i32 @abs_abs_x09(i32 %x) {
; CHECK-LABEL: @abs_abs_x09(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, -1
%sub = sub nsw i32 0, %x
@@ -157,8 +157,8 @@ define i32 @abs_abs_x09(i32 %x) {
define i32 @abs_abs_x10(i32 %x) {
; CHECK-LABEL: @abs_abs_x10(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -171,8 +171,8 @@ define i32 @abs_abs_x10(i32 %x) {
define i32 @abs_abs_x11(i32 %x) {
; CHECK-LABEL: @abs_abs_x11(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -185,8 +185,8 @@ define i32 @abs_abs_x11(i32 %x) {
define i32 @abs_abs_x12(i32 %x) {
; CHECK-LABEL: @abs_abs_x12(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 1
%sub = sub nsw i32 0, %x
@@ -199,8 +199,8 @@ define i32 @abs_abs_x12(i32 %x) {
define i32 @abs_abs_x13(i32 %x) {
; CHECK-LABEL: @abs_abs_x13(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, -1
%sub = sub nsw i32 0, %x
@@ -213,8 +213,8 @@ define i32 @abs_abs_x13(i32 %x) {
define i32 @abs_abs_x14(i32 %x) {
; CHECK-LABEL: @abs_abs_x14(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -227,8 +227,8 @@ define i32 @abs_abs_x14(i32 %x) {
define i32 @abs_abs_x15(i32 %x) {
; CHECK-LABEL: @abs_abs_x15(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 0
%sub = sub nsw i32 0, %x
@@ -241,8 +241,8 @@ define i32 @abs_abs_x15(i32 %x) {
define i32 @abs_abs_x16(i32 %x) {
; CHECK-LABEL: @abs_abs_x16(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 1
%sub = sub nsw i32 0, %x
@@ -256,8 +256,8 @@ define i32 @abs_abs_x16(i32 %x) {
; abs(abs(-x)) -> abs(-x) -> abs(x)
define i32 @abs_abs_x17(i32 %x) {
; CHECK-LABEL: @abs_abs_x17(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[COND]]
;
%sub = sub nsw i32 0, %x
%cmp = icmp sgt i32 %sub, -1
@@ -272,8 +272,8 @@ define i32 @abs_abs_x17(i32 %x) {
define i32 @abs_abs_x18(i32 %x, i32 %y) {
; CHECK-LABEL: @abs_abs_x18(
; CHECK-NEXT: [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT: ret i32 [[COND]]
;
%a = sub nsw i32 %x, %y
%b = sub nsw i32 %y, %x
@@ -288,8 +288,8 @@ define i32 @abs_abs_x18(i32 %x, i32 %y) {
; abs(abs(-x)) -> abs(-x) -> abs(x)
define <2 x i32> @abs_abs_x02_vec(<2 x i32> %x) {
; CHECK-LABEL: @abs_abs_x02_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: ret <2 x i32> [[COND]]
;
%sub = sub nsw <2 x i32> zeroinitializer, %x
%cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
@@ -304,8 +304,8 @@ define <2 x i32> @abs_abs_x02_vec(<2 x i32> %x) {
define <2 x i32> @abs_abs_x03_vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @abs_abs_x03_vec(
; CHECK-NEXT: [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
+; CHECK-NEXT: ret <2 x i32> [[COND]]
;
%a = sub nsw <2 x i32> %x, %y
%b = sub nsw <2 x i32> %y, %x
@@ -915,8 +915,8 @@ define <2 x i32> @abs_nabs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
define i32 @nabs_abs_x01(i32 %x) {
; CHECK-LABEL: @nabs_abs_x01(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp sgt i32 %x, -1
@@ -930,8 +930,8 @@ define i32 @nabs_abs_x01(i32 %x) {
define i32 @nabs_abs_x02(i32 %x) {
; CHECK-LABEL: @nabs_abs_x02(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp sgt i32 %x, 0
@@ -945,8 +945,8 @@ define i32 @nabs_abs_x02(i32 %x) {
define i32 @nabs_abs_x03(i32 %x) {
; CHECK-LABEL: @nabs_abs_x03(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp slt i32 %x, 0
@@ -960,8 +960,8 @@ define i32 @nabs_abs_x03(i32 %x) {
define i32 @nabs_abs_x04(i32 %x) {
; CHECK-LABEL: @nabs_abs_x04(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp slt i32 %x, 1
@@ -975,8 +975,8 @@ define i32 @nabs_abs_x04(i32 %x) {
define i32 @nabs_abs_x05(i32 %x) {
; CHECK-LABEL: @nabs_abs_x05(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp sgt i32 %x, -1
@@ -990,8 +990,8 @@ define i32 @nabs_abs_x05(i32 %x) {
define i32 @nabs_abs_x06(i32 %x) {
; CHECK-LABEL: @nabs_abs_x06(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp sgt i32 %x, 0
@@ -1005,8 +1005,8 @@ define i32 @nabs_abs_x06(i32 %x) {
define i32 @nabs_abs_x07(i32 %x) {
; CHECK-LABEL: @nabs_abs_x07(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp slt i32 %x, 0
@@ -1020,8 +1020,8 @@ define i32 @nabs_abs_x07(i32 %x) {
define i32 @nabs_abs_x08(i32 %x) {
; CHECK-LABEL: @nabs_abs_x08(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB9:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB9]]
;
%cmp = icmp slt i32 %x, 1
@@ -1035,8 +1035,8 @@ define i32 @nabs_abs_x08(i32 %x) {
define i32 @nabs_abs_x09(i32 %x) {
; CHECK-LABEL: @nabs_abs_x09(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp sgt i32 %x, -1
@@ -1050,8 +1050,8 @@ define i32 @nabs_abs_x09(i32 %x) {
define i32 @nabs_abs_x10(i32 %x) {
; CHECK-LABEL: @nabs_abs_x10(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp sgt i32 %x, 0
@@ -1065,8 +1065,8 @@ define i32 @nabs_abs_x10(i32 %x) {
define i32 @nabs_abs_x11(i32 %x) {
; CHECK-LABEL: @nabs_abs_x11(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp slt i32 %x, 0
@@ -1080,8 +1080,8 @@ define i32 @nabs_abs_x11(i32 %x) {
define i32 @nabs_abs_x12(i32 %x) {
; CHECK-LABEL: @nabs_abs_x12(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp slt i32 %x, 1
@@ -1095,8 +1095,8 @@ define i32 @nabs_abs_x12(i32 %x) {
define i32 @nabs_abs_x13(i32 %x) {
; CHECK-LABEL: @nabs_abs_x13(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp sgt i32 %x, -1
@@ -1110,8 +1110,8 @@ define i32 @nabs_abs_x13(i32 %x) {
define i32 @nabs_abs_x14(i32 %x) {
; CHECK-LABEL: @nabs_abs_x14(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp sgt i32 %x, 0
@@ -1125,8 +1125,8 @@ define i32 @nabs_abs_x14(i32 %x) {
define i32 @nabs_abs_x15(i32 %x) {
; CHECK-LABEL: @nabs_abs_x15(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp slt i32 %x, 0
@@ -1140,8 +1140,8 @@ define i32 @nabs_abs_x15(i32 %x) {
define i32 @nabs_abs_x16(i32 %x) {
; CHECK-LABEL: @nabs_abs_x16(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%cmp = icmp slt i32 %x, 1
@@ -1156,8 +1156,8 @@ define i32 @nabs_abs_x16(i32 %x) {
; nabs(abs(-x)) -> nabs(-x) -> nabs(x)
define i32 @nabs_abs_x17(i32 %x) {
; CHECK-LABEL: @nabs_abs_x17(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[SUB16]]
;
%sub = sub nsw i32 0, %x
@@ -1173,8 +1173,8 @@ define i32 @nabs_abs_x17(i32 %x) {
define i32 @nabs_abs_x18(i32 %x, i32 %y) {
; CHECK-LABEL: @nabs_abs_x18(
; CHECK-NEXT: [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
-; CHECK-NEXT: [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT: [[COND18:%.*]] = sub i32 0, [[COND]]
; CHECK-NEXT: ret i32 [[COND18]]
;
%a = sub nsw i32 %x, %y
@@ -1190,8 +1190,8 @@ define i32 @nabs_abs_x18(i32 %x, i32 %y) {
; nabs(abs(-x)) -> nabs(-x) -> nabs(x)
define <2 x i32> @nabs_abs_x01_vec(<2 x i32> %x) {
; CHECK-LABEL: @nabs_abs_x01_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
-; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]]
; CHECK-NEXT: ret <2 x i32> [[SUB16]]
;
%sub = sub nsw <2 x i32> zeroinitializer, %x
@@ -1207,8 +1207,8 @@ define <2 x i32> @nabs_abs_x01_vec(<2 x i32> %x) {
define <2 x i32> @nabs_abs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @nabs_abs_x02_vec(
; CHECK-NEXT: [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
-; CHECK-NEXT: [[COND18:%.*]] = sub <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
+; CHECK-NEXT: [[COND18:%.*]] = sub <2 x i32> zeroinitializer, [[COND]]
; CHECK-NEXT: ret <2 x i32> [[COND18]]
;
%a = sub nsw <2 x i32> %x, %y
diff --git a/llvm/test/Transforms/InstCombine/add2.ll b/llvm/test/Transforms/InstCombine/add2.ll
index a0e1a9c93405b..9170d291794e0 100644
--- a/llvm/test/Transforms/InstCombine/add2.ll
+++ b/llvm/test/Transforms/InstCombine/add2.ll
@@ -92,8 +92,8 @@ define i32 @test10(i32 %x, i32 %y) {
; CHECK-LABEL: @test10(
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[X:%.*]], 3
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHR]], 1431655765
-; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: ret i32 [[SUB]]
+; CHECK-NEXT: [[ADD1:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret i32 [[ADD1]]
;
%shr = ashr i32 %x, 3
%shr.not = or i32 %shr, -1431655766
@@ -107,8 +107,8 @@ define i32 @test10(i32 %x, i32 %y) {
define i32 @test11(i32 %x, i32 %y) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1431655765
-; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: ret i32 [[SUB]]
+; CHECK-NEXT: [[ADD1:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret i32 [[ADD1]]
;
%x.not = or i32 %x, -1431655766
%neg = xor i32 %x.not, 1431655765
@@ -121,8 +121,8 @@ define i32 @test11(i32 %x, i32 %y) {
define i32 @test12(i32 %x, i32 %y) {
; CHECK-LABEL: @test12(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1431655765
-; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: ret i32 [[SUB]]
+; CHECK-NEXT: [[ADD1:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret i32 [[ADD1]]
;
%add = add nsw i32 %y, 1
%x.not = or i32 %x, -1431655766
@@ -135,8 +135,8 @@ define i32 @test12(i32 %x, i32 %y) {
define i32 @test13(i32 %x, i32 %y) {
; CHECK-LABEL: @test13(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1431655766
-; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: ret i32 [[SUB]]
+; CHECK-NEXT: [[ADD1:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret i32 [[ADD1]]
;
%x.not = or i32 %x, -1431655767
%neg = xor i32 %x.not, 1431655766
@@ -149,8 +149,8 @@ define i32 @test13(i32 %x, i32 %y) {
define i32 @test14(i32 %x, i32 %y) {
; CHECK-LABEL: @test14(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1431655766
-; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
-; CHECK-NEXT: ret i32 [[SUB]]
+; CHECK-NEXT: [[ADD1:%.*]] = sub i32 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: ret i32 [[ADD1]]
;
%add = add nsw i32 %y, 1
%x.not = or i32 %x, -1431655767
@@ -329,7 +329,7 @@ define i16 @mul_add_to_mul_9(i16 %a) {
; ValueTracking uses that range.
define i16 @add_cttz(i16 %a) {
; CHECK-LABEL: @add_cttz(
-; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !0
+; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -8
; CHECK-NEXT: ret i16 [[B]]
;
@@ -351,7 +351,7 @@ declare i16 @llvm.cttz.i16(i16, i1)
; intrinsic is more strict. Therefore, ValueTracking uses that range.
define i16 @add_cttz_2(i16 %a) {
; CHECK-LABEL: @add_cttz_2(
-; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !1
+; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -16
; CHECK-NEXT: ret i16 [[B]]
;
diff --git a/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll b/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
index b6ba2143f8ecc..703ba52fa378f 100644
--- a/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
+++ b/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
@@ -7,8 +7,8 @@
define i32 @smax1(i32 %n) {
; CHECK-LABEL: @smax1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
@@ -19,8 +19,8 @@ define i32 @smax1(i32 %n) {
define i32 @smin1(i32 %n) {
; CHECK-LABEL: @smin1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
@@ -31,8 +31,8 @@ define i32 @smin1(i32 %n) {
define i32 @smax2(i32 %n) {
; CHECK-LABEL: @smax2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
@@ -43,8 +43,8 @@ define i32 @smax2(i32 %n) {
define i32 @smin2(i32 %n) {
; CHECK-LABEL: @smin2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
@@ -55,8 +55,8 @@ define i32 @smin2(i32 %n) {
define i32 @smax3(i32 %n) {
; CHECK-LABEL: @smax3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sgt i32 %n, -1
%m = select i1 %t, i32 %n, i32 0
@@ -67,8 +67,8 @@ define i32 @smax3(i32 %n) {
define <2 x i32> @smax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax3_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
@@ -79,8 +79,8 @@ define <2 x i32> @smax3_vec(<2 x i32> %n) {
define i32 @smin3(i32 %n) {
; CHECK-LABEL: @smin3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp slt i32 %n, 1
%m = select i1 %t, i32 %n, i32 0
@@ -91,8 +91,8 @@ define i32 @smin3(i32 %n) {
define <2 x i32> @smin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin3_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp slt <2 x i32> %n, <i32 1, i32 1>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
@@ -103,8 +103,8 @@ define <2 x i32> @smin3_vec(<2 x i32> %n) {
define i32 @umax3(i32 %n) {
; CHECK-LABEL: @umax3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 5)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 5)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp ugt i32 %n, 4
%m = select i1 %t, i32 %n, i32 5
@@ -115,8 +115,8 @@ define i32 @umax3(i32 %n) {
define <2 x i32> @umax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax3_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 5, i32 5>)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 5, i32 5>)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ugt <2 x i32> %n, <i32 4, i32 4>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 5, i32 5>
@@ -127,8 +127,8 @@ define <2 x i32> @umax3_vec(<2 x i32> %n) {
define i32 @umin3(i32 %n) {
; CHECK-LABEL: @umin3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 6)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 6)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp ult i32 %n, 7
%m = select i1 %t, i32 %n, i32 6
@@ -139,8 +139,8 @@ define i32 @umin3(i32 %n) {
define <2 x i32> @umin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin3_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 6, i32 6>)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 6, i32 6>)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ult <2 x i32> %n, <i32 7, i32 7>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 6, i32 6>
@@ -151,8 +151,8 @@ define <2 x i32> @umin3_vec(<2 x i32> %n) {
define i32 @smax4(i32 %n) {
; CHECK-LABEL: @smax4(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smax.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sge i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
@@ -163,8 +163,8 @@ define i32 @smax4(i32 %n) {
define <2 x i32> @smax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax4_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sge <2 x i32> %n, zeroinitializer
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
@@ -175,8 +175,8 @@ define <2 x i32> @smax4_vec(<2 x i32> %n) {
define i32 @smin4(i32 %n) {
; CHECK-LABEL: @smin4(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.smin.i32(i32 [[N:%.*]], i32 0)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp sle i32 %n, 0
%m = select i1 %t, i32 %n, i32 0
@@ -187,8 +187,8 @@ define i32 @smin4(i32 %n) {
define <2 x i32> @smin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin4_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> zeroinitializer)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sle <2 x i32> %n, zeroinitializer
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> zeroinitializer
@@ -199,8 +199,8 @@ define <2 x i32> @smin4_vec(<2 x i32> %n) {
define i32 @umax4(i32 %n) {
; CHECK-LABEL: @umax4(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 8)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umax.i32(i32 [[N:%.*]], i32 8)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp uge i32 %n, 8
%m = select i1 %t, i32 %n, i32 8
@@ -211,8 +211,8 @@ define i32 @umax4(i32 %n) {
define <2 x i32> @umax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax4_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 8, i32 8>)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 8, i32 8>)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp uge <2 x i32> %n, <i32 8, i32 8>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 8, i32 8>
@@ -223,8 +223,8 @@ define <2 x i32> @umax4_vec(<2 x i32> %n) {
define i32 @umin4(i32 %n) {
; CHECK-LABEL: @umin4(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 9)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[N:%.*]], i32 9)
+; CHECK-NEXT: ret i32 [[M]]
;
%t = icmp ule i32 %n, 9
%m = select i1 %t, i32 %n, i32 9
@@ -235,8 +235,8 @@ define i32 @umin4(i32 %n) {
define <2 x i32> @umin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin4_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 9, i32 9>)
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[N:%.*]], <2 x i32> <i32 9, i32 9>)
+; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ule <2 x i32> %n, <i32 9, i32 9>
%m = select <2 x i1> %t, <2 x i32> %n, <2 x i32> <i32 9, i32 9>
@@ -246,8 +246,8 @@ define <2 x i32> @umin4_vec(<2 x i32> %n) {
define i64 @smax_sext(i32 %a) {
; CHECK-LABEL: @smax_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MAX]]
;
%a_ext = sext i32 %a to i64
%cmp = icmp sgt i32 %a, -1
@@ -258,8 +258,8 @@ define i64 @smax_sext(i32 %a) {
define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @smax_sext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
%cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
@@ -270,8 +270,8 @@ define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
define i64 @smin_sext(i32 %a) {
; CHECK-LABEL: @smin_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MIN]]
;
%a_ext = sext i32 %a to i64
%cmp = icmp slt i32 %a, 1
@@ -282,8 +282,8 @@ define i64 @smin_sext(i32 %a) {
define <2 x i64>@smin_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @smin_sext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> zeroinitializer)
-; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
%cmp = icmp slt <2 x i32> %a, <i32 1, i32 1>
@@ -294,8 +294,8 @@ define <2 x i64>@smin_sext_vec(<2 x i32> %a) {
define i64 @umax_sext(i32 %a) {
; CHECK-LABEL: @umax_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 3)
-; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MAX]]
;
%a_ext = sext i32 %a to i64
%cmp = icmp ugt i32 %a, 2
@@ -306,8 +306,8 @@ define i64 @umax_sext(i32 %a) {
define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_sext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
-; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
%cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2>
@@ -318,8 +318,8 @@ define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
define i64 @umin_sext(i32 %a) {
; CHECK-LABEL: @umin_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MIN]]
;
%a_ext = sext i32 %a to i64
%cmp = icmp ult i32 %a, 3
@@ -330,8 +330,8 @@ define i64 @umin_sext(i32 %a) {
define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_sext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
-; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
%cmp = icmp ult <2 x i32> %a, <i32 3, i32 3>
@@ -342,8 +342,8 @@ define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
define i64 @umax_sext2(i32 %a) {
; CHECK-LABEL: @umax_sext2(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MIN]]
;
%a_ext = sext i32 %a to i64
%cmp = icmp ult i32 %a, 3
@@ -354,8 +354,8 @@ define i64 @umax_sext2(i32 %a) {
define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_sext2_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
-; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
%cmp = icmp ult <2 x i32> %a, <i32 3, i32 3>
@@ -366,8 +366,8 @@ define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
define i64 @umin_sext2(i32 %a) {
; CHECK-LABEL: @umin_sext2(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 3)
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MIN]]
;
%a_ext = sext i32 %a to i64
%cmp = icmp ugt i32 %a, 2
@@ -378,8 +378,8 @@ define i64 @umin_sext2(i32 %a) {
define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_sext2_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
-; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
%cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2>
@@ -390,8 +390,8 @@ define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
define i64 @umax_zext(i32 %a) {
; CHECK-LABEL: @umax_zext(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 3)
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MAX]]
;
%a_ext = zext i32 %a to i64
%cmp = icmp ugt i32 %a, 2
@@ -402,8 +402,8 @@ define i64 @umax_zext(i32 %a) {
define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_zext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 3, i32 3>)
-; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = zext <2 x i32> %a to <2 x i64>
%cmp = icmp ugt <2 x i32> %a, <i32 2, i32 2>
@@ -414,8 +414,8 @@ define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
define i64 @umin_zext(i32 %a) {
; CHECK-LABEL: @umin_zext(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MIN]]
;
%a_ext = zext i32 %a to i64
%cmp = icmp ult i32 %a, 3
@@ -426,8 +426,8 @@ define i64 @umin_zext(i32 %a) {
define <2 x i64> @umin_zext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_zext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A:%.*]], <2 x i32> <i32 2, i32 2>)
-; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = zext <2 x i32> %a to <2 x i64>
%cmp = icmp ult <2 x i32> %a, <i32 3, i32 3>
diff --git a/llvm/test/Transforms/InstCombine/align-addr.ll b/llvm/test/Transforms/InstCombine/align-addr.ll
index a53da0bc5a20a..0b935b51c7ba3 100644
--- a/llvm/test/Transforms/InstCombine/align-addr.ll
+++ b/llvm/test/Transforms/InstCombine/align-addr.ll
@@ -112,7 +112,7 @@ define void @test3(ptr sret(%struct.s) %a4) {
; Check that the alignment is bumped up the alignment of the sret type.
; CHECK-LABEL: @test3(
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) [[A4:%.*]], i8 0, i64 16, i1 false)
-; CHECK-NEXT: call void @use(ptr [[A4:%.*]])
+; CHECK-NEXT: call void @use(ptr [[A4]])
; CHECK-NEXT: ret void
;
call void @llvm.memset.p0.i64(ptr %a4, i8 0, i64 16, i1 false)
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll b/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
index f181ba8a6fe4b..d533cc7048536 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmp-nullptr.ll
@@ -570,8 +570,8 @@ define i1 @sgt_and_min(ptr %x, ptr %y) {
; CHECK-LABEL: @sgt_and_min(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sgt ptr %x, %y
%cmpeq = icmp eq ptr %x, null
@@ -583,8 +583,8 @@ define i1 @sgt_and_min_logical(ptr %x, ptr %y) {
; CHECK-LABEL: @sgt_and_min_logical(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sgt ptr %x, %y
%cmpeq = icmp eq ptr %x, null
@@ -596,8 +596,8 @@ define i1 @sle_or_not_min(ptr %x, ptr %y) {
; CHECK-LABEL: @sle_or_not_min(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp ne ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp sge ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sle ptr %x, %y
%cmpeq = icmp ne ptr %x, null
@@ -609,8 +609,8 @@ define i1 @sle_or_not_min_logical(ptr %x, ptr %y) {
; CHECK-LABEL: @sle_or_not_min_logical(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp ne ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp sge ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sle ptr %x, %y
%cmpeq = icmp ne ptr %x, null
@@ -622,8 +622,8 @@ define i1 @sle_and_min(ptr %x, ptr %y) {
; CHECK-LABEL: @sle_and_min(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp sge ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sle ptr %x, %y
%cmpeq = icmp eq ptr %x, null
@@ -635,8 +635,8 @@ define i1 @sle_and_min_logical(ptr %x, ptr %y) {
; CHECK-LABEL: @sle_and_min_logical(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp sge ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sle ptr %x, %y
%cmpeq = icmp eq ptr %x, null
@@ -674,8 +674,8 @@ define i1 @sgt_or_not_min(ptr %x, ptr %y) {
; CHECK-LABEL: @sgt_or_not_min(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp ne ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sgt ptr %x, %y
%cmpeq = icmp ne ptr %x, null
@@ -687,8 +687,8 @@ define i1 @sgt_or_not_min_logical(ptr %x, ptr %y) {
; CHECK-LABEL: @sgt_or_not_min_logical(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp ne ptr [[X:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt ptr [[Y:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp sgt ptr %x, %y
%cmpeq = icmp ne ptr %x, null
@@ -700,8 +700,8 @@ define i1 @slt_and_min(ptr %a, ptr %b) {
; CHECK-LABEL: @slt_and_min(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq ptr [[A:%.*]], null
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt ptr [[B:%.*]], null
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[CMPEQ]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmpeq = icmp eq ptr %a, null
%cmp = icmp slt ptr %a, %b
@@ -712,8 +712,8 @@ define i1 @slt_and_min(ptr %a, ptr %b) {
define i1 @slt_and_min_logical(ptr %a, ptr %b) {
; CHECK-LABEL: @slt_and_min_logical(
; CHECK-NEXT: [[CMPEQ:%.*]] = icmp eq ptr [[A:%.*]], null
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt ptr [[B:%.*]], null
-; CHECK-NEXT: [[R:%.*]] = select i1 [[CMPEQ]], i1 [[CMP]], i1 false
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt ptr [[B:%.*]], null
+; CHECK-NEXT: [[R:%.*]] = select i1 [[CMPEQ]], i1 [[TMP1]], i1 false
; CHECK-NEXT: ret i1 [[R]]
;
%cmpeq = icmp eq ptr %a, null
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
index 593ceff9b3440..163b13a266cf7 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -51,8 +51,8 @@ define i1 @PR1817_2_logical(i32 %X) {
define i1 @PR2330(i32 %a, i32 %b) {
; CHECK-LABEL: @PR2330(
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 8
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i32 [[TMP1]], 8
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ult i32 %a, 8
%cmp2 = icmp ult i32 %b, 8
@@ -80,8 +80,8 @@ define i1 @PR2330_logical(i32 %a, i32 %b) {
define i1 @or_eq_with_one_bit_
diff _constants1(i32 %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants1(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 50
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 50
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i32 %x, 50
%cmp2 = icmp eq i32 %x, 51
@@ -92,8 +92,8 @@ define i1 @or_eq_with_one_bit_
diff _constants1(i32 %x) {
define i1 @or_eq_with_one_bit_
diff _constants1_logical(i32 %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants1_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 50
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 50
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i32 %x, 50
%cmp2 = icmp eq i32 %x, 51
@@ -106,8 +106,8 @@ define i1 @or_eq_with_one_bit_
diff _constants1_logical(i32 %x) {
define i1 @and_ne_with_one_bit_
diff _constants1(i32 %x) {
; CHECK-LABEL: @and_ne_with_one_bit_
diff _constants1(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -52
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i32 %x, 51
%cmp2 = icmp ne i32 %x, 50
@@ -118,8 +118,8 @@ define i1 @and_ne_with_one_bit_
diff _constants1(i32 %x) {
define i1 @and_ne_with_one_bit_
diff _constants1_logical(i32 %x) {
; CHECK-LABEL: @and_ne_with_one_bit_
diff _constants1_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -52
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i32 %x, 51
%cmp2 = icmp ne i32 %x, 50
@@ -132,8 +132,8 @@ define i1 @and_ne_with_one_bit_
diff _constants1_logical(i32 %x) {
define i1 @or_eq_with_one_bit_
diff _constants2(i32 %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants2(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -33
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 65
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 65
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i32 %x, 97
%cmp2 = icmp eq i32 %x, 65
@@ -144,8 +144,8 @@ define i1 @or_eq_with_one_bit_
diff _constants2(i32 %x) {
define i1 @or_eq_with_one_bit_
diff _constants2_logical(i32 %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants2_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -33
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 65
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 65
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i32 %x, 97
%cmp2 = icmp eq i32 %x, 65
@@ -156,8 +156,8 @@ define i1 @or_eq_with_one_bit_
diff _constants2_logical(i32 %x) {
define i1 @and_ne_with_one_bit_
diff _constants2(i19 %x) {
; CHECK-LABEL: @and_ne_with_one_bit_
diff _constants2(
; CHECK-NEXT: [[TMP1:%.*]] = and i19 [[X:%.*]], -129
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i19 [[TMP1]], 65
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ne i19 [[TMP1]], 65
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i19 %x, 65
%cmp2 = icmp ne i19 %x, 193
@@ -168,8 +168,8 @@ define i1 @and_ne_with_one_bit_
diff _constants2(i19 %x) {
define i1 @and_ne_with_one_bit_
diff _constants2_logical(i19 %x) {
; CHECK-LABEL: @and_ne_with_one_bit_
diff _constants2_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i19 [[X:%.*]], -129
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i19 [[TMP1]], 65
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ne i19 [[TMP1]], 65
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i19 %x, 65
%cmp2 = icmp ne i19 %x, 193
@@ -182,8 +182,8 @@ define i1 @and_ne_with_one_bit_
diff _constants2_logical(i19 %x) {
define i1 @or_eq_with_one_bit_
diff _constants3(i8 %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants3(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 126
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i8 [[TMP1]], 126
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i8 %x, 254
%cmp2 = icmp eq i8 %x, 126
@@ -194,8 +194,8 @@ define i1 @or_eq_with_one_bit_
diff _constants3(i8 %x) {
define i1 @or_eq_with_one_bit_
diff _constants3_logical(i8 %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants3_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 126
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i8 [[TMP1]], 126
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i8 %x, 254
%cmp2 = icmp eq i8 %x, 126
@@ -206,8 +206,8 @@ define i1 @or_eq_with_one_bit_
diff _constants3_logical(i8 %x) {
define i1 @and_ne_with_one_bit_
diff _constants3(i8 %x) {
; CHECK-LABEL: @and_ne_with_one_bit_
diff _constants3(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 65
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ne i8 [[TMP1]], 65
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i8 %x, 65
%cmp2 = icmp ne i8 %x, 193
@@ -218,8 +218,8 @@ define i1 @and_ne_with_one_bit_
diff _constants3(i8 %x) {
define i1 @and_ne_with_one_bit_
diff _constants3_logical(i8 %x) {
; CHECK-LABEL: @and_ne_with_one_bit_
diff _constants3_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 65
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ne i8 [[TMP1]], 65
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i8 %x, 65
%cmp2 = icmp ne i8 %x, 193
@@ -233,8 +233,8 @@ define i1 @and_ne_with_one_bit_
diff _constants3_logical(i8 %x) {
define i1 @or_eq_with_
diff _one(i8 %x) {
; CHECK-LABEL: @or_eq_with_
diff _one(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -13
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i8 [[TMP1]], 2
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i8 %x, 13
%cmp2 = icmp eq i8 %x, 14
@@ -245,8 +245,8 @@ define i1 @or_eq_with_
diff _one(i8 %x) {
define i1 @or_eq_with_
diff _one_logical(i8 %x) {
; CHECK-LABEL: @or_eq_with_
diff _one_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -13
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i8 [[TMP1]], 2
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i8 %x, 13
%cmp2 = icmp eq i8 %x, 14
@@ -259,8 +259,8 @@ define i1 @or_eq_with_
diff _one_logical(i8 %x) {
define i1 @and_ne_with_
diff _one(i32 %x) {
; CHECK-LABEL: @and_ne_with_
diff _one(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -41
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i32 %x, 40
%cmp2 = icmp ne i32 %x, 39
@@ -271,8 +271,8 @@ define i1 @and_ne_with_
diff _one(i32 %x) {
define i1 @and_ne_with_
diff _one_logical(i32 %x) {
; CHECK-LABEL: @and_ne_with_
diff _one_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -41
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i32 %x, 40
%cmp2 = icmp ne i32 %x, 39
@@ -286,8 +286,8 @@ define i1 @and_ne_with_
diff _one_logical(i32 %x) {
define i1 @or_eq_with_
diff _one_signed(i32 %x) {
; CHECK-LABEL: @or_eq_with_
diff _one_signed(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i32 %x, 0
%cmp2 = icmp eq i32 %x, -1
@@ -298,8 +298,8 @@ define i1 @or_eq_with_
diff _one_signed(i32 %x) {
define i1 @or_eq_with_
diff _one_signed_logical(i32 %x) {
; CHECK-LABEL: @or_eq_with_
diff _one_signed_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp eq i32 %x, 0
%cmp2 = icmp eq i32 %x, -1
@@ -310,8 +310,8 @@ define i1 @or_eq_with_
diff _one_signed_logical(i32 %x) {
define i1 @and_ne_with_
diff _one_signed(i64 %x) {
; CHECK-LABEL: @and_ne_with_
diff _one_signed(
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[X:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i64 [[TMP1]], -2
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i64 %x, -1
%cmp2 = icmp ne i64 %x, 0
@@ -322,8 +322,8 @@ define i1 @and_ne_with_
diff _one_signed(i64 %x) {
define i1 @and_ne_with_
diff _one_signed_logical(i64 %x) {
; CHECK-LABEL: @and_ne_with_
diff _one_signed_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[X:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i64 [[TMP1]], -2
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp ne i64 %x, -1
%cmp2 = icmp ne i64 %x, 0
@@ -336,8 +336,8 @@ define i1 @and_ne_with_
diff _one_signed_logical(i64 %x) {
define <2 x i1> @or_eq_with_one_bit_
diff _constants2_splatvec(<2 x i32> %x) {
; CHECK-LABEL: @or_eq_with_one_bit_
diff _constants2_splatvec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -33, i32 -33>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 65, i32 65>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 65, i32 65>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%cmp1 = icmp eq <2 x i32> %x, <i32 97, i32 97>
%cmp2 = icmp eq <2 x i32> %x, <i32 65, i32 65>
@@ -348,8 +348,8 @@ define <2 x i1> @or_eq_with_one_bit_
diff _constants2_splatvec(<2 x i32> %x) {
define <2 x i1> @and_ne_with_
diff _one_splatvec(<2 x i32> %x) {
; CHECK-LABEL: @and_ne_with_
diff _one_splatvec(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -41, i32 -41>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -2, i32 -2>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -2, i32 -2>
+; CHECK-NEXT: ret <2 x i1> [[AND]]
;
%cmp1 = icmp ne <2 x i32> %x, <i32 40, i32 40>
%cmp2 = icmp ne <2 x i32> %x, <i32 39, i32 39>
@@ -420,8 +420,8 @@ define void @simplify_before_foldAndOfICmps() {
define i1 @PR42691_1(i32 %x) {
; CHECK-LABEL: @PR42691_1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp slt i32 %x, 0
%c2 = icmp eq i32 %x, 2147483647
@@ -431,8 +431,8 @@ define i1 @PR42691_1(i32 %x) {
define i1 @PR42691_1_logical(i32 %x) {
; CHECK-LABEL: @PR42691_1_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp slt i32 %x, 0
%c2 = icmp eq i32 %x, 2147483647
@@ -442,8 +442,8 @@ define i1 @PR42691_1_logical(i32 %x) {
define i1 @PR42691_2(i32 %x) {
; CHECK-LABEL: @PR42691_2(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], -2
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp ult i32 %x, 2147483648
%c2 = icmp eq i32 %x, 4294967295
@@ -453,8 +453,8 @@ define i1 @PR42691_2(i32 %x) {
define i1 @PR42691_2_logical(i32 %x) {
; CHECK-LABEL: @PR42691_2_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], -2
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp ult i32 %x, 2147483648
%c2 = icmp eq i32 %x, 4294967295
@@ -464,8 +464,8 @@ define i1 @PR42691_2_logical(i32 %x) {
define i1 @PR42691_3(i32 %x) {
; CHECK-LABEL: @PR42691_3(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sge i32 %x, 0
%c2 = icmp eq i32 %x, -2147483648
@@ -475,8 +475,8 @@ define i1 @PR42691_3(i32 %x) {
define i1 @PR42691_3_logical(i32 %x) {
; CHECK-LABEL: @PR42691_3_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sge i32 %x, 0
%c2 = icmp eq i32 %x, -2147483648
@@ -486,8 +486,8 @@ define i1 @PR42691_3_logical(i32 %x) {
define i1 @PR42691_4(i32 %x) {
; CHECK-LABEL: @PR42691_4(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, 2147483648
%c2 = icmp eq i32 %x, 0
@@ -497,8 +497,8 @@ define i1 @PR42691_4(i32 %x) {
define i1 @PR42691_4_logical(i32 %x) {
; CHECK-LABEL: @PR42691_4_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, 2147483648
%c2 = icmp eq i32 %x, 0
@@ -509,8 +509,8 @@ define i1 @PR42691_4_logical(i32 %x) {
define i1 @PR42691_5(i32 %x) {
; CHECK-LABEL: @PR42691_5(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -2147483647
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp slt i32 %x, 1
%c2 = icmp eq i32 %x, 2147483647
@@ -521,8 +521,8 @@ define i1 @PR42691_5(i32 %x) {
define i1 @PR42691_5_logical(i32 %x) {
; CHECK-LABEL: @PR42691_5_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -2147483647
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp slt i32 %x, 1
%c2 = icmp eq i32 %x, 2147483647
@@ -533,8 +533,8 @@ define i1 @PR42691_5_logical(i32 %x) {
define i1 @PR42691_6(i32 %x) {
; CHECK-LABEL: @PR42691_6(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp ult i32 %x, 2147483649
%c2 = icmp eq i32 %x, 4294967295
@@ -545,8 +545,8 @@ define i1 @PR42691_6(i32 %x) {
define i1 @PR42691_6_logical(i32 %x) {
; CHECK-LABEL: @PR42691_6_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp ult i32 %x, 2147483649
%c2 = icmp eq i32 %x, 4294967295
@@ -557,8 +557,8 @@ define i1 @PR42691_6_logical(i32 %x) {
define i1 @PR42691_7(i32 %x) {
; CHECK-LABEL: @PR42691_7(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, 2147483649
%c2 = icmp eq i32 %x, 0
@@ -569,8 +569,8 @@ define i1 @PR42691_7(i32 %x) {
define i1 @PR42691_7_logical(i32 %x) {
; CHECK-LABEL: @PR42691_7_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp uge i32 %x, 2147483649
%c2 = icmp eq i32 %x, 0
@@ -581,8 +581,8 @@ define i1 @PR42691_7_logical(i32 %x) {
define i1 @PR42691_8(i32 %x) {
; CHECK-LABEL: @PR42691_8(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483635
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483635
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp slt i32 %x, 14
%c2 = icmp ne i32 %x, -2147483648
@@ -593,8 +593,8 @@ define i1 @PR42691_8(i32 %x) {
define i1 @PR42691_8_logical(i32 %x) {
; CHECK-LABEL: @PR42691_8_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483635
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483635
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp slt i32 %x, 14
%c2 = icmp ne i32 %x, -2147483648
@@ -605,8 +605,8 @@ define i1 @PR42691_8_logical(i32 %x) {
define i1 @PR42691_9(i32 %x) {
; CHECK-LABEL: @PR42691_9(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2147483633
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], 2147483633
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sgt i32 %x, 13
%c2 = icmp ne i32 %x, 2147483647
@@ -617,8 +617,8 @@ define i1 @PR42691_9(i32 %x) {
define i1 @PR42691_9_logical(i32 %x) {
; CHECK-LABEL: @PR42691_9_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2147483633
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], 2147483633
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp sgt i32 %x, 13
%c2 = icmp ne i32 %x, 2147483647
@@ -629,8 +629,8 @@ define i1 @PR42691_9_logical(i32 %x) {
define i1 @PR42691_10(i32 %x) {
; CHECK-LABEL: @PR42691_10(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -15
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -15
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp ugt i32 %x, 13
%c2 = icmp ne i32 %x, 4294967295
@@ -641,8 +641,8 @@ define i1 @PR42691_10(i32 %x) {
define i1 @PR42691_10_logical(i32 %x) {
; CHECK-LABEL: @PR42691_10_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -15
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -15
+; CHECK-NEXT: ret i1 [[C]]
;
%c1 = icmp ugt i32 %x, 13
%c2 = icmp ne i32 %x, 4294967295
@@ -654,8 +654,8 @@ define i1 @substitute_constant_and_eq_eq(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_and_eq_eq(
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
%c2 = icmp eq i8 %x, %y
@@ -667,8 +667,8 @@ define i1 @substitute_constant_and_eq_eq_logical(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_and_eq_eq_logical(
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
%c2 = icmp eq i8 %x, %y
@@ -680,8 +680,8 @@ define i1 @substitute_constant_and_eq_eq_commute(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_and_eq_eq_commute(
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
%c2 = icmp eq i8 %x, %y
@@ -693,8 +693,8 @@ define i1 @substitute_constant_and_eq_eq_commute_logical(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_and_eq_eq_commute_logical(
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
%c2 = icmp eq i8 %x, %y
@@ -706,8 +706,8 @@ define i1 @substitute_constant_and_eq_ugt_swap(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_and_eq_ugt_swap(
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
%c2 = icmp ugt i8 %y, %x
@@ -719,8 +719,8 @@ define i1 @substitute_constant_and_eq_ugt_swap_logical(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_and_eq_ugt_swap_logical(
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
%c2 = icmp ugt i8 %y, %x
@@ -732,8 +732,8 @@ define <2 x i1> @substitute_constant_and_eq_ne_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @substitute_constant_and_eq_ne_vec(
; CHECK-NEXT: [[C1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 42, i8 97>
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i8> [[Y:%.*]], <i8 42, i8 97>
-; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i1> [[C1]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[C1]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
;
%c1 = icmp eq <2 x i8> %x, <i8 42, i8 97>
%c2 = icmp ne <2 x i8> %x, %y
@@ -745,8 +745,8 @@ define <2 x i1> @substitute_constant_and_eq_ne_vec_logical(<2 x i8> %x, <2 x i8>
; CHECK-LABEL: @substitute_constant_and_eq_ne_vec_logical(
; CHECK-NEXT: [[C1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 42, i8 97>
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i8> [[Y:%.*]], <i8 42, i8 97>
-; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[C1]], <2 x i1> [[TMP1]], <2 x i1> zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C1]], <2 x i1> [[TMP1]], <2 x i1> zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[R]]
;
%c1 = icmp eq <2 x i8> %x, <i8 42, i8 97>
%c2 = icmp ne <2 x i8> %x, %y
@@ -759,8 +759,8 @@ define i1 @substitute_constant_and_eq_sgt_use(i8 %x, i8 %y) {
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: call void @use(i1 [[C1]])
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
call void @use(i1 %c1)
@@ -774,8 +774,8 @@ define i1 @substitute_constant_and_eq_sgt_use_logical(i8 %x, i8 %y) {
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
; CHECK-NEXT: call void @use(i1 [[C1]])
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 42
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp eq i8 %x, 42
call void @use(i1 %c1)
@@ -906,8 +906,8 @@ define i1 @substitute_constant_or_ne_swap_sle(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_or_ne_swap_sle(
; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp ne i8 %x, 42
%c2 = icmp sle i8 %y, %x
@@ -919,8 +919,8 @@ define i1 @substitute_constant_or_ne_swap_sle_logical(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_or_ne_swap_sle_logical(
; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp ne i8 %x, 42
%c2 = icmp sle i8 %y, %x
@@ -932,8 +932,8 @@ define i1 @substitute_constant_or_ne_uge_commute(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_or_ne_uge_commute(
; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[Y:%.*]], 43
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp ne i8 %x, 42
%c2 = icmp uge i8 %x, %y
@@ -945,8 +945,8 @@ define i1 @substitute_constant_or_ne_uge_commute_logical(i8 %x, i8 %y) {
; CHECK-LABEL: @substitute_constant_or_ne_uge_commute_logical(
; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[Y:%.*]], 43
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp ne i8 %x, 42
%c2 = icmp uge i8 %x, %y
@@ -1013,8 +1013,8 @@ define i1 @substitute_constant_or_ne_sge_use(i8 %x, i8 %y) {
; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
; CHECK-NEXT: call void @use(i1 [[C1]])
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp ne i8 %x, 42
call void @use(i1 %c1)
@@ -1028,8 +1028,8 @@ define i1 @substitute_constant_or_ne_sge_use_logical(i8 %x, i8 %y) {
; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
; CHECK-NEXT: call void @use(i1 [[C1]])
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
;
%c1 = icmp ne i8 %x, 42
call void @use(i1 %c1)
@@ -1073,8 +1073,8 @@ define i1 @substitute_constant_or_ne_ule_use2_logical(i8 %x, i8 %y) {
define i1 @or_ranges_overlap(i8 %x) {
; CHECK-LABEL: @or_ranges_overlap(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 16
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C7:%.*]] = icmp ult i8 [[TMP1]], 16
+; CHECK-NEXT: ret i1 [[C7]]
;
%c1 = icmp uge i8 %x, 5
%c2 = icmp ule i8 %x, 10
@@ -1089,8 +1089,8 @@ define i1 @or_ranges_overlap(i8 %x) {
define i1 @or_ranges_adjacent(i8 %x) {
; CHECK-LABEL: @or_ranges_adjacent(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 16
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C7:%.*]] = icmp ult i8 [[TMP1]], 16
+; CHECK-NEXT: ret i1 [[C7]]
;
%c1 = icmp uge i8 %x, 5
%c2 = icmp ule i8 %x, 10
@@ -1105,10 +1105,10 @@ define i1 @or_ranges_adjacent(i8 %x) {
define i1 @or_ranges_separated(i8 %x) {
; CHECK-LABEL: @or_ranges_separated(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
-; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[X]], -12
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 9
-; CHECK-NEXT: [[C7:%.*]] = or i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: [[C3:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[X]], -12
+; CHECK-NEXT: [[C6:%.*]] = icmp ult i8 [[TMP2]], 9
+; CHECK-NEXT: [[C7:%.*]] = or i1 [[C3]], [[C6]]
; CHECK-NEXT: ret i1 [[C7]]
;
%c1 = icmp uge i8 %x, 5
@@ -1124,8 +1124,8 @@ define i1 @or_ranges_separated(i8 %x) {
define i1 @or_ranges_single_elem_right(i8 %x) {
; CHECK-LABEL: @or_ranges_single_elem_right(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 7
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C6:%.*]] = icmp ult i8 [[TMP1]], 7
+; CHECK-NEXT: ret i1 [[C6]]
;
%c1 = icmp uge i8 %x, 5
%c2 = icmp ule i8 %x, 10
@@ -1138,8 +1138,8 @@ define i1 @or_ranges_single_elem_right(i8 %x) {
define i1 @or_ranges_single_elem_left(i8 %x) {
; CHECK-LABEL: @or_ranges_single_elem_left(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -4
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 7
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C6:%.*]] = icmp ult i8 [[TMP1]], 7
+; CHECK-NEXT: ret i1 [[C6]]
;
%c1 = icmp uge i8 %x, 5
%c2 = icmp ule i8 %x, 10
@@ -1152,8 +1152,8 @@ define i1 @or_ranges_single_elem_left(i8 %x) {
define i1 @and_ranges_overlap(i8 %x) {
; CHECK-LABEL: @and_ranges_overlap(
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], -7
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 4
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[C7:%.*]] = icmp ult i8 [[TMP1]], 4
+; CHECK-NEXT: ret i1 [[C7]]
;
%c1 = icmp uge i8 %x, 5
%c2 = icmp ule i8 %x, 10
@@ -1167,8 +1167,8 @@ define i1 @and_ranges_overlap(i8 %x) {
define i1 @and_ranges_overlap_single(i8 %x) {
; CHECK-LABEL: @and_ranges_overlap_single(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], 10
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C7:%.*]] = icmp eq i8 [[X:%.*]], 10
+; CHECK-NEXT: ret i1 [[C7]]
;
%c1 = icmp uge i8 %x, 5
%c2 = icmp ule i8 %x, 10
@@ -1197,8 +1197,8 @@ define i1 @and_ranges_no_overlap(i8 %x) {
define i1 @and_ranges_signed_pred(i64 %x) {
; CHECK-LABEL: @and_ranges_signed_pred(
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[X:%.*]], -9223372036854775681
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -9223372036854775553
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ult i64 [[TMP1]], -9223372036854775553
+; CHECK-NEXT: ret i1 [[T5]]
;
%t1 = add i64 %x, 127
%t2 = icmp slt i64 %t1, 1024
@@ -1212,8 +1212,8 @@ define i1 @and_two_ranges_to_mask_and_range(i8 %c) {
; CHECK-LABEL: @and_two_ranges_to_mask_and_range(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -91
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], -26
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ult i8 [[TMP2]], -26
+; CHECK-NEXT: ret i1 [[AND]]
;
%c.off = add i8 %c, -97
%cmp1 = icmp ugt i8 %c.off, 25
@@ -1260,8 +1260,8 @@ define i1 @and_two_ranges_to_mask_and_range_
diff erent_sizes(i8 %c) {
define i1 @and_two_ranges_to_mask_and_range_no_add_on_one_range(i16 %x) {
; CHECK-LABEL: @and_two_ranges_to_mask_and_range_no_add_on_one_range(
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[X:%.*]], -20
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i16 [[TMP1]], 11
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND:%.*]] = icmp ugt i16 [[TMP1]], 11
+; CHECK-NEXT: ret i1 [[AND]]
;
%cmp1 = icmp uge i16 %x, 12
%cmp2 = icmp ult i16 %x, 16
@@ -1278,8 +1278,8 @@ define i1 @is_ascii_alphabetic(i32 %char) {
; CHECK-LABEL: @is_ascii_alphabetic(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[CHAR:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -65
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 26
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[LOGICAL:%.*]] = icmp ult i32 [[TMP2]], 26
+; CHECK-NEXT: ret i1 [[LOGICAL]]
;
%add1 = add nsw i32 %char, -65
%cmp1 = icmp ult i32 %add1, 26
@@ -1293,8 +1293,8 @@ define i1 @is_ascii_alphabetic_inverted(i32 %char) {
; CHECK-LABEL: @is_ascii_alphabetic_inverted(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[CHAR:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -91
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], -26
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[LOGICAL:%.*]] = icmp ult i32 [[TMP2]], -26
+; CHECK-NEXT: ret i1 [[LOGICAL]]
;
%add1 = add nsw i32 %char, -91
%cmp1 = icmp ult i32 %add1, -26
@@ -1311,8 +1311,8 @@ define i1 @bitwise_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[C1]], [[TMP3]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = and i1 [[C1]], [[TMP3]]
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1332,8 +1332,8 @@ define i1 @bitwise_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[C1]], [[TMP3]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = and i1 [[C1]], [[TMP3]]
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1353,8 +1353,8 @@ define i1 @bitwise_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP3]], [[C1]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = and i1 [[TMP3]], [[C1]]
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1374,8 +1374,8 @@ define i1 @bitwise_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP3]], [[C1]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = and i1 [[TMP3]], [[C1]]
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1395,8 +1395,8 @@ define i1 @bitwise_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1416,8 +1416,8 @@ define i1 @bitwise_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1438,8 +1438,8 @@ define i1 @bitwise_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], [[X:%.*]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i8 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i1 [[C1]], i1 false
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP4]], i1 [[C1]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1459,8 +1459,8 @@ define i1 @bitwise_and_logical_and_icmps_comm3(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[C1]], i1 false
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP3]], i1 [[C1]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1662,8 +1662,8 @@ define i1 @bitwise_or_bitwise_or_icmps(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[C1]], [[TMP3]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = or i1 [[C1]], [[TMP3]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1683,8 +1683,8 @@ define i1 @bitwise_or_bitwise_or_icmps_comm1(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[C1]], [[TMP3]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = or i1 [[C1]], [[TMP3]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1704,8 +1704,8 @@ define i1 @bitwise_or_bitwise_or_icmps_comm2(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[C1]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = or i1 [[TMP3]], [[C1]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1725,8 +1725,8 @@ define i1 @bitwise_or_bitwise_or_icmps_comm3(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[C1]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = or i1 [[TMP3]], [[C1]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1746,8 +1746,8 @@ define i1 @bitwise_or_logical_or_icmps(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1767,8 +1767,8 @@ define i1 @bitwise_or_logical_or_icmps_comm1(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1789,8 +1789,8 @@ define i1 @bitwise_or_logical_or_icmps_comm2(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 1
; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], [[X:%.*]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i1 true, i1 [[C1]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[OR2:%.*]] = select i1 [[TMP4]], i1 true, i1 [[C1]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -1810,8 +1810,8 @@ define i1 @bitwise_or_logical_or_icmps_comm3(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i1 true, i1 [[C1]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR2:%.*]] = select i1 [[TMP3]], i1 true, i1 [[C1]]
+; CHECK-NEXT: ret i1 [[OR2]]
;
%c1 = icmp eq i8 %y, 42
%x.m1 = and i8 %x, 1
@@ -2010,8 +2010,8 @@ define i1 @bitwise_and_logical_and_masked_icmp_asymmetric(i1 %c, i32 %x) {
; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_asymmetric(
; CHECK-NEXT: [[X_M2:%.*]] = and i32 [[X:%.*]], 11
; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[X_M2]], 11
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C2]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C2]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%x.m1 = and i32 %x, 255
%c1 = icmp ne i32 %x.m1, 0
@@ -2026,8 +2026,8 @@ define i1 @bitwise_and_logical_and_masked_icmp_allzeros(i1 %c, i32 %x) {
; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allzeros(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%x.m1 = and i32 %x, 8
%c1 = icmp eq i32 %x.m1, 0
@@ -2043,8 +2043,8 @@ define i1 @bitwise_and_logical_and_masked_icmp_allzeros_poison1(i1 %c, i32 %x, i
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[Y:%.*]], 7
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP3]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%x.m1 = and i32 %x, %y
%c1 = icmp eq i32 %x.m1, 0
@@ -2078,8 +2078,8 @@ define i1 @bitwise_and_logical_and_masked_icmp_allones(i1 %c, i32 %x) {
; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allones(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 15
-; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%x.m1 = and i32 %x, 8
%c1 = icmp eq i32 %x.m1, 8
@@ -2095,8 +2095,8 @@ define i1 @bitwise_and_logical_and_masked_icmp_allones_poison1(i1 %c, i32 %x, i3
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[Y:%.*]], 7
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP3]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%x.m1 = and i32 %x, %y
%c1 = icmp eq i32 %x.m1, %y
@@ -2129,8 +2129,8 @@ define i1 @bitwise_and_logical_and_masked_icmp_allones_poison2(i1 %c, i32 %x, i3
define i1 @samesign(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%lt = icmp slt i32 %a, 0
@@ -2143,8 +2143,8 @@ define i1 @samesign(i32 %x, i32 %y) {
define <2 x i1> @samesign_
diff erent_sign_bittest1(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @samesign_
diff erent_sign_bittest1(
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i32> [[TMP1]], <i32 -1, i32 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i32> [[TMP1]], <i32 -1, i32 -1>
+; CHECK-NEXT: ret <2 x i1> [[R]]
;
%a = and <2 x i32> %x, %y
%lt = icmp sle <2 x i32> %a, <i32 -1, i32 -1>
@@ -2157,8 +2157,8 @@ define <2 x i1> @samesign_
diff erent_sign_bittest1(<2 x i32> %x, <2 x i32> %y) {
define i1 @samesign_
diff erent_sign_bittest2(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_
diff erent_sign_bittest2(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%lt = icmp slt i32 %a, 0
@@ -2171,8 +2171,8 @@ define i1 @samesign_
diff erent_sign_bittest2(i32 %x, i32 %y) {
define i1 @samesign_commute1(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_commute1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%lt = icmp slt i32 %a, 0
@@ -2185,8 +2185,8 @@ define i1 @samesign_commute1(i32 %x, i32 %y) {
define i1 @samesign_commute2(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_commute2(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%lt = icmp slt i32 %a, 0
@@ -2199,8 +2199,8 @@ define i1 @samesign_commute2(i32 %x, i32 %y) {
define i1 @samesign_commute3(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_commute3(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%lt = icmp slt i32 %a, 0
@@ -2251,8 +2251,8 @@ define i1 @samesign_mult_use(i32 %x, i32 %y) {
; CHECK-NEXT: [[O:%.*]] = or i32 [[X]], [[Y]]
; CHECK-NEXT: call void @use32(i32 [[O]])
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
call void @use32(i32 %a)
@@ -2270,8 +2270,8 @@ define i1 @samesign_mult_use2(i32 %x, i32 %y) {
; CHECK-NEXT: [[GT:%.*]] = icmp sgt i32 [[O]], -1
; CHECK-NEXT: call void @use(i1 [[GT]])
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%lt = icmp slt i32 %a, 0
@@ -2323,8 +2323,8 @@ define i1 @samesign_wrong_cmp(i32 %x, i32 %y) {
define i1 @samesign_inverted(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_inverted(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%gt = icmp sgt i32 %a, -1
@@ -2337,8 +2337,8 @@ define i1 @samesign_inverted(i32 %x, i32 %y) {
define i1 @samesign_inverted_
diff erent_sign_bittest1(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_inverted_
diff erent_sign_bittest1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%gt = icmp sge i32 %a, 0
@@ -2351,8 +2351,8 @@ define i1 @samesign_inverted_
diff erent_sign_bittest1(i32 %x, i32 %y) {
define i1 @samesign_inverted_
diff erent_sign_bittest2(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_inverted_
diff erent_sign_bittest2(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%gt = icmp sgt i32 %a, -1
@@ -2365,8 +2365,8 @@ define i1 @samesign_inverted_
diff erent_sign_bittest2(i32 %x, i32 %y) {
define i1 @samesign_inverted_commute1(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_inverted_commute1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%gt = icmp sgt i32 %a, -1
@@ -2379,8 +2379,8 @@ define i1 @samesign_inverted_commute1(i32 %x, i32 %y) {
define i1 @samesign_inverted_commute2(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_inverted_commute2(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%gt = icmp sgt i32 %a, -1
@@ -2393,8 +2393,8 @@ define i1 @samesign_inverted_commute2(i32 %x, i32 %y) {
define i1 @samesign_inverted_commute3(i32 %x, i32 %y) {
; CHECK-LABEL: @samesign_inverted_commute3(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
%gt = icmp sgt i32 %a, -1
@@ -2444,8 +2444,8 @@ define i1 @samesign_inverted_mult_use(i32 %x, i32 %y) {
; CHECK-NEXT: [[O:%.*]] = or i32 [[X]], [[Y]]
; CHECK-NEXT: call void @use32(i32 [[O]])
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%a = and i32 %x, %y
call void @use32(i32 %a)
diff --git a/llvm/test/Transforms/InstCombine/and-or.ll b/llvm/test/Transforms/InstCombine/and-or.ll
index 7a37af406f9d9..65a27ecb1fa81 100644
--- a/llvm/test/Transforms/InstCombine/and-or.ll
+++ b/llvm/test/Transforms/InstCombine/and-or.ll
@@ -703,13 +703,13 @@ define { i1, i1, i1, i1, i1 } @or_or_and_noOneUse_fail2(i1 %a_0, i1 %a_1, i1 %a_
; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[A_1]]
; CHECK-NEXT: [[TMP7:%.*]] = and i1 [[TMP6]], [[B_1]]
; CHECK-NEXT: [[D:%.*]] = or i1 [[TMP7]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { i1, i1, i1, i1, i1 } zeroinitializer, i1 [[D]], 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP9]], i1 [[TMP4]], 1
-; CHECK-NEXT: [[TMP11:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP10]], i1 true, 2
-; CHECK-NEXT: [[TMP12:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP11]], i1 [[A_3]], 3
-; CHECK-NEXT: [[TMP13:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP12]], i1 [[TMP8]], 4
-; CHECK-NEXT: ret { i1, i1, i1, i1, i1 } [[TMP13]]
+; CHECK-NEXT: [[DOTNOT1:%.*]] = or i1 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { i1, i1, i1, i1, i1 } zeroinitializer, i1 [[D]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP8]], i1 [[TMP4]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP9]], i1 true, 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP10]], i1 [[A_3]], 3
+; CHECK-NEXT: [[TMP12:%.*]] = insertvalue { i1, i1, i1, i1, i1 } [[TMP11]], i1 [[DOTNOT1]], 4
+; CHECK-NEXT: ret { i1, i1, i1, i1, i1 } [[TMP12]]
;
entry:
%0 = and i1 %a_0, %b_0
diff --git a/llvm/test/Transforms/InstCombine/and-xor-merge.ll b/llvm/test/Transforms/InstCombine/and-xor-merge.ll
index baf3248e29804..543336468ff0a 100644
--- a/llvm/test/Transforms/InstCombine/and-xor-merge.ll
+++ b/llvm/test/Transforms/InstCombine/and-xor-merge.ll
@@ -29,8 +29,8 @@ define i32 @test2(i32 %x, i32 %y, i32 %z) {
define i32 @PR38781(i32 %a, i32 %b) {
; CHECK-LABEL: @PR38781(
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: [[AND2:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: [[AND:%.*]] = zext i1 [[AND2]] to i32
; CHECK-NEXT: ret i32 [[AND]]
;
%a.lobit = lshr i32 %a, 31
diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll
index 30fe059642cb4..73bdadc86710e 100644
--- a/llvm/test/Transforms/InstCombine/and2.ll
+++ b/llvm/test/Transforms/InstCombine/and2.ll
@@ -34,8 +34,8 @@ define i32 @test3(i32 %X, i32 %Y) {
define i1 @test7(i32 %i, i1 %b) {
; CHECK-LABEL: @test7(
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[AND2]]
;
%cmp1 = icmp slt i32 %i, 1
%cmp2 = icmp sgt i32 %i, -1
@@ -47,8 +47,8 @@ define i1 @test7(i32 %i, i1 %b) {
define i1 @test7_logical(i32 %i, i1 %b) {
; CHECK-LABEL: @test7_logical(
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP1]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT: ret i1 [[AND2]]
;
%cmp1 = icmp slt i32 %i, 1
%cmp2 = icmp sgt i32 %i, -1
@@ -60,8 +60,8 @@ define i1 @test7_logical(i32 %i, i1 %b) {
define i1 @test8(i32 %i) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 13
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[TMP1]], 13
+; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = icmp ne i32 %i, 0
%cmp2 = icmp ult i32 %i, 14
@@ -72,8 +72,8 @@ define i1 @test8(i32 %i) {
define i1 @test8_logical(i32 %i) {
; CHECK-LABEL: @test8_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 13
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[TMP1]], 13
+; CHECK-NEXT: ret i1 [[COND]]
;
%cmp1 = icmp ne i32 %i, 0
%cmp2 = icmp ult i32 %i, 14
@@ -84,8 +84,8 @@ define i1 @test8_logical(i32 %i) {
define <2 x i1> @test8vec(<2 x i32> %i) {
; CHECK-LABEL: @test8vec(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[I:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 13, i32 13>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[COND:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 13, i32 13>
+; CHECK-NEXT: ret <2 x i1> [[COND]]
;
%cmp1 = icmp ne <2 x i32> %i, zeroinitializer
%cmp2 = icmp ult <2 x i32> %i, <i32 14, i32 14>
diff --git a/llvm/test/Transforms/InstCombine/apint-add.ll b/llvm/test/Transforms/InstCombine/apint-add.ll
index bcd5e2ef5b3f9..c125fe7db605a 100644
--- a/llvm/test/Transforms/InstCombine/apint-add.ll
+++ b/llvm/test/Transforms/InstCombine/apint-add.ll
@@ -6,7 +6,7 @@
;; Flip sign bit then add INT_MIN -> nop.
define i1 @test1(i1 %x) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: ret i1 %x
+; CHECK-NEXT: ret i1 [[X:%.*]]
;
%tmp.2 = xor i1 %x, 1
%tmp.4 = add i1 %tmp.2, 1
@@ -16,7 +16,7 @@ define i1 @test1(i1 %x) {
;; Flip sign bit then add INT_MIN -> nop.
define i47 @test2(i47 %x) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: ret i47 %x
+; CHECK-NEXT: ret i47 [[X:%.*]]
;
%tmp.2 = xor i47 %x, 70368744177664
%tmp.4 = add i47 %tmp.2, 70368744177664
@@ -26,7 +26,7 @@ define i47 @test2(i47 %x) {
;; Flip sign bit then add INT_MIN -> nop.
define i15 @test3(i15 %x) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: ret i15 %x
+; CHECK-NEXT: ret i15 [[X:%.*]]
;
%tmp.2 = xor i15 %x, 16384
%tmp.4 = add i15 %tmp.2, 16384
@@ -36,7 +36,7 @@ define i15 @test3(i15 %x) {
; X + signbit --> X ^ signbit
define <2 x i5> @test3vec(<2 x i5> %x) {
; CHECK-LABEL: @test3vec(
-; CHECK-NEXT: [[Y:%.*]] = xor <2 x i5> %x, <i5 -16, i5 -16>
+; CHECK-NEXT: [[Y:%.*]] = xor <2 x i5> [[X:%.*]], <i5 -16, i5 -16>
; CHECK-NEXT: ret <2 x i5> [[Y]]
;
%y = add <2 x i5> %x, <i5 16, i5 16>
@@ -46,7 +46,7 @@ define <2 x i5> @test3vec(<2 x i5> %x) {
;; (x & 0b1111..0) + 1 -> x | 1
define i49 @test4(i49 %x) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[TMP_4:%.*]] = or i49 %x, 1
+; CHECK-NEXT: [[TMP_4:%.*]] = or i49 [[X:%.*]], 1
; CHECK-NEXT: ret i49 [[TMP_4]]
;
%tmp.2 = and i49 %x, 562949953421310
@@ -56,7 +56,7 @@ define i49 @test4(i49 %x) {
define i7 @sext(i4 %x) {
; CHECK-LABEL: @sext(
-; CHECK-NEXT: [[ADD:%.*]] = sext i4 %x to i7
+; CHECK-NEXT: [[ADD:%.*]] = sext i4 [[X:%.*]] to i7
; CHECK-NEXT: ret i7 [[ADD]]
;
%xor = xor i4 %x, -8
@@ -67,7 +67,7 @@ define i7 @sext(i4 %x) {
define <2 x i10> @sext_vec(<2 x i3> %x) {
; CHECK-LABEL: @sext_vec(
-; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i3> %x to <2 x i10>
+; CHECK-NEXT: [[ADD:%.*]] = sext <2 x i3> [[X:%.*]] to <2 x i10>
; CHECK-NEXT: ret <2 x i10> [[ADD]]
;
%xor = xor <2 x i3> %x, <i3 -4, i3 -4>
@@ -80,9 +80,9 @@ define <2 x i10> @sext_vec(<2 x i3> %x) {
define i4 @sext_multiuse(i4 %x) {
; CHECK-LABEL: @sext_multiuse(
-; CHECK-NEXT: [[XOR:%.*]] = xor i4 %x, -8
+; CHECK-NEXT: [[XOR:%.*]] = xor i4 [[X:%.*]], -8
; CHECK-NEXT: [[ZEXT:%.*]] = zext i4 [[XOR]] to i7
-; CHECK-NEXT: [[ADD:%.*]] = sext i4 %x to i7
+; CHECK-NEXT: [[ADD:%.*]] = sext i4 [[X]] to i7
; CHECK-NEXT: [[MUL:%.*]] = sdiv i7 [[ZEXT]], [[ADD]]
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i7 [[MUL]] to i4
; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[TRUNC]], [[XOR]]
@@ -102,7 +102,7 @@ define i4 @sext_multiuse(i4 %x) {
;; Flip sign bit then add INT_MIN -> nop.
define i111 @test5(i111 %x) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: ret i111 %x
+; CHECK-NEXT: ret i111 [[X:%.*]]
;
%tmp.2 = shl i111 1, 110
%tmp.4 = xor i111 %x, %tmp.2
@@ -113,7 +113,7 @@ define i111 @test5(i111 %x) {
;; Flip sign bit then add INT_MIN -> nop.
define i65 @test6(i65 %x) {
; CHECK-LABEL: @test6(
-; CHECK-NEXT: ret i65 %x
+; CHECK-NEXT: ret i65 [[X:%.*]]
;
%tmp.0 = shl i65 1, 64
%tmp.2 = xor i65 %x, %tmp.0
@@ -124,7 +124,7 @@ define i65 @test6(i65 %x) {
;; Flip sign bit then add INT_MIN -> nop.
define i1024 @test7(i1024 %x) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: ret i1024 %x
+; CHECK-NEXT: ret i1024 [[X:%.*]]
;
%tmp.0 = shl i1024 1, 1023
%tmp.2 = xor i1024 %x, %tmp.0
@@ -135,7 +135,7 @@ define i1024 @test7(i1024 %x) {
;; If we have add(xor(X, 0xF..F80..), 0x80..), it's an xor.
define i128 @test8(i128 %x) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[TMP_4:%.*]] = xor i128 %x, 170141183460469231731687303715884105600
+; CHECK-NEXT: [[TMP_4:%.*]] = xor i128 [[X:%.*]], 170141183460469231731687303715884105600
; CHECK-NEXT: ret i128 [[TMP_4]]
;
%tmp.5 = shl i128 1, 127
@@ -148,7 +148,7 @@ define i128 @test8(i128 %x) {
;; (x & 254)+1 -> (x & 254)|1
define i77 @test9(i77 %x) {
; CHECK-LABEL: @test9(
-; CHECK-NEXT: [[TMP_2:%.*]] = and i77 %x, 562949953421310
+; CHECK-NEXT: [[TMP_2:%.*]] = and i77 [[X:%.*]], 562949953421310
; CHECK-NEXT: [[TMP_4:%.*]] = or i77 [[TMP_2]], 1
; CHECK-NEXT: ret i77 [[TMP_4]]
;
diff --git a/llvm/test/Transforms/InstCombine/apint-select.ll b/llvm/test/Transforms/InstCombine/apint-select.ll
index dd1b0e45b9710..c96c3dc368693 100644
--- a/llvm/test/Transforms/InstCombine/apint-select.ll
+++ b/llvm/test/Transforms/InstCombine/apint-select.ll
@@ -5,7 +5,7 @@
define i41 @zext(i1 %C) {
; CHECK-LABEL: @zext(
-; CHECK-NEXT: [[V:%.*]] = zext i1 %C to i41
+; CHECK-NEXT: [[V:%.*]] = zext i1 [[C:%.*]] to i41
; CHECK-NEXT: ret i41 [[V]]
;
%V = select i1 %C, i41 1, i41 0
@@ -14,7 +14,7 @@ define i41 @zext(i1 %C) {
define i41 @sext(i1 %C) {
; CHECK-LABEL: @sext(
-; CHECK-NEXT: [[V:%.*]] = sext i1 %C to i41
+; CHECK-NEXT: [[V:%.*]] = sext i1 [[C:%.*]] to i41
; CHECK-NEXT: ret i41 [[V]]
;
%V = select i1 %C, i41 -1, i41 0
@@ -23,7 +23,7 @@ define i41 @sext(i1 %C) {
define i999 @not_zext(i1 %C) {
; CHECK-LABEL: @not_zext(
-; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 %C, true
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
; CHECK-NEXT: [[V:%.*]] = zext i1 [[NOT_C]] to i999
; CHECK-NEXT: ret i999 [[V]]
;
@@ -33,7 +33,7 @@ define i999 @not_zext(i1 %C) {
define i999 @not_sext(i1 %C) {
; CHECK-LABEL: @not_sext(
-; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 %C, true
+; CHECK-NEXT: [[NOT_C:%.*]] = xor i1 [[C:%.*]], true
; CHECK-NEXT: [[V:%.*]] = sext i1 [[NOT_C]] to i999
; CHECK-NEXT: ret i999 [[V]]
;
@@ -45,7 +45,7 @@ define i999 @not_sext(i1 %C) {
define <2 x i41> @zext_vec(<2 x i1> %C) {
; CHECK-LABEL: @zext_vec(
-; CHECK-NEXT: [[V:%.*]] = zext <2 x i1> %C to <2 x i41>
+; CHECK-NEXT: [[V:%.*]] = zext <2 x i1> [[C:%.*]] to <2 x i41>
; CHECK-NEXT: ret <2 x i41> [[V]]
;
%V = select <2 x i1> %C, <2 x i41> <i41 1, i41 1>, <2 x i41> <i41 0, i41 0>
@@ -54,7 +54,7 @@ define <2 x i41> @zext_vec(<2 x i1> %C) {
define <2 x i32> @sext_vec(<2 x i1> %C) {
; CHECK-LABEL: @sext_vec(
-; CHECK-NEXT: [[V:%.*]] = sext <2 x i1> %C to <2 x i32>
+; CHECK-NEXT: [[V:%.*]] = sext <2 x i1> [[C:%.*]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%V = select <2 x i1> %C, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 0, i32 0>
@@ -63,7 +63,7 @@ define <2 x i32> @sext_vec(<2 x i1> %C) {
define <2 x i999> @not_zext_vec(<2 x i1> %C) {
; CHECK-LABEL: @not_zext_vec(
-; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> %C, <i1 true, i1 true>
+; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true>
; CHECK-NEXT: [[V:%.*]] = zext <2 x i1> [[NOT_C]] to <2 x i999>
; CHECK-NEXT: ret <2 x i999> [[V]]
;
@@ -73,7 +73,7 @@ define <2 x i999> @not_zext_vec(<2 x i1> %C) {
define <2 x i64> @not_sext_vec(<2 x i1> %C) {
; CHECK-LABEL: @not_sext_vec(
-; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> %C, <i1 true, i1 true>
+; CHECK-NEXT: [[NOT_C:%.*]] = xor <2 x i1> [[C:%.*]], <i1 true, i1 true>
; CHECK-NEXT: [[V:%.*]] = sext <2 x i1> [[NOT_C]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[V]]
;
@@ -85,7 +85,7 @@ define <2 x i64> @not_sext_vec(<2 x i1> %C) {
define <2 x i32> @scalar_select_of_vectors(i1 %c) {
; CHECK-LABEL: @scalar_select_of_vectors(
-; CHECK-NEXT: [[V:%.*]] = select i1 %c, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%V = select i1 %c, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
@@ -96,7 +96,7 @@ define <2 x i32> @scalar_select_of_vectors(i1 %c) {
define i41 @test3(i41 %X) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i41 %X, 40
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i41 [[X:%.*]], 40
; CHECK-NEXT: ret i41 [[X_LOBIT]]
;
%t = icmp slt i41 %X, 0
@@ -108,7 +108,7 @@ define i41 @test3(i41 %X) {
define i1023 @test4(i1023 %X) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i1023 %X, 1022
+; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i1023 [[X:%.*]], 1022
; CHECK-NEXT: ret i1023 [[X_LOBIT]]
;
%t = icmp slt i1023 %X, 0
diff --git a/llvm/test/Transforms/InstCombine/apint-shift.ll b/llvm/test/Transforms/InstCombine/apint-shift.ll
index 6b5a1c8eb8fe0..cbe8ed993b400 100644
--- a/llvm/test/Transforms/InstCombine/apint-shift.ll
+++ b/llvm/test/Transforms/InstCombine/apint-shift.ll
@@ -240,8 +240,8 @@ define i23 @test11(i23 %x) {
define i47 @test12(i47 %X) {
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[TMP1:%.*]] = and i47 [[X:%.*]], -256
-; CHECK-NEXT: ret i47 [[TMP1]]
+; CHECK-NEXT: [[SH2:%.*]] = and i47 [[X:%.*]], -256
+; CHECK-NEXT: ret i47 [[SH2]]
;
%sh1 = ashr i47 %X, 8
%sh2 = shl i47 %sh1, 8
@@ -250,8 +250,8 @@ define i47 @test12(i47 %X) {
define <2 x i47> @test12_splat_vec(<2 x i47> %X) {
; CHECK-LABEL: @test12_splat_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i47> [[X:%.*]], <i47 -256, i47 -256>
-; CHECK-NEXT: ret <2 x i47> [[TMP1]]
+; CHECK-NEXT: [[SH2:%.*]] = and <2 x i47> [[X:%.*]], <i47 -256, i47 -256>
+; CHECK-NEXT: ret <2 x i47> [[SH2]]
;
%sh1 = ashr <2 x i47> %X, <i47 8, i47 8>
%sh2 = shl <2 x i47> %sh1, <i47 8, i47 8>
diff --git a/llvm/test/Transforms/InstCombine/apint-sub.ll b/llvm/test/Transforms/InstCombine/apint-sub.ll
index c3a2843077c9d..1c0374d443740 100644
--- a/llvm/test/Transforms/InstCombine/apint-sub.ll
+++ b/llvm/test/Transforms/InstCombine/apint-sub.ll
@@ -38,8 +38,8 @@ define i108 @test4(i108 %A, i108 %x) {
define i19 @test5(i19 %A, i19 %Bok, i19 %Cok) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[D1:%.*]] = sub i19 [[COK:%.*]], [[BOK:%.*]]
-; CHECK-NEXT: [[E:%.*]] = add i19 [[D1]], [[A:%.*]]
+; CHECK-NEXT: [[D_NEG:%.*]] = sub i19 [[COK:%.*]], [[BOK:%.*]]
+; CHECK-NEXT: [[E:%.*]] = add i19 [[D_NEG]], [[A:%.*]]
; CHECK-NEXT: ret i19 [[E]]
;
%D = sub i19 %Bok, %Cok
@@ -99,8 +99,8 @@ define i1 @test11(i9 %A, i9 %B) {
define i43 @test12(i43 %A) {
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[C:%.*]] = lshr i43 [[A:%.*]], 42
-; CHECK-NEXT: ret i43 [[C]]
+; CHECK-NEXT: [[B_NEG:%.*]] = lshr i43 [[A:%.*]], 42
+; CHECK-NEXT: ret i43 [[B_NEG]]
;
%B = ashr i43 %A, 42
%C = sub i43 0, %B
@@ -109,8 +109,8 @@ define i43 @test12(i43 %A) {
define i79 @test13(i79 %A) {
; CHECK-LABEL: @test13(
-; CHECK-NEXT: [[C:%.*]] = ashr i79 [[A:%.*]], 78
-; CHECK-NEXT: ret i79 [[C]]
+; CHECK-NEXT: [[B_NEG:%.*]] = ashr i79 [[A:%.*]], 78
+; CHECK-NEXT: ret i79 [[B_NEG]]
;
%B = lshr i79 %A, 78
%C = sub i79 0, %B
@@ -119,8 +119,8 @@ define i79 @test13(i79 %A) {
define i1024 @test14(i1024 %A) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[D:%.*]] = ashr i1024 [[A:%.*]], 1023
-; CHECK-NEXT: ret i1024 [[D]]
+; CHECK-NEXT: [[B_NEG:%.*]] = ashr i1024 [[A:%.*]], 1023
+; CHECK-NEXT: ret i1024 [[B_NEG]]
;
%B = lshr i1024 %A, 1023
%C = bitcast i1024 %B to i1024
@@ -130,8 +130,8 @@ define i1024 @test14(i1024 %A) {
define i51 @test16(i51 %A) {
; CHECK-LABEL: @test16(
-; CHECK-NEXT: [[Y:%.*]] = sdiv i51 [[A:%.*]], -1123
-; CHECK-NEXT: ret i51 [[Y]]
+; CHECK-NEXT: [[X_NEG:%.*]] = sdiv i51 [[A:%.*]], -1123
+; CHECK-NEXT: ret i51 [[X_NEG]]
;
%X = sdiv i51 %A, 1123
%Y = sub i51 0, %X
diff --git a/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll b/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
index 07e224bdab92e..04b530647d0a2 100644
--- a/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
+++ b/llvm/test/Transforms/InstCombine/assoc-cast-assoc.ll
@@ -3,7 +3,7 @@
define i5 @XorZextXor(i3 %a) {
; CHECK-LABEL: @XorZextXor(
-; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5
+; CHECK-NEXT: [[CAST:%.*]] = zext i3 [[A:%.*]] to i5
; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 15
; CHECK-NEXT: ret i5 [[OP2]]
;
@@ -15,7 +15,7 @@ define i5 @XorZextXor(i3 %a) {
define <2 x i32> @XorZextXorVec(<2 x i1> %a) {
; CHECK-LABEL: @XorZextXorVec(
-; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> %a to <2 x i32>
+; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i32>
; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>
; CHECK-NEXT: ret <2 x i32> [[OP2]]
;
@@ -27,7 +27,7 @@ define <2 x i32> @XorZextXorVec(<2 x i1> %a) {
define i5 @OrZextOr(i3 %a) {
; CHECK-LABEL: @OrZextOr(
-; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5
+; CHECK-NEXT: [[CAST:%.*]] = zext i3 [[A:%.*]] to i5
; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 11
; CHECK-NEXT: ret i5 [[OP2]]
;
@@ -39,7 +39,7 @@ define i5 @OrZextOr(i3 %a) {
define <2 x i32> @OrZextOrVec(<2 x i2> %a) {
; CHECK-LABEL: @OrZextOrVec(
-; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> %a to <2 x i32>
+; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> [[A:%.*]] to <2 x i32>
; CHECK-NEXT: [[OP2:%.*]] = or <2 x i32> [[CAST]], <i32 3, i32 5>
; CHECK-NEXT: ret <2 x i32> [[OP2]]
;
@@ -53,7 +53,7 @@ define <2 x i32> @OrZextOrVec(<2 x i2> %a) {
define i5 @AndZextAnd(i3 %a) {
; CHECK-LABEL: @AndZextAnd(
-; CHECK-NEXT: [[TMP1:%.*]] = and i3 %a, 2
+; CHECK-NEXT: [[TMP1:%.*]] = and i3 [[A:%.*]], 2
; CHECK-NEXT: [[OP2:%.*]] = zext i3 [[TMP1]] to i5
; CHECK-NEXT: ret i5 [[OP2]]
;
@@ -65,7 +65,7 @@ define i5 @AndZextAnd(i3 %a) {
define <2 x i32> @AndZextAndVec(<2 x i8> %a) {
; CHECK-LABEL: @AndZextAndVec(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> %a, <i8 5, i8 0>
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[A:%.*]], <i8 5, i8 0>
; CHECK-NEXT: [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[OP2]]
;
diff --git a/llvm/test/Transforms/InstCombine/bcmp-1.ll b/llvm/test/Transforms/InstCombine/bcmp-1.ll
index 87e06c5c4988f..73daae44d020d 100644
--- a/llvm/test/Transforms/InstCombine/bcmp-1.ll
+++ b/llvm/test/Transforms/InstCombine/bcmp-1.ll
@@ -76,8 +76,8 @@ define i32 @test_simplify6() {
define i1 @test_simplify7(i64 %x, i64 %y) {
; CHECK-LABEL: @test_simplify7(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[DOTNOT]]
;
%x.addr = alloca i64, align 8
%y.addr = alloca i64, align 8
@@ -92,8 +92,8 @@ define i1 @test_simplify7(i64 %x, i64 %y) {
define i1 @test_simplify8(i32 %x, i32 %y) {
; CHECK-LABEL: @test_simplify8(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[DOTNOT]]
;
%x.addr = alloca i32, align 4
%y.addr = alloca i32, align 4
@@ -108,8 +108,8 @@ define i1 @test_simplify8(i32 %x, i32 %y) {
define i1 @test_simplify9(i16 %x, i16 %y) {
; CHECK-LABEL: @test_simplify9(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[DOTNOT]]
;
%x.addr = alloca i16, align 2
%y.addr = alloca i16, align 2
diff --git a/llvm/test/Transforms/InstCombine/bcopy.ll b/llvm/test/Transforms/InstCombine/bcopy.ll
index 57bfc4abaa7c3..16ed3185455c9 100644
--- a/llvm/test/Transforms/InstCombine/bcopy.ll
+++ b/llvm/test/Transforms/InstCombine/bcopy.ll
@@ -5,8 +5,8 @@ declare void @bcopy(ptr nocapture readonly, ptr nocapture, i32)
define void @bcopy_memmove(ptr nocapture readonly %a, ptr nocapture %b) {
; CHECK-LABEL: @bcopy_memmove(
-; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[A:%.*]], align 1
-; CHECK-NEXT: store i64 [[TMP3]], ptr [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A:%.*]], align 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B:%.*]], align 1
; CHECK-NEXT: ret void
;
tail call void @bcopy(ptr %a, ptr %b, i32 8)
@@ -15,7 +15,7 @@ define void @bcopy_memmove(ptr nocapture readonly %a, ptr nocapture %b) {
define void @bcopy_memmove2(ptr nocapture readonly %a, ptr nocapture %b, i32 %len) {
; CHECK-LABEL: @bcopy_memmove2(
-; CHECK-NEXT: call void @llvm.memmove.p0.p0.i32(ptr align 1 [[B:%.*]], ptr align 1 [[A:%.*]], i32 [[LEN:%.*]], i1 false)
+; CHECK-NEXT: tail call void @llvm.memmove.p0.p0.i32(ptr align 1 [[B:%.*]], ptr align 1 [[A:%.*]], i32 [[LEN:%.*]], i1 false)
; CHECK-NEXT: ret void
;
tail call void @bcopy(ptr %a, ptr %b, i32 %len)
diff --git a/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll b/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
index c56a402fa6034..58df37b8d8d53 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
@@ -52,8 +52,8 @@ define float @test3(<2 x float> %A, <2 x i64> %B) {
define <2 x i32> @test4(i32 %A, i32 %B){
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[B:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A:%.*]], i64 1
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A:%.*]], i64 1
+; CHECK-NEXT: ret <2 x i32> [[TMP43]]
;
%tmp38 = zext i32 %A to i64
%tmp32 = zext i32 %B to i64
@@ -66,8 +66,8 @@ define <2 x i32> @test4(i32 %A, i32 %B){
define <2 x float> @test5(float %A, float %B) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[B:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[A:%.*]], i64 1
-; CHECK-NEXT: ret <2 x float> [[TMP2]]
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x float> [[TMP1]], float [[A:%.*]], i64 1
+; CHECK-NEXT: ret <2 x float> [[TMP43]]
;
%tmp37 = bitcast float %A to i32
%tmp38 = zext i32 %tmp37 to i64
@@ -81,8 +81,8 @@ define <2 x float> @test5(float %A, float %B) {
define <2 x float> @test6(float %A){
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 4.200000e+01>, float [[A:%.*]], i64 0
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[TMP35:%.*]] = insertelement <2 x float> <float poison, float 4.200000e+01>, float [[A:%.*]], i64 0
+; CHECK-NEXT: ret <2 x float> [[TMP35]]
;
%tmp23 = bitcast float %A to i32
%tmp24 = zext i32 %tmp23 to i64
diff --git a/llvm/test/Transforms/InstCombine/bitcast-function.ll b/llvm/test/Transforms/InstCombine/bitcast-function.ll
index 61039be35471b..e92d4e5de664a 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-function.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-function.ll
@@ -150,8 +150,8 @@ define void @bitcast_vector_ptrs_same_size(ptr noalias %source, ptr noalias %des
; CHECK-LABEL: define void @bitcast_vector_ptrs_same_size
; CHECK-SAME: (ptr noalias [[SOURCE:%.*]], ptr noalias [[DEST:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x ptr>, ptr [[SOURCE]], align 8
-; CHECK-NEXT: [[CALL:%.*]] = call <2 x ptr> @func_v2i32p(<2 x ptr> [[TMP1]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP:%.*]] = load <2 x ptr>, ptr [[SOURCE]], align 8
+; CHECK-NEXT: [[CALL:%.*]] = call <2 x ptr> @func_v2i32p(<2 x ptr> [[TMP]]) #[[ATTR1]]
; CHECK-NEXT: store <2 x ptr> [[CALL]], ptr [[DEST]], align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
index 2fa2bd9a795da..94e08d537575e 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
@@ -31,8 +31,8 @@ define <1 x i64> @c(double %y) {
define <1 x i64> @d(i64 %y) {
; CHECK-LABEL: @d(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[Y:%.*]], i64 0
-; CHECK-NEXT: ret <1 x i64> [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = insertelement <1 x i64> poison, i64 [[Y:%.*]], i64 0
+; CHECK-NEXT: ret <1 x i64> [[C]]
;
%c = bitcast i64 %y to <1 x i64>
ret <1 x i64> %c
diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
index 906c88ee817f8..fb5c91c7460a1 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
@@ -31,8 +31,8 @@ define <1 x i64> @c(double %y) {
define <1 x i64> @d(i64 %y) {
; CHECK-LABEL: @d(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[Y:%.*]], i64 0
-; CHECK-NEXT: ret <1 x i64> [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = insertelement <1 x i64> poison, i64 [[Y:%.*]], i64 0
+; CHECK-NEXT: ret <1 x i64> [[C]]
;
%c = bitcast i64 %y to <1 x i64>
ret <1 x i64> %c
diff --git a/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll b/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll
index ae3eadda0d6fe..86a57a1b702fa 100644
--- a/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll
+++ b/llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll
@@ -47,7 +47,7 @@ define i1 @test3(i32 %arg) {
define i8 @add_bitreverse(i8 %a) {
; CHECK-LABEL: @add_bitreverse(
; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -4
-; CHECK-NEXT: [[REVERSE:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[B]]), [[RNG0:!range !.*]]
+; CHECK-NEXT: [[REVERSE:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[B]]), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[C:%.*]] = or i8 [[REVERSE]], -16
; CHECK-NEXT: ret i8 [[C]]
;
diff --git a/llvm/test/Transforms/InstCombine/bswap-fold.ll b/llvm/test/Transforms/InstCombine/bswap-fold.ll
index 394cbb0478bdb..8183a0d709f33 100644
--- a/llvm/test/Transforms/InstCombine/bswap-fold.ll
+++ b/llvm/test/Transforms/InstCombine/bswap-fold.ll
@@ -48,8 +48,8 @@ define <2 x i32> @lshr16_v2i32(<2 x i32> %x) {
define i32 @lshr24_i32(i32 %x) {
; CHECK-LABEL: @lshr24_i32(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -16777216
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = and i32 [[X:%.*]], -16777216
+; CHECK-NEXT: ret i32 [[R]]
;
%s = lshr i32 %x, 24
%r = call i32 @llvm.bswap.i32(i32 %s)
@@ -110,8 +110,8 @@ define <2 x i64> @shl16_v2i64(<2 x i64> %x) {
define i64 @shl56_i64(i64 %x) {
; CHECK-LABEL: @shl56_i64(
-; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], 255
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = and i64 [[X:%.*]], 255
+; CHECK-NEXT: ret i64 [[R]]
;
%s = shl i64 %x, 56
%r = call i64 @llvm.bswap.i64(i64 %s)
@@ -282,8 +282,8 @@ define i16 @bs_and16i(i16 %a, i16 %b) #0 {
define i16 @bs_and16(i16 %a, i16 %b) #0 {
; CHECK-LABEL: @bs_and16(
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]])
-; CHECK-NEXT: ret i16 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]])
+; CHECK-NEXT: ret i16 [[T3]]
;
%t1 = tail call i16 @llvm.bswap.i16(i16 %a)
%t2 = tail call i16 @llvm.bswap.i16(i16 %b)
@@ -294,8 +294,8 @@ define i16 @bs_and16(i16 %a, i16 %b) #0 {
define i16 @bs_or16(i16 %a, i16 %b) #0 {
; CHECK-LABEL: @bs_or16(
; CHECK-NEXT: [[TMP1:%.*]] = or i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]])
-; CHECK-NEXT: ret i16 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]])
+; CHECK-NEXT: ret i16 [[T3]]
;
%t1 = tail call i16 @llvm.bswap.i16(i16 %a)
%t2 = tail call i16 @llvm.bswap.i16(i16 %b)
@@ -306,8 +306,8 @@ define i16 @bs_or16(i16 %a, i16 %b) #0 {
define i16 @bs_xor16(i16 %a, i16 %b) #0 {
; CHECK-LABEL: @bs_xor16(
; CHECK-NEXT: [[TMP1:%.*]] = xor i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]])
-; CHECK-NEXT: ret i16 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP1]])
+; CHECK-NEXT: ret i16 [[T3]]
;
%t1 = tail call i16 @llvm.bswap.i16(i16 %a)
%t2 = tail call i16 @llvm.bswap.i16(i16 %b)
@@ -318,8 +318,8 @@ define i16 @bs_xor16(i16 %a, i16 %b) #0 {
define i32 @bs_and32i(i32 %a, i32 %b) #0 {
; CHECK-LABEL: @bs_and32i(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -1585053440
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[T2:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[T2]]
;
%t1 = tail call i32 @llvm.bswap.i32(i32 %a)
%t2 = and i32 %t1, 100001
@@ -329,8 +329,8 @@ define i32 @bs_and32i(i32 %a, i32 %b) #0 {
define i32 @bs_and32(i32 %a, i32 %b) #0 {
; CHECK-LABEL: @bs_and32(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = tail call i32 @llvm.bswap.i32(i32 %a)
%t2 = tail call i32 @llvm.bswap.i32(i32 %b)
@@ -341,8 +341,8 @@ define i32 @bs_and32(i32 %a, i32 %b) #0 {
define i32 @bs_or32(i32 %a, i32 %b) #0 {
; CHECK-LABEL: @bs_or32(
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = tail call i32 @llvm.bswap.i32(i32 %a)
%t2 = tail call i32 @llvm.bswap.i32(i32 %b)
@@ -353,8 +353,8 @@ define i32 @bs_or32(i32 %a, i32 %b) #0 {
define i32 @bs_xor32(i32 %a, i32 %b) #0 {
; CHECK-LABEL: @bs_xor32(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = tail call i32 @llvm.bswap.i32(i32 %a)
%t2 = tail call i32 @llvm.bswap.i32(i32 %b)
@@ -365,8 +365,8 @@ define i32 @bs_xor32(i32 %a, i32 %b) #0 {
define i64 @bs_and64i(i64 %a, i64 %b) #0 {
; CHECK-LABEL: @bs_and64i(
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], 129085117527228416
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[T2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
+; CHECK-NEXT: ret i64 [[T2]]
;
%t1 = tail call i64 @llvm.bswap.i64(i64 %a)
%t2 = and i64 %t1, 1000000001
@@ -376,8 +376,8 @@ define i64 @bs_and64i(i64 %a, i64 %b) #0 {
define i64 @bs_and64(i64 %a, i64 %b) #0 {
; CHECK-LABEL: @bs_and64(
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
+; CHECK-NEXT: ret i64 [[T3]]
;
%t1 = tail call i64 @llvm.bswap.i64(i64 %a)
%t2 = tail call i64 @llvm.bswap.i64(i64 %b)
@@ -388,8 +388,8 @@ define i64 @bs_and64(i64 %a, i64 %b) #0 {
define i64 @bs_or64(i64 %a, i64 %b) #0 {
; CHECK-LABEL: @bs_or64(
; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
+; CHECK-NEXT: ret i64 [[T3]]
;
%t1 = tail call i64 @llvm.bswap.i64(i64 %a)
%t2 = tail call i64 @llvm.bswap.i64(i64 %b)
@@ -400,8 +400,8 @@ define i64 @bs_or64(i64 %a, i64 %b) #0 {
define i64 @bs_xor64(i64 %a, i64 %b) #0 {
; CHECK-LABEL: @bs_xor64(
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
+; CHECK-NEXT: ret i64 [[T3]]
;
%t1 = tail call i64 @llvm.bswap.i64(i64 %a)
%t2 = tail call i64 @llvm.bswap.i64(i64 %b)
@@ -412,8 +412,8 @@ define i64 @bs_xor64(i64 %a, i64 %b) #0 {
define <2 x i32> @bs_and32vec(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: @bs_and32vec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
+; CHECK-NEXT: ret <2 x i32> [[T3]]
;
%t1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
%t2 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %b)
@@ -424,8 +424,8 @@ define <2 x i32> @bs_and32vec(<2 x i32> %a, <2 x i32> %b) #0 {
define <2 x i32> @bs_or32vec(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: @bs_or32vec(
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
+; CHECK-NEXT: ret <2 x i32> [[T3]]
;
%t1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
%t2 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %b)
@@ -436,8 +436,8 @@ define <2 x i32> @bs_or32vec(<2 x i32> %a, <2 x i32> %b) #0 {
define <2 x i32> @bs_xor32vec(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: @bs_xor32vec(
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
+; CHECK-NEXT: ret <2 x i32> [[T3]]
;
%t1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
%t2 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %b)
@@ -448,8 +448,8 @@ define <2 x i32> @bs_xor32vec(<2 x i32> %a, <2 x i32> %b) #0 {
define <2 x i32> @bs_and32ivec(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: @bs_and32ivec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 -1585053440, i32 -1585053440>
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
+; CHECK-NEXT: ret <2 x i32> [[T2]]
;
%t1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
%t2 = and <2 x i32> %t1, <i32 100001, i32 100001>
@@ -459,8 +459,8 @@ define <2 x i32> @bs_and32ivec(<2 x i32> %a, <2 x i32> %b) #0 {
define <2 x i32> @bs_or32ivec(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: @bs_or32ivec(
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[A:%.*]], <i32 -1585053440, i32 -1585053440>
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
+; CHECK-NEXT: ret <2 x i32> [[T2]]
;
%t1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
%t2 = or <2 x i32> %t1, <i32 100001, i32 100001>
@@ -470,8 +470,8 @@ define <2 x i32> @bs_or32ivec(<2 x i32> %a, <2 x i32> %b) #0 {
define <2 x i32> @bs_xor32ivec(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-LABEL: @bs_xor32ivec(
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[A:%.*]], <i32 -1585053440, i32 -1585053440>
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[T2:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP1]])
+; CHECK-NEXT: ret <2 x i32> [[T2]]
;
%t1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a)
%t2 = xor <2 x i32> %t1, <i32 100001, i32 100001>
@@ -499,8 +499,8 @@ define i64 @bs_and64_multiuse2(i64 %a, i64 %b) #0 {
; CHECK-LABEL: @bs_and64_multiuse2(
; CHECK-NEXT: [[T1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[A:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
-; CHECK-NEXT: [[T4:%.*]] = mul i64 [[TMP2]], [[T1]]
+; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
+; CHECK-NEXT: [[T4:%.*]] = mul i64 [[T3]], [[T1]]
; CHECK-NEXT: ret i64 [[T4]]
;
%t1 = tail call i64 @llvm.bswap.i64(i64 %a)
@@ -514,8 +514,8 @@ define i64 @bs_and64_multiuse3(i64 %a, i64 %b) #0 {
; CHECK-LABEL: @bs_and64_multiuse3(
; CHECK-NEXT: [[T2:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], [[B]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
-; CHECK-NEXT: [[T4:%.*]] = mul i64 [[TMP2]], [[T2]]
+; CHECK-NEXT: [[T3:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]])
+; CHECK-NEXT: [[T4:%.*]] = mul i64 [[T3]], [[T2]]
; CHECK-NEXT: ret i64 [[T4]]
;
%t1 = tail call i64 @llvm.bswap.i64(i64 %a)
diff --git a/llvm/test/Transforms/InstCombine/call-callconv.ll b/llvm/test/Transforms/InstCombine/call-callconv.ll
index 5b8e3e4781ebe..c75360db159b8 100644
--- a/llvm/test/Transforms/InstCombine/call-callconv.ll
+++ b/llvm/test/Transforms/InstCombine/call-callconv.ll
@@ -11,8 +11,8 @@ target datalayout = "p:32:32"
define arm_aapcscc i32 @_abs(i32 %i) nounwind readnone {
; CHECK-LABEL: @_abs(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[I:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.abs.i32(i32 [[I:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[CALL]]
;
%call = tail call arm_aapcscc i32 @abs(i32 %i) nounwind readnone
ret i32 %call
@@ -22,8 +22,8 @@ declare arm_aapcscc i32 @abs(i32) nounwind readnone
define arm_aapcscc i32 @_labs(i32 %i) nounwind readnone {
; CHECK-LABEL: @_labs(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[I:%.*]], i1 true)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.abs.i32(i32 [[I:%.*]], i1 true)
+; CHECK-NEXT: ret i32 [[CALL]]
;
%call = tail call arm_aapcscc i32 @labs(i32 %i) nounwind readnone
ret i32 %call
@@ -43,8 +43,8 @@ declare arm_aapcscc i32 @strlen(ptr)
define arm_aapcscc zeroext i1 @_strlen2(ptr %str) {
; CHECK-LABEL: @_strlen2(
-; CHECK-NEXT: [[STRLENFIRST:%.*]] = load i8, ptr [[STR:%.*]], align 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[STRLENFIRST]], 0
+; CHECK-NEXT: [[CHAR0:%.*]] = load i8, ptr [[STR:%.*]], align 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[CHAR0]], 0
; CHECK-NEXT: ret i1 [[CMP]]
;
%call = tail call arm_aapcscc i32 @strlen(ptr %str)
diff --git a/llvm/test/Transforms/InstCombine/call-returned.ll b/llvm/test/Transforms/InstCombine/call-returned.ll
index 4cbcaad0cf012..be42568ef8753 100644
--- a/llvm/test/Transforms/InstCombine/call-returned.ll
+++ b/llvm/test/Transforms/InstCombine/call-returned.ll
@@ -55,9 +55,9 @@ define <8 x i8> @returned_const_vec_arg_casted() {
define <8 x i8> @returned_vec_arg_casted(<2 x i32> %a) {
; CHECK-LABEL: @returned_vec_arg_casted(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[A:%.*]] to <8 x i8>
-; CHECK-NEXT: [[X:%.*]] = call <8 x i8> @passthru_8i8v_from_2i32v(<2 x i32> [[A]])
-; CHECK-NEXT: ret <8 x i8> [[TMP1]]
+; CHECK-NEXT: [[X:%.*]] = bitcast <2 x i32> [[A:%.*]] to <8 x i8>
+; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i8> @passthru_8i8v_from_2i32v(<2 x i32> [[A]])
+; CHECK-NEXT: ret <8 x i8> [[X]]
;
%x = call <8 x i8> @passthru_8i8v_from_2i32v(<2 x i32> %a)
ret <8 x i8> %x
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll b/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll
index 6feb527c66727..bace0b2d76e49 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll
@@ -26,8 +26,8 @@ define i8 @positive_samevar(i8 %x, i8 %y) {
define i8 @positive_sameconst(i8 %x) {
; CHECK-LABEL: @positive_sameconst(
-; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -8
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = and i8 [[X:%.*]], -8
+; CHECK-NEXT: ret i8 [[RET]]
;
%tmp0 = ashr i8 %x, 3
%ret = shl i8 %tmp0, 3
@@ -386,8 +386,8 @@ define <2 x i8> @positive_samevar_vec(<2 x i8> %x, <2 x i8> %y) {
define <2 x i8> @positive_sameconst_vec(<2 x i8> %x) {
; CHECK-LABEL: @positive_sameconst_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], <i8 -8, i8 -8>
-; CHECK-NEXT: ret <2 x i8> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = and <2 x i8> [[X:%.*]], <i8 -8, i8 -8>
+; CHECK-NEXT: ret <2 x i8> [[RET]]
;
%tmp0 = ashr <2 x i8> %x, <i8 3, i8 3>
%ret = shl <2 x i8> %tmp0, <i8 3, i8 3>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-clamp-with-select-of-constant-threshold-pattern.ll b/llvm/test/Transforms/InstCombine/canonicalize-clamp-with-select-of-constant-threshold-pattern.ll
index 1ad8dcfb20091..13f458ca7c937 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-clamp-with-select-of-constant-threshold-pattern.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-clamp-with-select-of-constant-threshold-pattern.ll
@@ -8,8 +8,8 @@
define i32 @t0_select_cond_and_v0(i32 %X) {
; CHECK-LABEL: @t0_select_cond_and_v0(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%dont_need_to_clamp_positive = icmp sle i32 %X, 32767
%dont_need_to_clamp_negative = icmp sge i32 %X, -32768
@@ -22,8 +22,8 @@ define i32 @t0_select_cond_and_v0(i32 %X) {
define i32 @t0_select_cond_and_v0_logical(i32 %X) {
; CHECK-LABEL: @t0_select_cond_and_v0_logical(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%dont_need_to_clamp_positive = icmp sle i32 %X, 32767
%dont_need_to_clamp_negative = icmp sge i32 %X, -32768
@@ -35,8 +35,8 @@ define i32 @t0_select_cond_and_v0_logical(i32 %X) {
define i32 @t1_select_cond_and_v1(i32 %X) {
; CHECK-LABEL: @t1_select_cond_and_v1(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%dont_need_to_clamp_positive = icmp sle i32 %X, 32767
%dont_need_to_clamp_negative = icmp sge i32 %X, -32768
@@ -49,8 +49,8 @@ define i32 @t1_select_cond_and_v1(i32 %X) {
define i32 @t1_select_cond_and_v1_logical(i32 %X) {
; CHECK-LABEL: @t1_select_cond_and_v1_logical(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%dont_need_to_clamp_positive = icmp sle i32 %X, 32767
%dont_need_to_clamp_negative = icmp sge i32 %X, -32768
@@ -65,8 +65,8 @@ define i32 @t1_select_cond_and_v1_logical(i32 %X) {
define i32 @t2_select_cond_or_v0(i32 %X) {
; CHECK-LABEL: @t2_select_cond_or_v0(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%need_to_clamp_positive = icmp sgt i32 %X, 32767
%need_to_clamp_negative = icmp slt i32 %X, -32768
@@ -79,8 +79,8 @@ define i32 @t2_select_cond_or_v0(i32 %X) {
define i32 @t2_select_cond_or_v0_logical(i32 %X) {
; CHECK-LABEL: @t2_select_cond_or_v0_logical(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%need_to_clamp_positive = icmp sgt i32 %X, 32767
%need_to_clamp_negative = icmp slt i32 %X, -32768
@@ -92,8 +92,8 @@ define i32 @t2_select_cond_or_v0_logical(i32 %X) {
define i32 @t3_select_cond_or_v1(i32 %X) {
; CHECK-LABEL: @t3_select_cond_or_v1(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%need_to_clamp_positive = icmp sgt i32 %X, 32767
%need_to_clamp_negative = icmp slt i32 %X, -32768
@@ -106,8 +106,8 @@ define i32 @t3_select_cond_or_v1(i32 %X) {
define i32 @t3_select_cond_or_v1_logical(i32 %X) {
; CHECK-LABEL: @t3_select_cond_or_v1_logical(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%need_to_clamp_positive = icmp sgt i32 %X, 32767
%need_to_clamp_negative = icmp slt i32 %X, -32768
@@ -122,8 +122,8 @@ define i32 @t3_select_cond_or_v1_logical(i32 %X) {
define i32 @t4_select_cond_xor_v0(i32 %X) {
; CHECK-LABEL: @t4_select_cond_xor_v0(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%need_to_clamp_positive = icmp sgt i32 %X, 32767
%dont_need_to_clamp_negative = icmp sgt i32 %X, -32768
@@ -135,8 +135,8 @@ define i32 @t4_select_cond_xor_v0(i32 %X) {
define i32 @t4_select_cond_xor_v1(i32 %X) {
; CHECK-LABEL: @t4_select_cond_xor_v1(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%need_to_clamp_positive = icmp sgt i32 %X, 32767
%dont_need_to_clamp_negative = icmp sgt i32 %X, -32768
@@ -149,8 +149,8 @@ define i32 @t4_select_cond_xor_v1(i32 %X) {
define i32 @t5_select_cond_xor_v2(i32 %X) {
; CHECK-LABEL: @t5_select_cond_xor_v2(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%dont_need_to_clamp_positive = icmp sle i32 %X, 32767
%need_to_clamp_negative = icmp sle i32 %X, -32768
@@ -162,8 +162,8 @@ define i32 @t5_select_cond_xor_v2(i32 %X) {
define i32 @t5_select_cond_xor_v3(i32 %X) {
; CHECK-LABEL: @t5_select_cond_xor_v3(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -32768)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 32767)
+; CHECK-NEXT: ret i32 [[R]]
;
%dont_need_to_clamp_positive = icmp sle i32 %X, 32767
%need_to_clamp_negative = icmp sle i32 %X, -32768
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
index dd17f0b5db597..85bb4d51c7ba4 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
@@ -16,8 +16,8 @@
define i1 @p0(i8 %x) {
; CHECK-LABEL: @p0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X:%.*]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
%ret = icmp eq i8 %tmp0, %x
@@ -27,8 +27,8 @@ define i1 @p0(i8 %x) {
define i1 @pv(i8 %x, i8 %y) {
; CHECK-LABEL: @pv(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -42,8 +42,8 @@ define i1 @pv(i8 %x, i8 %y) {
define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 4>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 4>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
%ret = icmp eq <2 x i8> %tmp0, %x
@@ -52,8 +52,8 @@ define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 16>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 16>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
%ret = icmp eq <2 x i8> %tmp0, %x
@@ -72,8 +72,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
}
define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <2 x i8> [[X:%.*]], <i8 3, i8 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule <2 x i8> [[X:%.*]], <i8 3, i8 -1>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 -1>
%ret = icmp eq <2 x i8> %tmp0, %x
@@ -82,8 +82,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_splat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <3 x i8> [[X:%.*]], <i8 4, i8 4, i8 4>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <3 x i8> [[X:%.*]], <i8 4, i8 4, i8 4>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
%ret = icmp eq <3 x i8> %tmp0, %x
@@ -99,8 +99,8 @@ declare i8 @gen8()
define i1 @c0() {
; CHECK-LABEL: @c0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
@@ -116,8 +116,8 @@ define i1 @cv0(i8 %y) {
; CHECK-LABEL: @cv0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -130,8 +130,8 @@ define i1 @cv1(i8 %y) {
; CHECK-LABEL: @cv1(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -144,8 +144,8 @@ define i1 @cv2(i8 %y) {
; CHECK-LABEL: @cv2(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -164,8 +164,8 @@ define i1 @oneuse0(i8 %x) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
index f61b2a0e4d8ac..473ae0caabe6b 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
@@ -16,8 +16,8 @@
define i1 @p0(i8 %x) {
; CHECK-LABEL: @p0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
%ret = icmp ne i8 %tmp0, %x
@@ -27,8 +27,8 @@ define i1 @p0(i8 %x) {
define i1 @pv(i8 %x, i8 %y) {
; CHECK-LABEL: @pv(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -42,8 +42,8 @@ define i1 @pv(i8 %x, i8 %y) {
define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 3>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 3>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
%ret = icmp ne <2 x i8> %tmp0, %x
@@ -52,8 +52,8 @@ define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 15>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 15>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
%ret = icmp ne <2 x i8> %tmp0, %x
@@ -72,8 +72,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
}
define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 -1>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 -1>
%ret = icmp ne <2 x i8> %tmp0, %x
@@ -82,8 +82,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_splat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
%ret = icmp ne <3 x i8> %tmp0, %x
@@ -92,8 +92,8 @@ define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
define <3 x i1> @p3_vec_nonsplat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_nonsplat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 -1, i8 undef, i8 3>
%ret = icmp ne <3 x i8> %tmp0, %x
@@ -109,8 +109,8 @@ declare i8 @gen8()
define i1 @c0() {
; CHECK-LABEL: @c0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
@@ -126,8 +126,8 @@ define i1 @cv0(i8 %y) {
; CHECK-LABEL: @cv0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -140,8 +140,8 @@ define i1 @cv1(i8 %y) {
; CHECK-LABEL: @cv1(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -154,8 +154,8 @@ define i1 @cv2(i8 %y) {
; CHECK-LABEL: @cv2(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -174,8 +174,8 @@ define i1 @oneuse0(i8 %x) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
index 3faa3e0fa1e1c..0dfc9f51baf9c 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
@@ -16,8 +16,8 @@
define i1 @p0(i8 %x) {
; CHECK-LABEL: @p0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[X:%.*]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
%ret = icmp sge i8 %tmp0, %x
@@ -30,8 +30,8 @@ define i1 @p0(i8 %x) {
define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X:%.*]], <i8 4, i8 4>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[X:%.*]], <i8 4, i8 4>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
%ret = icmp sge <2 x i8> %tmp0, %x
@@ -40,8 +40,8 @@ define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X:%.*]], <i8 4, i8 16>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[X:%.*]], <i8 4, i8 16>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
%ret = icmp sge <2 x i8> %tmp0, %x
@@ -61,8 +61,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase(<2 x i8> %x) {
define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_splat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <3 x i8> [[X:%.*]], <i8 4, i8 4, i8 4>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <3 x i8> [[X:%.*]], <i8 4, i8 4, i8 4>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
%ret = icmp sge <3 x i8> %tmp0, %x
@@ -79,8 +79,8 @@ define i1 @oneuse0(i8 %x) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
index 29fa1f2af8ef0..e0893ce4cf2ec 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
@@ -23,8 +23,8 @@ declare <3 x i8> @gen3x8()
define i1 @p0() {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
@@ -39,8 +39,8 @@ define i1 @p0() {
define <2 x i1> @p1_vec_splat() {
; CHECK-LABEL: @p1_vec_splat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i8> [[X]], <i8 3, i8 3>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X]], <i8 3, i8 3>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
@@ -51,8 +51,8 @@ define <2 x i1> @p1_vec_splat() {
define <2 x i1> @p2_vec_nonsplat() {
; CHECK-LABEL: @p2_vec_nonsplat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i8> [[X]], <i8 3, i8 15>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X]], <i8 3, i8 15>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
@@ -76,8 +76,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase() {
define <3 x i1> @p3_vec_splat_undef() {
; CHECK-LABEL: @p3_vec_splat_undef(
; CHECK-NEXT: [[X:%.*]] = call <3 x i8> @gen3x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i8> [[X]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <3 x i8> [[X]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%x = call <3 x i8> @gen3x8()
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -88,8 +88,8 @@ define <3 x i1> @p3_vec_splat_undef() {
define <3 x i1> @p3_vec_nonsplat_undef() {
; CHECK-LABEL: @p3_vec_nonsplat_undef(
; CHECK-NEXT: [[X:%.*]] = call <3 x i8> @gen3x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i8> [[X]], <i8 15, i8 3, i8 15>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <3 x i8> [[X]], <i8 15, i8 3, i8 15>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%x = call <3 x i8> @gen3x8()
%tmp0 = and <3 x i8> %x, <i8 15, i8 3, i8 undef>
@@ -108,8 +108,8 @@ define i1 @oneuse0() {
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
index e7c608f69f1a1..81887a3909157 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
@@ -23,8 +23,8 @@ declare <3 x i8> @gen3x8()
define i1 @p0() {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
@@ -39,8 +39,8 @@ define i1 @p0() {
define <2 x i1> @p1_vec_splat() {
; CHECK-LABEL: @p1_vec_splat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X]], <i8 4, i8 4>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[X]], <i8 4, i8 4>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
@@ -51,8 +51,8 @@ define <2 x i1> @p1_vec_splat() {
define <2 x i1> @p2_vec_nonsplat() {
; CHECK-LABEL: @p2_vec_nonsplat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X]], <i8 4, i8 16>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[X]], <i8 4, i8 16>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
@@ -76,8 +76,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase() {
define <3 x i1> @p3_vec_splat_undef() {
; CHECK-LABEL: @p3_vec_splat_undef(
; CHECK-NEXT: [[X:%.*]] = call <3 x i8> @gen3x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <3 x i8> [[X]], <i8 4, i8 4, i8 4>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <3 x i8> [[X]], <i8 4, i8 4, i8 4>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%x = call <3 x i8> @gen3x8()
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -96,8 +96,8 @@ define i1 @oneuse0() {
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
index 873149710f4b9..8ce8687f19844 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
@@ -16,8 +16,8 @@
define i1 @p0(i8 %x) {
; CHECK-LABEL: @p0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt i8 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
%ret = icmp slt i8 %tmp0, %x
@@ -30,8 +30,8 @@ define i1 @p0(i8 %x) {
define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 3, i8 3>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 3, i8 3>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
%ret = icmp slt <2 x i8> %tmp0, %x
@@ -40,8 +40,8 @@ define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 3, i8 15>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 3, i8 15>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
%ret = icmp slt <2 x i8> %tmp0, %x
@@ -61,8 +61,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase(<2 x i8> %x) {
define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_splat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
%ret = icmp slt <3 x i8> %tmp0, %x
@@ -71,8 +71,8 @@ define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
define <3 x i1> @p3_vec_nonsplat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_nonsplat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i8> [[X:%.*]], <i8 15, i8 15, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <3 x i8> [[X:%.*]], <i8 15, i8 15, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 undef, i8 15, i8 3>
%ret = icmp slt <3 x i8> %tmp0, %x
@@ -89,8 +89,8 @@ define i1 @oneuse0(i8 %x) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
index 321a6933b5fe3..c84b8f8024bf4 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
@@ -16,8 +16,8 @@
define i1 @p0(i8 %x) {
; CHECK-LABEL: @p0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X:%.*]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
%ret = icmp uge i8 %tmp0, %x
@@ -27,8 +27,8 @@ define i1 @p0(i8 %x) {
define i1 @pv(i8 %x, i8 %y) {
; CHECK-LABEL: @pv(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -42,8 +42,8 @@ define i1 @pv(i8 %x, i8 %y) {
define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 4>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 4>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
%ret = icmp uge <2 x i8> %tmp0, %x
@@ -52,8 +52,8 @@ define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 16>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 16>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
%ret = icmp uge <2 x i8> %tmp0, %x
@@ -72,8 +72,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
}
define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <2 x i8> [[X:%.*]], <i8 3, i8 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule <2 x i8> [[X:%.*]], <i8 3, i8 -1>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 -1>
%ret = icmp uge <2 x i8> %tmp0, %x
@@ -82,8 +82,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_splat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <3 x i8> [[X:%.*]], <i8 4, i8 4, i8 4>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <3 x i8> [[X:%.*]], <i8 4, i8 4, i8 4>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
%ret = icmp uge <3 x i8> %tmp0, %x
@@ -116,8 +116,8 @@ define i1 @cv0(i8 %y) {
; CHECK-LABEL: @cv0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -160,8 +160,8 @@ define i1 @oneuse0(i8 %x) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
index 4674e3a2c1097..69f5cf719740c 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
@@ -21,8 +21,8 @@ declare <3 x i8> @gen3x8()
define i1 @p0() {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
@@ -34,8 +34,8 @@ define i1 @pv(i8 %y) {
; CHECK-LABEL: @pv(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -51,8 +51,8 @@ define i1 @pv(i8 %y) {
define <2 x i1> @p1_vec_splat() {
; CHECK-LABEL: @p1_vec_splat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 3>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 3>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
@@ -63,8 +63,8 @@ define <2 x i1> @p1_vec_splat() {
define <2 x i1> @p2_vec_nonsplat() {
; CHECK-LABEL: @p2_vec_nonsplat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 15>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 15>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
@@ -87,8 +87,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase0() {
define <2 x i1> @p2_vec_nonsplat_edgecase1() {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase1(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 -1>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 -1>
@@ -99,8 +99,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase1() {
define <3 x i1> @p3_vec_splat_undef() {
; CHECK-LABEL: @p3_vec_splat_undef(
; CHECK-NEXT: [[X:%.*]] = call <3 x i8> @gen3x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <3 x i8> [[X]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <3 x i8> [[X]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%x = call <3 x i8> @gen3x8()
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -111,8 +111,8 @@ define <3 x i1> @p3_vec_splat_undef() {
define <3 x i1> @p3_vec_nonsplat_undef() {
; CHECK-LABEL: @p3_vec_nonsplat_undef(
; CHECK-NEXT: [[X:%.*]] = call <3 x i8> @gen3x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <3 x i8> [[X]], <i8 3, i8 3, i8 15>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <3 x i8> [[X]], <i8 3, i8 3, i8 15>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%x = call <3 x i8> @gen3x8()
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 15>
@@ -141,8 +141,8 @@ define i1 @cv0(i8 %y) {
; CHECK-LABEL: @cv0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -184,8 +184,8 @@ define i1 @oneuse0() {
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
index 753a5938b5990..bd8ed8ef4c36a 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
@@ -21,8 +21,8 @@ declare <3 x i8> @gen3x8()
define i1 @p0() {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
@@ -34,8 +34,8 @@ define i1 @pv(i8 %y) {
; CHECK-LABEL: @pv(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -51,8 +51,8 @@ define i1 @pv(i8 %y) {
define <2 x i1> @p1_vec_splat() {
; CHECK-LABEL: @p1_vec_splat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[X]], <i8 4, i8 4>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X]], <i8 4, i8 4>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
@@ -63,8 +63,8 @@ define <2 x i1> @p1_vec_splat() {
define <2 x i1> @p2_vec_nonsplat() {
; CHECK-LABEL: @p2_vec_nonsplat(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[X]], <i8 4, i8 16>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X]], <i8 4, i8 16>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
@@ -87,8 +87,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase0() {
define <2 x i1> @p2_vec_nonsplat_edgecase1() {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase1(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <2 x i8> [[X]], <i8 3, i8 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule <2 x i8> [[X]], <i8 3, i8 -1>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
%tmp0 = and <2 x i8> %x, <i8 3, i8 -1>
@@ -99,8 +99,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase1() {
define <3 x i1> @p3_vec_splat_undef() {
; CHECK-LABEL: @p3_vec_splat_undef(
; CHECK-NEXT: [[X:%.*]] = call <3 x i8> @gen3x8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <3 x i8> [[X]], <i8 4, i8 4, i8 4>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <3 x i8> [[X]], <i8 4, i8 4, i8 4>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%x = call <3 x i8> @gen3x8()
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -129,8 +129,8 @@ define i1 @cv0(i8 %y) {
; CHECK-LABEL: @cv0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -172,8 +172,8 @@ define i1 @oneuse0() {
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X]], 4
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X]], 4
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = and i8 %x, 3
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
index 48b3ef52ee51c..a7e58cbb617ea 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
@@ -16,8 +16,8 @@
define i1 @p0(i8 %x) {
; CHECK-LABEL: @p0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
%ret = icmp ult i8 %tmp0, %x
@@ -27,8 +27,8 @@ define i1 @p0(i8 %x) {
define i1 @pv(i8 %x, i8 %y) {
; CHECK-LABEL: @pv(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -42,8 +42,8 @@ define i1 @pv(i8 %x, i8 %y) {
define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
; CHECK-LABEL: @p1_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 3>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 3>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 3>
%ret = icmp ult <2 x i8> %tmp0, %x
@@ -52,8 +52,8 @@ define <2 x i1> @p1_vec_splat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 15>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 15>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
%ret = icmp ult <2 x i8> %tmp0, %x
@@ -73,8 +73,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 -1>
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 -1>
%ret = icmp ult <2 x i8> %tmp0, %x
@@ -83,8 +83,8 @@ define <2 x i1> @p2_vec_nonsplat_edgecase1(<2 x i8> %x) {
define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_splat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 3, i8 undef, i8 3>
%ret = icmp ult <3 x i8> %tmp0, %x
@@ -93,8 +93,8 @@ define <3 x i1> @p3_vec_splat_undef(<3 x i8> %x) {
define <3 x i1> @p3_vec_nonsplat_undef(<3 x i8> %x) {
; CHECK-LABEL: @p3_vec_nonsplat_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 7, i8 31, i8 7>
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <3 x i8> [[X:%.*]], <i8 7, i8 31, i8 7>
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = and <3 x i8> %x, <i8 7, i8 31, i8 undef>
%ret = icmp ult <3 x i8> %tmp0, %x
@@ -127,8 +127,8 @@ define i1 @cv0(i8 %y) {
; CHECK-LABEL: @cv0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%x = call i8 @gen8()
%tmp0 = lshr i8 -1, %y
@@ -171,8 +171,8 @@ define i1 @oneuse0(i8 %x) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], 3
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], 3
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = and i8 %x, 3
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll b/llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll
index 303365b098685..b706ff15f569c 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll
@@ -198,8 +198,8 @@ define i1 @n0(i8 %x) {
define i1 @n1(i8 %x) {
; CHECK-LABEL: @n1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 8
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[X:%.*]], 8
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%tmp0 = shl i8 %x, 5
%tmp1 = lshr exact i8 %tmp0, 5 ; not ashr
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
index be2629dfdda57..38611d8b53a98 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
@@ -15,8 +15,8 @@
define i1 @p0(i8 %x, i8 %y) {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -31,8 +31,8 @@ define i1 @p0(i8 %x, i8 %y) {
define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @p1_vec(
; CHECK-NEXT: [[TMP0:%.*]] = lshr <2 x i8> <i8 -1, i8 -1>, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge <2 x i8> [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge <2 x i8> [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = lshr <2 x i8> <i8 -1, i8 -1>, %y
%tmp1 = and <2 x i8> %tmp0, %x
@@ -43,8 +43,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
define <3 x i1> @p2_vec_undef(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p2_vec_undef(
; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> <i8 -1, i8 undef, i8 -1>, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge <3 x i8> [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge <3 x i8> [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = lshr <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
%tmp1 = and <3 x i8> %tmp0, %x
@@ -62,8 +62,8 @@ define i1 @c0(i8 %y) {
; CHECK-LABEL: @c0(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%x = call i8 @gen8()
@@ -76,8 +76,8 @@ define i1 @c1(i8 %y) {
; CHECK-LABEL: @c1(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%x = call i8 @gen8()
@@ -90,8 +90,8 @@ define i1 @c2(i8 %y) {
; CHECK-LABEL: @c2(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%x = call i8 @gen8()
@@ -110,8 +110,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
call void @use8(i8 %tmp0)
@@ -125,8 +125,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[TMP1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[TMP0]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[TMP0]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -141,8 +141,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[TMP1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[TMP0]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[TMP0]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
index 354d6e7a1a73e..37d317b695f60 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
@@ -15,8 +15,8 @@
define i1 @p0(i8 %x, i8 %y) {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -31,8 +31,8 @@ define i1 @p0(i8 %x, i8 %y) {
define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @p1_vec(
; CHECK-NEXT: [[TMP0:%.*]] = lshr <2 x i8> <i8 -1, i8 -1>, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = lshr <2 x i8> <i8 -1, i8 -1>, %y
%tmp1 = and <2 x i8> %tmp0, %x
@@ -43,8 +43,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
define <3 x i1> @p2_vec_undef(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p2_vec_undef(
; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> <i8 -1, i8 undef, i8 -1>, [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <3 x i8> [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <3 x i8> [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%tmp0 = lshr <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
%tmp1 = and <3 x i8> %tmp0, %x
@@ -62,8 +62,8 @@ define i1 @c0(i8 %y) {
; CHECK-LABEL: @c0(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%x = call i8 @gen8()
@@ -76,8 +76,8 @@ define i1 @c1(i8 %y) {
; CHECK-LABEL: @c1(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%x = call i8 @gen8()
@@ -90,8 +90,8 @@ define i1 @c2(i8 %y) {
; CHECK-LABEL: @c2(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%x = call i8 @gen8()
@@ -110,8 +110,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-LABEL: @oneuse0(
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[TMP0]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
call void @use8(i8 %tmp0)
@@ -125,8 +125,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[TMP1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[TMP0]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[TMP0]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
%tmp1 = and i8 %tmp0, %x
@@ -141,8 +141,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[TMP1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[TMP0]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[TMP0]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%tmp0 = lshr i8 -1, %y
call void @use8(i8 %tmp0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll
index 2c2affff6d367..624b9baa37281 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll
@@ -17,8 +17,8 @@
define i1 @p0(i8 %x, i8 %y) {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -34,8 +34,8 @@ define i1 @p0(i8 %x, i8 %y) {
define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @p1_vec(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <2 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <2 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%t0 = shl <2 x i8> <i8 -1, i8 -1>, %y
%t1 = xor <2 x i8> %t0, <i8 -1, i8 -1>
@@ -47,8 +47,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p2_vec_undef0(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
%t1 = xor <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
@@ -60,8 +60,8 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p3_vec_undef0(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 -1, i8 -1>, %y
%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
@@ -73,8 +73,8 @@ define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
define <3 x i1> @p4_vec_undef2(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p4_vec_undef2(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
@@ -93,8 +93,8 @@ define i1 @c0(i8 %y) {
; CHECK-LABEL: @c0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -108,8 +108,8 @@ define i1 @c1(i8 %y) {
; CHECK-LABEL: @c1(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -123,8 +123,8 @@ define i1 @c2(i8 %y) {
; CHECK-LABEL: @c2(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -145,8 +145,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -161,8 +161,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -178,8 +178,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -195,8 +195,8 @@ define i1 @oneuse3(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -214,8 +214,8 @@ define i1 @oneuse4(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -234,8 +234,8 @@ define i1 @oneuse5(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll
index 1b0947b0f8c6d..4e1b90a476a26 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll
@@ -17,8 +17,8 @@
define i1 @p0(i8 %x, i8 %y) {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -34,8 +34,8 @@ define i1 @p0(i8 %x, i8 %y) {
define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @p1_vec(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <2 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%t0 = shl <2 x i8> <i8 -1, i8 -1>, %y
%t1 = xor <2 x i8> %t0, <i8 -1, i8 -1>
@@ -47,8 +47,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p2_vec_undef0(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
%t1 = xor <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
@@ -60,8 +60,8 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p3_vec_undef0(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 -1, i8 -1>, %y
%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
@@ -73,8 +73,8 @@ define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
define <3 x i1> @p4_vec_undef2(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @p4_vec_undef2(
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
@@ -93,8 +93,8 @@ define i1 @c0(i8 %y) {
; CHECK-LABEL: @c0(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -108,8 +108,8 @@ define i1 @c1(i8 %y) {
; CHECK-LABEL: @c1(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -123,8 +123,8 @@ define i1 @c2(i8 %y) {
; CHECK-LABEL: @c2(
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -145,8 +145,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -161,8 +161,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -178,8 +178,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
%t1 = xor i8 %t0, -1
@@ -195,8 +195,8 @@ define i1 @oneuse3(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -214,8 +214,8 @@ define i1 @oneuse4(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -234,8 +234,8 @@ define i1 @oneuse5(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
index d110c0150df8b..b774cd766a264 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
@@ -23,8 +23,8 @@ define i1 @p0(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -43,8 +43,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 -1>, [[Y:%.*]]
; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i8> [[T0]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge <2 x i8> [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge <2 x i8> [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%t0 = shl <2 x i8> <i8 -1, i8 -1>, %y
call void @use2i8(<2 x i8> %t0)
@@ -59,8 +59,8 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i8> [[T0]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge <3 x i8> [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge <3 x i8> [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
call void @use3i8(<3 x i8> %t0)
@@ -82,8 +82,8 @@ define i1 @c0(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[T1]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[T1]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -100,8 +100,8 @@ define i1 @c1(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[T1]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[T1]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -118,8 +118,8 @@ define i1 @c2(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[X]], [[T1]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ule i8 [[X]], [[T1]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -140,8 +140,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -159,8 +159,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -179,8 +179,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -217,8 +217,8 @@ define i1 @n1(i8 %x, i8 %y) {
; CHECK-LABEL: @n1(
; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 2
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[X:%.*]], 2
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y ; not -1
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
index b7e5d08066f83..c4865404c2f28 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
@@ -23,8 +23,8 @@ define i1 @p0(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -43,8 +43,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 -1>, [[Y:%.*]]
; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i8> [[T0]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i8> [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%t0 = shl <2 x i8> <i8 -1, i8 -1>, %y
call void @use2i8(<2 x i8> %t0)
@@ -59,8 +59,8 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i8> [[T0]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <3 x i8> [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <3 x i8> [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %y
call void @use3i8(<3 x i8> %t0)
@@ -82,8 +82,8 @@ define i1 @c0(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[T1]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[T1]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -100,8 +100,8 @@ define i1 @c1(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[T1]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[T1]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -118,8 +118,8 @@ define i1 @c2(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X]], [[T1]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X]], [[T1]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -140,8 +140,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -159,8 +159,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]]
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -179,8 +179,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 -1, %y
call void @use8(i8 %t0)
@@ -217,8 +217,8 @@ define i1 @n1(i8 %x, i8 %y) {
; CHECK-LABEL: @n1(
; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt i8 [[X:%.*]], 1
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y ; not -1
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll b/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
index 05e522d214ff7..ecdc00a3be6ae 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
@@ -26,8 +26,8 @@ define i8 @positive_samevar(i8 %x, i8 %y) {
define i8 @positive_sameconst(i8 %x) {
; CHECK-LABEL: @positive_sameconst(
-; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], -8
-; CHECK-NEXT: ret i8 [[TMP0]]
+; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], -8
+; CHECK-NEXT: ret i8 [[T0]]
;
%t0 = lshr i8 %x, 3
%ret = shl i8 %t0, 3
@@ -73,8 +73,8 @@ define i8 @positive_samevar_shlnuw(i8 %x, i8 %y) {
define i8 @positive_sameconst_shlnuw(i8 %x) {
; CHECK-LABEL: @positive_sameconst_shlnuw(
-; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], -8
-; CHECK-NEXT: ret i8 [[TMP0]]
+; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], -8
+; CHECK-NEXT: ret i8 [[T0]]
;
%t0 = lshr i8 %x, 3
%ret = shl nuw i8 %t0, 3
@@ -120,8 +120,8 @@ define i8 @positive_samevar_shlnsw(i8 %x, i8 %y) {
define i8 @positive_sameconst_shlnsw(i8 %x) {
; CHECK-LABEL: @positive_sameconst_shlnsw(
-; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], -8
-; CHECK-NEXT: ret i8 [[TMP0]]
+; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], -8
+; CHECK-NEXT: ret i8 [[T0]]
;
%t0 = lshr i8 %x, 3
%ret = shl nsw i8 %t0, 3
@@ -167,8 +167,8 @@ define i8 @positive_samevar_shlnuwnsw(i8 %x, i8 %y) {
define i8 @positive_sameconst_shlnuwnsw(i8 %x) {
; CHECK-LABEL: @positive_sameconst_shlnuwnsw(
-; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[X:%.*]], -8
-; CHECK-NEXT: ret i8 [[TMP0]]
+; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], -8
+; CHECK-NEXT: ret i8 [[T0]]
;
%t0 = lshr i8 %x, 3
%ret = shl nuw nsw i8 %t0, 3
@@ -386,8 +386,8 @@ define <2 x i8> @positive_samevar_vec(<2 x i8> %x, <2 x i8> %y) {
define <2 x i8> @positive_sameconst_vec(<2 x i8> %x) {
; CHECK-LABEL: @positive_sameconst_vec(
-; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i8> [[X:%.*]], <i8 -8, i8 -8>
-; CHECK-NEXT: ret <2 x i8> [[TMP0]]
+; CHECK-NEXT: [[T0:%.*]] = and <2 x i8> [[X:%.*]], <i8 -8, i8 -8>
+; CHECK-NEXT: ret <2 x i8> [[T0]]
;
%t0 = lshr <2 x i8> %x, <i8 3, i8 3>
%ret = shl <2 x i8> %t0, <i8 3, i8 3>
@@ -396,8 +396,8 @@ define <2 x i8> @positive_sameconst_vec(<2 x i8> %x) {
define <3 x i8> @positive_sameconst_vec_undef0(<3 x i8> %x) {
; CHECK-LABEL: @positive_sameconst_vec_undef0(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 undef, i8 3>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 undef, i8 3>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 3, i8 3, i8 3>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -407,8 +407,8 @@ define <3 x i8> @positive_sameconst_vec_undef0(<3 x i8> %x) {
define <3 x i8> @positive_sameconst_vec_undef1(<3 x i8> %x) {
; CHECK-LABEL: @positive_sameconst_vec_undef1(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 3, i8 undef, i8 3>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 3, i8 undef, i8 3>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 3, i8 3, i8 3>
@@ -439,8 +439,8 @@ define <2 x i8> @positive_biggerlshr_vec(<2 x i8> %x) {
define <3 x i8> @positive_biggerlshr_vec_undef0(<3 x i8> %x) {
; CHECK-LABEL: @positive_biggerlshr_vec_undef0(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 6, i8 undef, i8 6>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 6, i8 undef, i8 6>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 3, i8 3, i8 3>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 6, i8 undef, i8 6>
@@ -450,8 +450,8 @@ define <3 x i8> @positive_biggerlshr_vec_undef0(<3 x i8> %x) {
define <3 x i8> @positive_biggerlshr_vec_undef1(<3 x i8> %x) {
; CHECK-LABEL: @positive_biggerlshr_vec_undef1(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 6, i8 6, i8 6>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 3, i8 undef, i8 3>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 6, i8 6, i8 6>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 3, i8 undef, i8 3>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 6, i8 6, i8 6>
@@ -461,8 +461,8 @@ define <3 x i8> @positive_biggerlshr_vec_undef1(<3 x i8> %x) {
define <3 x i8> @positive_biggerlshr_vec_undef2(<3 x i8> %x) {
; CHECK-LABEL: @positive_biggerlshr_vec_undef2(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 6, i8 undef, i8 6>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 3, i8 undef, i8 3>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 6, i8 undef, i8 6>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 3, i8 undef, i8 3>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 6, i8 undef, i8 6>
@@ -483,8 +483,8 @@ define <2 x i8> @positive_biggershl_vec(<2 x i8> %x) {
define <3 x i8> @positive_biggershl_vec_undef0(<3 x i8> %x) {
; CHECK-LABEL: @positive_biggershl_vec_undef0(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 undef, i8 3>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 6, i8 6, i8 6>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 undef, i8 3>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 6, i8 6, i8 6>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -494,8 +494,8 @@ define <3 x i8> @positive_biggershl_vec_undef0(<3 x i8> %x) {
define <3 x i8> @positive_biggershl_vec_undef1(<3 x i8> %x) {
; CHECK-LABEL: @positive_biggershl_vec_undef1(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 6, i8 undef, i8 6>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 6, i8 undef, i8 6>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 3, i8 3, i8 3>
@@ -505,8 +505,8 @@ define <3 x i8> @positive_biggershl_vec_undef1(<3 x i8> %x) {
define <3 x i8> @positive_biggershl_vec_undef2(<3 x i8> %x) {
; CHECK-LABEL: @positive_biggershl_vec_undef2(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 undef, i8 3>
-; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[TMP0]], <i8 6, i8 undef, i8 6>
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i8> [[X:%.*]], <i8 3, i8 undef, i8 3>
+; CHECK-NEXT: [[RET:%.*]] = shl <3 x i8> [[T0]], <i8 6, i8 undef, i8 6>
; CHECK-NEXT: ret <3 x i8> [[RET]]
;
%t0 = lshr <3 x i8> %x, <i8 3, i8 undef, i8 3>
@@ -520,8 +520,8 @@ define <3 x i8> @positive_biggershl_vec_undef2(<3 x i8> %x) {
define i8 @positive_sameconst_multiuse(i8 %x) {
; CHECK-LABEL: @positive_sameconst_multiuse(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 [[X:%.*]], 3
-; CHECK-NEXT: call void @use32(i8 [[TMP0]])
+; CHECK-NEXT: [[T0:%.*]] = lshr i8 [[X:%.*]], 3
+; CHECK-NEXT: call void @use32(i8 [[T0]])
; CHECK-NEXT: [[RET:%.*]] = and i8 [[X]], -8
; CHECK-NEXT: ret i8 [[RET]]
;
@@ -533,9 +533,9 @@ define i8 @positive_sameconst_multiuse(i8 %x) {
define i8 @positive_biggerlshr_multiuse(i8 %x) {
; CHECK-LABEL: @positive_biggerlshr_multiuse(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 [[X:%.*]], 6
-; CHECK-NEXT: call void @use32(i8 [[TMP0]])
-; CHECK-NEXT: [[RET:%.*]] = shl nuw nsw i8 [[TMP0]], 3
+; CHECK-NEXT: [[T0:%.*]] = lshr i8 [[X:%.*]], 6
+; CHECK-NEXT: call void @use32(i8 [[T0]])
+; CHECK-NEXT: [[RET:%.*]] = shl nuw nsw i8 [[T0]], 3
; CHECK-NEXT: ret i8 [[RET]]
;
%t0 = lshr i8 %x, 6
@@ -546,9 +546,9 @@ define i8 @positive_biggerlshr_multiuse(i8 %x) {
define i8 @positive_biggershl_multiuse(i8 %x) {
; CHECK-LABEL: @positive_biggershl_multiuse(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 [[X:%.*]], 3
-; CHECK-NEXT: call void @use32(i8 [[TMP0]])
-; CHECK-NEXT: [[RET:%.*]] = shl i8 [[TMP0]], 6
+; CHECK-NEXT: [[T0:%.*]] = lshr i8 [[X:%.*]], 3
+; CHECK-NEXT: call void @use32(i8 [[T0]])
+; CHECK-NEXT: [[RET:%.*]] = shl i8 [[T0]], 6
; CHECK-NEXT: ret i8 [[RET]]
;
%t0 = lshr i8 %x, 3
@@ -563,8 +563,8 @@ define i8 @positive_biggershl_multiuse(i8 %x) {
define <2 x i8> @positive_biggerlshr_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @positive_biggerlshr_vec_nonsplat(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 3, i8 3>
-; CHECK-NEXT: [[RET:%.*]] = shl <2 x i8> [[TMP0]], <i8 3, i8 6>
+; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 3, i8 3>
+; CHECK-NEXT: [[RET:%.*]] = shl <2 x i8> [[T0]], <i8 3, i8 6>
; CHECK-NEXT: ret <2 x i8> [[RET]]
;
%t0 = lshr <2 x i8> %x, <i8 3, i8 3>
@@ -574,8 +574,8 @@ define <2 x i8> @positive_biggerlshr_vec_nonsplat(<2 x i8> %x) {
define <2 x i8> @positive_biggerLlshr_vec_nonsplat(<2 x i8> %x) {
; CHECK-LABEL: @positive_biggerLlshr_vec_nonsplat(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 3, i8 6>
-; CHECK-NEXT: [[RET:%.*]] = shl <2 x i8> [[TMP0]], <i8 3, i8 3>
+; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 3, i8 6>
+; CHECK-NEXT: [[RET:%.*]] = shl <2 x i8> [[T0]], <i8 3, i8 3>
; CHECK-NEXT: ret <2 x i8> [[RET]]
;
%t0 = lshr <2 x i8> %x, <i8 3, i8 6>
@@ -589,8 +589,8 @@ define <2 x i8> @positive_biggerLlshr_vec_nonsplat(<2 x i8> %x) {
define i8 @negative_twovars(i8 %x, i8 %y, i8 %z) {
; CHECK-LABEL: @negative_twovars(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[RET:%.*]] = shl i8 [[TMP0]], [[Z:%.*]]
+; CHECK-NEXT: [[T0:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = shl i8 [[T0]], [[Z:%.*]]
; CHECK-NEXT: ret i8 [[RET]]
;
%t0 = lshr i8 %x, %y
@@ -603,9 +603,9 @@ declare void @use32(i8)
; One use only.
define i8 @negative_oneuse(i8 %x, i8 %y) {
; CHECK-LABEL: @negative_oneuse(
-; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: call void @use32(i8 [[TMP0]])
-; CHECK-NEXT: [[RET:%.*]] = shl i8 [[TMP0]], [[Y]]
+; CHECK-NEXT: [[T0:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: call void @use32(i8 [[T0]])
+; CHECK-NEXT: [[RET:%.*]] = shl i8 [[T0]], [[Y]]
; CHECK-NEXT: ret i8 [[RET]]
;
%t0 = lshr i8 %x, %y
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
index 27b29a879ea72..5883c089119c4 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
@@ -9,7 +9,7 @@ define i8 @p0(i8 %x, i8 %v0, i8 %v1) {
; CHECK-LABEL: @p0(
; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1
; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0
-; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]], !prof !0
+; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]], !prof [[PROF0:![0-9]+]]
; CHECK-NEXT: ret i8 [[R]]
;
%t0 = and i8 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll b/llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll
index 40beb17106847..b9875fb9780fa 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll
@@ -198,8 +198,8 @@ define i1 @n0(i8 %x) {
define i1 @n1(i8 %x) {
; CHECK-LABEL: @n1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 7
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i8 [[X:%.*]], 7
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%tmp0 = shl i8 %x, 5
%tmp1 = lshr exact i8 %tmp0, 5 ; not ashr
diff --git a/llvm/test/Transforms/InstCombine/cast-set.ll b/llvm/test/Transforms/InstCombine/cast-set.ll
index a86804d9d703e..4685a84fab0be 100644
--- a/llvm/test/Transforms/InstCombine/cast-set.ll
+++ b/llvm/test/Transforms/InstCombine/cast-set.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
define i1 @test1(i32 %X) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[C:%.*]] = icmp ne i32 %X, 12
+; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[X:%.*]], 12
; CHECK-NEXT: ret i1 [[C]]
;
%A = bitcast i32 %X to i32
@@ -16,7 +16,7 @@ define i1 @test1(i32 %X) {
define i1 @test2(i32 %X, i32 %Y) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[C:%.*]] = icmp ne i32 %X, %Y
+; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[C]]
;
%A = bitcast i32 %X to i32
@@ -28,7 +28,7 @@ define i1 @test2(i32 %X, i32 %Y) {
define i32 @test4(i32 %A) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[C:%.*]] = shl i32 %A, 2
+; CHECK-NEXT: [[C:%.*]] = shl i32 [[A:%.*]], 2
; CHECK-NEXT: ret i32 [[C]]
;
%B = bitcast i32 %A to i32
@@ -39,8 +39,8 @@ define i32 @test4(i32 %A) {
define i16 @test5(i16 %A) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[C:%.*]] = and i16 %A, 15
-; CHECK-NEXT: ret i16 [[C]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[A:%.*]], 15
+; CHECK-NEXT: ret i16 [[TMP1]]
;
%B = sext i16 %A to i32
%C = and i32 %B, 15
@@ -50,7 +50,7 @@ define i16 @test5(i16 %A) {
define i1 @test6(i1 %A) {
; CHECK-LABEL: @test6(
-; CHECK-NEXT: ret i1 %A
+; CHECK-NEXT: ret i1 [[A:%.*]]
;
%B = zext i1 %A to i32
%C = icmp ne i32 %B, 0
@@ -68,7 +68,7 @@ define i1 @test6a(i1 %A) {
define i1 @test7(ptr %A) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[C:%.*]] = icmp eq ptr %A, null
+; CHECK-NEXT: [[C:%.*]] = icmp eq ptr [[A:%.*]], null
; CHECK-NEXT: ret i1 [[C]]
;
%C = icmp eq ptr %A, null
diff --git a/llvm/test/Transforms/InstCombine/cast_phi.ll b/llvm/test/Transforms/InstCombine/cast_phi.ll
index fafcd39090318..feeee16e27f23 100644
--- a/llvm/test/Transforms/InstCombine/cast_phi.ll
+++ b/llvm/test/Transforms/InstCombine/cast_phi.ll
@@ -248,13 +248,13 @@ define i64 @zext_from_legal_to_legal_type(i32 %x) {
; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
; CHECK: t:
; CHECK-NEXT: [[Y:%.*]] = call i32 @get_i32()
-; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i32 [[Y]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[Y]] to i64
; CHECK-NEXT: br label [[EXIT:%.*]]
; CHECK: f:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[PHI_CAST]], [[T]] ], [ 3, [[F]] ]
+; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[TMP0]], [[T]] ], [ 3, [[F]] ]
; CHECK-NEXT: ret i64 [[P]]
;
entry:
@@ -282,13 +282,13 @@ define i64 @zext_from_illegal_to_legal_type(i32 %x) {
; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
; CHECK: t:
; CHECK-NEXT: [[Y:%.*]] = call i3 @get_i3()
-; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i3 [[Y]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = zext i3 [[Y]] to i64
; CHECK-NEXT: br label [[EXIT:%.*]]
; CHECK: f:
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[PHI_CAST]], [[T]] ], [ 3, [[F]] ]
+; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[TMP0]], [[T]] ], [ 3, [[F]] ]
; CHECK-NEXT: ret i64 [[P]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
index f2cecd34228d0..65a89976cf713 100644
--- a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
+++ b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
@@ -217,7 +217,7 @@ define <2 x i1> @ctlz_ult_other_v2i32(<2 x i32> %x) {
define <2 x i1> @ctlz_ult_other_multiuse_v2i32(<2 x i32> %x, ptr %p) {
; CHECK-LABEL: @ctlz_ult_other_multiuse_v2i32(
-; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: store <2 x i32> [[LZ]], ptr [[P:%.*]], align 8
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X]], <i32 65535, i32 65535>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
@@ -424,7 +424,7 @@ define <2 x i1> @cttz_ult_other_v2i32(<2 x i32> %x) {
define <2 x i1> @cttz_ult_other_multiuse_v2i32(<2 x i32> %x, ptr %p) {
; CHECK-LABEL: @cttz_ult_other_multiuse_v2i32(
-; CHECK-NEXT: [[TZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[TZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: store <2 x i32> [[TZ]], ptr [[P:%.*]], align 8
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[TZ]], <i32 16, i32 16>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
diff --git a/llvm/test/Transforms/InstCombine/compare-signs.ll b/llvm/test/Transforms/InstCombine/compare-signs.ll
index 2e3a59556be14..d7aa710e1ef03 100644
--- a/llvm/test/Transforms/InstCombine/compare-signs.ll
+++ b/llvm/test/Transforms/InstCombine/compare-signs.ll
@@ -6,8 +6,8 @@
define i32 @test1(i32 %a, i32 %b) nounwind readnone {
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: [[T3:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: [[T3:%.*]] = zext i1 [[T2]] to i32
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = icmp sgt i32 %a, -1
@@ -23,8 +23,8 @@ define i32 @test2(i32 %a, i32 %b) nounwind readnone {
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 3
; CHECK-NEXT: [[DOTLOBIT:%.*]] = and i32 [[TMP2]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[DOTLOBIT]], 1
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[DOTLOBIT]], 1
+; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = and i32 %a, 8
%t1 = and i32 %b, 8
diff --git a/llvm/test/Transforms/InstCombine/compare-udiv.ll b/llvm/test/Transforms/InstCombine/compare-udiv.ll
index 0d8c05d5c6bd1..20e719cafa6ab 100644
--- a/llvm/test/Transforms/InstCombine/compare-udiv.ll
+++ b/llvm/test/Transforms/InstCombine/compare-udiv.ll
@@ -3,7 +3,7 @@
define i1 @test1(i32 %n, i32 %d) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, %n
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], [[N:%.*]]
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 %n, %d
@@ -13,7 +13,7 @@ define i1 @test1(i32 %n, i32 %d) {
define <2 x i1> @test1vec(<2 x i32> %n, <2 x i32> %d) {
; CHECK-LABEL: @test1vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, %n
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], [[N:%.*]]
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> %n, %d
@@ -23,7 +23,7 @@ define <2 x i1> @test1vec(<2 x i32> %n, <2 x i32> %d) {
define i1 @test2(i32 %d) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, 64
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 64
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 64, %d
@@ -33,7 +33,7 @@ define i1 @test2(i32 %d) {
define <2 x i1> @test2vec(<2 x i32> %d) {
; CHECK-LABEL: @test2vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, <i32 64, i32 63>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], <i32 64, i32 63>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 64, i32 63>, %d
@@ -43,7 +43,7 @@ define <2 x i1> @test2vec(<2 x i32> %d) {
define i1 @test3(i32 %n, i32 %d) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ule i32 %d, %n
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ule i32 [[D:%.*]], [[N:%.*]]
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 %n, %d
@@ -53,7 +53,7 @@ define i1 @test3(i32 %n, i32 %d) {
define <2 x i1> @test3vec(<2 x i32> %n, <2 x i32> %d) {
; CHECK-LABEL: @test3vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ule <2 x i32> %d, %n
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ule <2 x i32> [[D:%.*]], [[N:%.*]]
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> %n, %d
@@ -63,7 +63,7 @@ define <2 x i1> @test3vec(<2 x i32> %n, <2 x i32> %d) {
define i1 @test4(i32 %d) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %d, 65
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 65
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 64, %d
@@ -73,7 +73,7 @@ define i1 @test4(i32 %d) {
define <2 x i1> @test4vec(<2 x i32> %d) {
; CHECK-LABEL: @test4vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> %d, <i32 65, i32 66>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], <i32 65, i32 66>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 64, i32 65>, %d
@@ -101,7 +101,7 @@ define <2 x i1> @test5vec(<2 x i32> %d) {
define i1 @test6(i32 %d) {
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %d, 6
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 6
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 5, %d
@@ -111,7 +111,7 @@ define i1 @test6(i32 %d) {
define <2 x i1> @test6vec(<2 x i32> %d) {
; CHECK-LABEL: @test6vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> %d, <i32 6, i32 6>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], <i32 6, i32 6>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 5, i32 5>, %d
@@ -140,7 +140,7 @@ define <2 x i1> @test7vec(<2 x i32> %d) {
define i1 @test8(i32 %d) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %d, 2
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 2
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -150,7 +150,7 @@ define i1 @test8(i32 %d) {
define <2 x i1> @test8vec(<2 x i32> %d) {
; CHECK-LABEL: @test8vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> %d, <i32 2, i32 2>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], <i32 2, i32 2>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
@@ -160,7 +160,7 @@ define <2 x i1> @test8vec(<2 x i32> %d) {
define i1 @test9(i32 %d) {
; CHECK-LABEL: @test9(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %d, 2
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 2
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -170,7 +170,7 @@ define i1 @test9(i32 %d) {
define <2 x i1> @test9vec(<2 x i32> %d) {
; CHECK-LABEL: @test9vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> %d, <i32 2, i32 2>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], <i32 2, i32 2>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
@@ -180,7 +180,7 @@ define <2 x i1> @test9vec(<2 x i32> %d) {
define i1 @test10(i32 %d) {
; CHECK-LABEL: @test10(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 %d, 3
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 3
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -190,7 +190,7 @@ define i1 @test10(i32 %d) {
define <2 x i1> @test10vec(<2 x i32> %d) {
; CHECK-LABEL: @test10vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> %d, <i32 3, i32 3>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], <i32 3, i32 3>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
@@ -200,7 +200,7 @@ define <2 x i1> @test10vec(<2 x i32> %d) {
define i1 @test11(i32 %d) {
; CHECK-LABEL: @test11(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, 4
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 4
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -210,7 +210,7 @@ define i1 @test11(i32 %d) {
define <2 x i1> @test11vec(<2 x i32> %d) {
; CHECK-LABEL: @test11vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, <i32 4, i32 4>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], <i32 4, i32 4>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
@@ -220,7 +220,7 @@ define <2 x i1> @test11vec(<2 x i32> %d) {
define i1 @test12(i32 %d) {
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, 2
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 2
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -230,7 +230,7 @@ define i1 @test12(i32 %d) {
define <2 x i1> @test12vec(<2 x i32> %d) {
; CHECK-LABEL: @test12vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, <i32 2, i32 2>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], <i32 2, i32 2>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
@@ -240,7 +240,7 @@ define <2 x i1> @test12vec(<2 x i32> %d) {
define i1 @test13(i32 %d) {
; CHECK-LABEL: @test13(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 1
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -250,7 +250,7 @@ define i1 @test13(i32 %d) {
define <2 x i1> @test13vec(<2 x i32> %d) {
; CHECK-LABEL: @test13vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, <i32 1, i32 1>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
@@ -260,7 +260,7 @@ define <2 x i1> @test13vec(<2 x i32> %d) {
define i1 @test14(i32 %d) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 %d, 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 1
; CHECK-NEXT: ret i1 [[CMP1]]
;
%div = udiv i32 4, %d
@@ -270,7 +270,7 @@ define i1 @test14(i32 %d) {
define <2 x i1> @test14vec(<2 x i32> %d) {
; CHECK-LABEL: @test14vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> %d, <i32 1, i32 1>
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i1> [[CMP1]]
;
%div = udiv <2 x i32> <i32 4, i32 4>, %d
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll b/llvm/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
index d0714ca5f8165..e59f7529c6722 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll
@@ -223,7 +223,7 @@ define i32 @test_cast_gep_large_indices_as() {
define i32 @test_constant_cast_gep_struct_indices_as() {
; CHECK-LABEL: @test_constant_cast_gep_struct_indices_as(
-; CHECK-NEXT: [[Y:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds (%struct.foo, ptr addrspace(3) @constant_fold_global_ptr, i16 0, i32 2, i16 2), align 16
+; CHECK-NEXT: [[Y:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([[STRUCT_FOO:%.*]], ptr addrspace(3) @constant_fold_global_ptr, i16 0, i32 2, i16 2), align 16
; CHECK-NEXT: ret i32 [[Y]]
;
%x = getelementptr %struct.foo, ptr addrspace(3) @constant_fold_global_ptr, i18 0, i32 2, i12 2
diff --git a/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll b/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
index 63596a02f945b..db839e86f2532 100644
--- a/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
+++ b/llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
@@ -45,8 +45,8 @@ define half @copysign_fneg_y(half %x, half %y) {
define half @copysign_fabs_y(half %x, half %y) {
; CHECK-LABEL: @copysign_fabs_y(
-; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[COPYSIGN:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: ret half [[COPYSIGN]]
;
%fabs.y = call half @llvm.fabs.f16(half %y)
%copysign = call half @llvm.copysign.f16(half %x, half %fabs.y)
@@ -69,8 +69,8 @@ define half @copysign_fneg_fabs_y(half %x, half %y) {
define half @fneg_copysign(half %x, half %y) {
; CHECK-LABEL: @fneg_copysign(
; CHECK-NEXT: [[TMP1:%.*]] = fneg half [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
-; CHECK-NEXT: ret half [[TMP2]]
+; CHECK-NEXT: [[FNEG_COPYSIGN:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
+; CHECK-NEXT: ret half [[FNEG_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
%fneg.copysign = fneg half %copysign
@@ -79,8 +79,8 @@ define half @fneg_copysign(half %x, half %y) {
define half @fneg_fabs_copysign(half %x, half %y) {
; CHECK-LABEL: @fneg_fabs_copysign(
-; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg half [[FABS_COPYSIGN]]
; CHECK-NEXT: ret half [[FNEG_FABS_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
@@ -92,8 +92,8 @@ define half @fneg_fabs_copysign(half %x, half %y) {
; https://alive2.llvm.org/ce/z/Ft-7ea
define half @fabs_copysign(half %x, half %y) {
; CHECK-LABEL: @fabs_copysign(
-; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
%fabs.copysign = call half @llvm.fabs.f16(half %copysign)
@@ -103,8 +103,8 @@ define half @fabs_copysign(half %x, half %y) {
define <2 x half> @fneg_copysign_vector(<2 x half> %x, <2 x half> %y) {
; CHECK-LABEL: @fneg_copysign_vector(
; CHECK-NEXT: [[TMP1:%.*]] = fneg <2 x half> [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[X:%.*]], <2 x half> [[TMP1]])
-; CHECK-NEXT: ret <2 x half> [[TMP2]]
+; CHECK-NEXT: [[FNEG_COPYSIGN:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[X:%.*]], <2 x half> [[TMP1]])
+; CHECK-NEXT: ret <2 x half> [[FNEG_COPYSIGN]]
;
%copysign = call <2 x half> @llvm.copysign.v2f16(<2 x half> %x, <2 x half> %y)
%fneg.copysign = fneg <2 x half> %copysign
@@ -113,8 +113,8 @@ define <2 x half> @fneg_copysign_vector(<2 x half> %x, <2 x half> %y) {
define <2 x half> @fneg_fabs_copysign_vector(<2 x half> %x, <2 x half> %y) {
; CHECK-LABEL: @fneg_fabs_copysign_vector(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg <2 x half> [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
+; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg <2 x half> [[FABS_COPYSIGN]]
; CHECK-NEXT: ret <2 x half> [[FNEG_FABS_COPYSIGN]]
;
%copysign = call <2 x half> @llvm.copysign.v2f16(<2 x half> %x, <2 x half> %y)
@@ -125,8 +125,8 @@ define <2 x half> @fneg_fabs_copysign_vector(<2 x half> %x, <2 x half> %y) {
define <2 x half> @fabs_copysign_vector(<2 x half> %x, <2 x half> %y) {
; CHECK-LABEL: @fabs_copysign_vector(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT: ret <2 x half> [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
+; CHECK-NEXT: ret <2 x half> [[FABS_COPYSIGN]]
;
%copysign = call <2 x half> @llvm.copysign.v2f16(<2 x half> %x, <2 x half> %y)
%fabs.copysign = call <2 x half> @llvm.fabs.v2f16(<2 x half> %copysign)
@@ -136,8 +136,8 @@ define <2 x half> @fabs_copysign_vector(<2 x half> %x, <2 x half> %y) {
define half @fneg_copysign_flags(half %x, half %y) {
; CHECK-LABEL: @fneg_copysign_flags(
; CHECK-NEXT: [[TMP1:%.*]] = fneg nsz half [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call nsz half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
-; CHECK-NEXT: ret half [[TMP2]]
+; CHECK-NEXT: [[FNEG_COPYSIGN:%.*]] = call nsz half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
+; CHECK-NEXT: ret half [[FNEG_COPYSIGN]]
;
%copysign = call nnan nsz half @llvm.copysign.f16(half %x, half %y)
%fneg.copysign = fneg ninf nsz half %copysign
@@ -146,8 +146,8 @@ define half @fneg_copysign_flags(half %x, half %y) {
define half @fneg_fabs_copysign_flags(half %x, half %y) {
; CHECK-LABEL: @fneg_fabs_copysign_flags(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg reassoc ninf half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call nnan ninf afn half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg reassoc ninf half [[FABS_COPYSIGN]]
; CHECK-NEXT: ret half [[FNEG_FABS_COPYSIGN]]
;
%copysign = call nnan nsz ninf half @llvm.copysign.f16(half %x, half %y)
@@ -160,8 +160,8 @@ define half @fneg_fabs_copysign_flags(half %x, half %y) {
define half @fneg_nsz_copysign(half %x, half %y) {
; CHECK-LABEL: @fneg_nsz_copysign(
; CHECK-NEXT: [[TMP1:%.*]] = fneg half [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
-; CHECK-NEXT: ret half [[TMP2]]
+; CHECK-NEXT: [[FNEG_COPYSIGN:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[TMP1]])
+; CHECK-NEXT: ret half [[FNEG_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
%fneg.copysign = fneg nsz half %copysign
@@ -170,8 +170,8 @@ define half @fneg_nsz_copysign(half %x, half %y) {
define half @fneg_fabs_copysign_flags_none_fabs(half %x, half %y) {
; CHECK-LABEL: @fneg_fabs_copysign_flags_none_fabs(
-; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg fast half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg fast half [[FABS_COPYSIGN]]
; CHECK-NEXT: ret half [[FNEG_FABS_COPYSIGN]]
;
%copysign = call nnan nsz ninf half @llvm.copysign.f16(half %x, half %y)
@@ -182,8 +182,8 @@ define half @fneg_fabs_copysign_flags_none_fabs(half %x, half %y) {
define half @fabs_copysign_flags(half %x, half %y) {
; CHECK-LABEL: @fabs_copysign_flags(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call nnan nsz half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call nnan half @llvm.copysign.f16(half %x, half %y)
%fabs.copysign = call nsz nnan half @llvm.fabs.f16(half %copysign)
@@ -192,8 +192,8 @@ define half @fabs_copysign_flags(half %x, half %y) {
define half @fabs_copysign_all_flags(half %x, half %y) {
; CHECK-LABEL: @fabs_copysign_all_flags(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call fast half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call fast half @llvm.copysign.f16(half %x, half %y)
%fabs.copysign = call fast half @llvm.fabs.f16(half %copysign)
@@ -204,8 +204,8 @@ define half @fabs_copysign_no_flags_copysign_user(half %x, half %y, ptr %ptr) {
; CHECK-LABEL: @fabs_copysign_no_flags_copysign_user(
; CHECK-NEXT: [[COPYSIGN:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
; CHECK-NEXT: store half [[COPYSIGN]], ptr [[PTR:%.*]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = call fast half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call fast half @llvm.fabs.f16(half [[X]])
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
store half %copysign, ptr %ptr
@@ -215,8 +215,8 @@ define half @fabs_copysign_no_flags_copysign_user(half %x, half %y, ptr %ptr) {
define half @fneg_fabs_copysign_drop_flags(half %x, half %y) {
; CHECK-LABEL: @fneg_fabs_copysign_drop_flags(
-; CHECK-NEXT: [[TMP1:%.*]] = call ninf half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg nsz half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call ninf half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: [[FNEG_FABS_COPYSIGN:%.*]] = fneg nsz half [[FABS_COPYSIGN]]
; CHECK-NEXT: ret half [[FNEG_FABS_COPYSIGN]]
;
%copysign = call nnan half @llvm.copysign.f16(half %x, half %y)
@@ -242,8 +242,8 @@ define half @fabs_copysign_multi_use(half %x, half %y, ptr %ptr) {
; CHECK-LABEL: @fabs_copysign_multi_use(
; CHECK-NEXT: [[COPYSIGN:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
; CHECK-NEXT: store half [[COPYSIGN]], ptr [[PTR:%.*]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call half @llvm.fabs.f16(half [[X]])
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
store half %copysign, ptr %ptr
@@ -255,8 +255,8 @@ define half @fabs_flags_copysign_multi_use(half %x, half %y, ptr %ptr) {
; CHECK-LABEL: @fabs_flags_copysign_multi_use(
; CHECK-NEXT: [[COPYSIGN:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
; CHECK-NEXT: store half [[COPYSIGN]], ptr [[PTR:%.*]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf half @llvm.fabs.f16(half [[X]])
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call nnan ninf half @llvm.fabs.f16(half [[X]])
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
store half %copysign, ptr %ptr
@@ -266,9 +266,9 @@ define half @fabs_flags_copysign_multi_use(half %x, half %y, ptr %ptr) {
define half @fneg_fabs_copysign_multi_use_fabs(half %x, half %y, ptr %ptr) {
; CHECK-LABEL: @fneg_fabs_copysign_multi_use_fabs(
-; CHECK-NEXT: [[TMP1:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT: store half [[TMP1]], ptr [[PTR:%.*]], align 2
-; CHECK-NEXT: ret half [[TMP1]]
+; CHECK-NEXT: [[FABS_COPYSIGN:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT: store half [[FABS_COPYSIGN]], ptr [[PTR:%.*]], align 2
+; CHECK-NEXT: ret half [[FABS_COPYSIGN]]
;
%copysign = call half @llvm.copysign.f16(half %x, half %y)
%fabs.copysign = call half @llvm.fabs.f16(half %copysign)
diff --git a/llvm/test/Transforms/InstCombine/copysign.ll b/llvm/test/Transforms/InstCombine/copysign.ll
index 6058fb6466970..abc707acf0cd3 100644
--- a/llvm/test/Transforms/InstCombine/copysign.ll
+++ b/llvm/test/Transforms/InstCombine/copysign.ll
@@ -8,8 +8,8 @@ declare <3 x double> @llvm.copysign.v3f64(<3 x double>, <3 x double>)
define float @positive_sign_arg(float %x) {
; CHECK-LABEL: @positive_sign_arg(
-; CHECK-NEXT: [[TMP1:%.*]] = call arcp float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call arcp float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: ret float [[R]]
;
%r = call arcp float @llvm.copysign.f32(float %x, float 0.0)
ret float %r
@@ -17,8 +17,8 @@ define float @positive_sign_arg(float %x) {
define <3 x double> @positive_sign_arg_vec_splat(<3 x double> %x) {
; CHECK-LABEL: @positive_sign_arg_vec_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = call ninf <3 x double> @llvm.fabs.v3f64(<3 x double> [[X:%.*]])
-; CHECK-NEXT: ret <3 x double> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call ninf <3 x double> @llvm.fabs.v3f64(<3 x double> [[X:%.*]])
+; CHECK-NEXT: ret <3 x double> [[R]]
;
%r = call ninf <3 x double> @llvm.copysign.v3f64(<3 x double> %x, <3 x double> <double 42.0, double 42.0, double 42.0>)
ret <3 x double> %r
@@ -27,8 +27,8 @@ define <3 x double> @positive_sign_arg_vec_splat(<3 x double> %x) {
define float @negative_sign_arg(float %x) {
; CHECK-LABEL: @negative_sign_arg(
; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fneg nnan float [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = fneg nnan float [[TMP1]]
+; CHECK-NEXT: ret float [[R]]
;
%r = call nnan float @llvm.copysign.f32(float %x, float -0.0)
ret float %r
@@ -37,8 +37,8 @@ define float @negative_sign_arg(float %x) {
define <3 x double> @negative_sign_arg_vec_splat(<3 x double> %x) {
; CHECK-LABEL: @negative_sign_arg_vec_splat(
; CHECK-NEXT: [[TMP1:%.*]] = call fast <3 x double> @llvm.fabs.v3f64(<3 x double> [[X:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fneg fast <3 x double> [[TMP1]]
-; CHECK-NEXT: ret <3 x double> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = fneg fast <3 x double> [[TMP1]]
+; CHECK-NEXT: ret <3 x double> [[R]]
;
%r = call fast <3 x double> @llvm.copysign.v3f64(<3 x double> %x, <3 x double> <double -42.0, double -42.0, double -42.0>)
ret <3 x double> %r
@@ -46,8 +46,8 @@ define <3 x double> @negative_sign_arg_vec_splat(<3 x double> %x) {
define float @known_positive_sign_arg(float %x, float %y) {
; CHECK-LABEL: @known_positive_sign_arg(
-; CHECK-NEXT: [[TMP1:%.*]] = call ninf float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call ninf float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: ret float [[R]]
;
%fabs = call float @llvm.fabs.f32(float %y)
%r = call ninf float @llvm.copysign.f32(float %x, float %fabs)
@@ -56,8 +56,8 @@ define float @known_positive_sign_arg(float %x, float %y) {
define <3 x double> @known_positive_sign_arg_vec(<3 x double> %x, <3 x i32> %y) {
; CHECK-LABEL: @known_positive_sign_arg_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call arcp <3 x double> @llvm.fabs.v3f64(<3 x double> [[X:%.*]])
-; CHECK-NEXT: ret <3 x double> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call arcp <3 x double> @llvm.fabs.v3f64(<3 x double> [[X:%.*]])
+; CHECK-NEXT: ret <3 x double> [[R]]
;
%yf = uitofp <3 x i32> %y to <3 x double>
%r = call arcp <3 x double> @llvm.copysign.v3f64(<3 x double> %x, <3 x double> %yf)
diff --git a/llvm/test/Transforms/InstCombine/cos-1.ll b/llvm/test/Transforms/InstCombine/cos-1.ll
index e095e2bfbbd78..7cdb1d2f2b678 100644
--- a/llvm/test/Transforms/InstCombine/cos-1.ll
+++ b/llvm/test/Transforms/InstCombine/cos-1.ll
@@ -105,8 +105,8 @@ define float @cosf_unary_negated_arg_FMF(float %x) {
define double @sin_negated_arg(double %x) {
; ANY-LABEL: @sin_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call double @sin(double [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]]
-; ANY-NEXT: ret double [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg double [[TMP1]]
+; ANY-NEXT: ret double [[R]]
;
%neg = fsub double -0.0, %x
%r = call double @sin(double %neg)
@@ -116,8 +116,8 @@ define double @sin_negated_arg(double %x) {
define double @sin_unary_negated_arg(double %x) {
; ANY-LABEL: @sin_unary_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call double @sin(double [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]]
-; ANY-NEXT: ret double [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg double [[TMP1]]
+; ANY-NEXT: ret double [[R]]
;
%neg = fneg double %x
%r = call double @sin(double %neg)
@@ -138,8 +138,8 @@ define double @sin_unary_negated_arg_musttail(double %x) {
define float @sinf_negated_arg(float %x) {
; ANY-LABEL: @sinf_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call float @sinf(float [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]]
-; ANY-NEXT: ret float [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg float [[TMP1]]
+; ANY-NEXT: ret float [[R]]
;
%neg = fsub float -0.0, %x
%r = call float @sinf(float %neg)
@@ -149,8 +149,8 @@ define float @sinf_negated_arg(float %x) {
define float @sinf_unary_negated_arg(float %x) {
; ANY-LABEL: @sinf_unary_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call float @sinf(float [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]]
-; ANY-NEXT: ret float [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg float [[TMP1]]
+; ANY-NEXT: ret float [[R]]
;
%neg = fneg float %x
%r = call float @sinf(float %neg)
@@ -160,8 +160,8 @@ define float @sinf_unary_negated_arg(float %x) {
define float @sinf_negated_arg_FMF(float %x) {
; ANY-LABEL: @sinf_negated_arg_FMF(
; ANY-NEXT: [[TMP1:%.*]] = call nnan afn float @sinf(float [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg nnan afn float [[TMP1]]
-; ANY-NEXT: ret float [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg nnan afn float [[TMP1]]
+; ANY-NEXT: ret float [[R]]
;
%neg = fsub ninf float -0.0, %x
%r = call afn nnan float @sinf(float %neg)
@@ -171,8 +171,8 @@ define float @sinf_negated_arg_FMF(float %x) {
define float @sinf_unary_negated_arg_FMF(float %x) {
; ANY-LABEL: @sinf_unary_negated_arg_FMF(
; ANY-NEXT: [[TMP1:%.*]] = call nnan afn float @sinf(float [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg nnan afn float [[TMP1]]
-; ANY-NEXT: ret float [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg nnan afn float [[TMP1]]
+; ANY-NEXT: ret float [[R]]
;
%neg = fneg ninf float %x
%r = call afn nnan float @sinf(float %neg)
@@ -259,8 +259,8 @@ define double @unary_neg_sin_negated_arg(double %x) {
define double @tan_negated_arg(double %x) {
; ANY-LABEL: @tan_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call double @tan(double [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]]
-; ANY-NEXT: ret double [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg double [[TMP1]]
+; ANY-NEXT: ret double [[R]]
;
%neg = fsub double -0.0, %x
%r = call double @tan(double %neg)
@@ -270,8 +270,8 @@ define double @tan_negated_arg(double %x) {
define double @tan_negated_arg_tail(double %x) {
; ANY-LABEL: @tan_negated_arg_tail(
; ANY-NEXT: [[TMP1:%.*]] = tail call double @tan(double [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]]
-; ANY-NEXT: ret double [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg double [[TMP1]]
+; ANY-NEXT: ret double [[R]]
;
%neg = fsub double -0.0, %x
%r = tail call double @tan(double %neg)
@@ -291,8 +291,8 @@ define double @tan_negated_arg_musttail(double %x) {
define double @tan_unary_negated_arg(double %x) {
; ANY-LABEL: @tan_unary_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call double @tan(double [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]]
-; ANY-NEXT: ret double [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg double [[TMP1]]
+; ANY-NEXT: ret double [[R]]
;
%neg = fneg double %x
%r = call double @tan(double %neg)
@@ -304,8 +304,8 @@ define double @tan_unary_negated_arg(double %x) {
define fp128 @tanl_negated_arg(fp128 %x) {
; ANY-LABEL: @tanl_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call fp128 @tanl(fp128 [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg fp128 [[TMP1]]
-; ANY-NEXT: ret fp128 [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg fp128 [[TMP1]]
+; ANY-NEXT: ret fp128 [[R]]
;
%neg = fsub fp128 0xL00000000000000008000000000000000, %x
%r = call fp128 @tanl(fp128 %neg)
@@ -315,8 +315,8 @@ define fp128 @tanl_negated_arg(fp128 %x) {
define fp128 @tanl_unary_negated_arg(fp128 %x) {
; ANY-LABEL: @tanl_unary_negated_arg(
; ANY-NEXT: [[TMP1:%.*]] = call fp128 @tanl(fp128 [[X:%.*]])
-; ANY-NEXT: [[TMP2:%.*]] = fneg fp128 [[TMP1]]
-; ANY-NEXT: ret fp128 [[TMP2]]
+; ANY-NEXT: [[R:%.*]] = fneg fp128 [[TMP1]]
+; ANY-NEXT: ret fp128 [[R]]
;
%neg = fneg fp128 %x
%r = call fp128 @tanl(fp128 %neg)
diff --git a/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll b/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll
index fa9e0bfd039b2..a5189f4765056 100644
--- a/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll
+++ b/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll
@@ -3,8 +3,8 @@
define i32 @ctlz_true_bitreverse(i32 %x) {
; CHECK-LABEL: @ctlz_true_bitreverse(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range !0
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]]
+; CHECK-NEXT: ret i32 [[B]]
;
%a = tail call i32 @llvm.bitreverse.i32(i32 %x)
%b = tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
@@ -13,8 +13,8 @@ define i32 @ctlz_true_bitreverse(i32 %x) {
define <2 x i64> @ctlz_true_bitreverse_vec(<2 x i64> %x) {
; CHECK-LABEL: @ctlz_true_bitreverse_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 true)
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]]
+; CHECK-NEXT: ret <2 x i64> [[B]]
;
%a = tail call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %x)
%b = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true)
@@ -23,8 +23,8 @@ define <2 x i64> @ctlz_true_bitreverse_vec(<2 x i64> %x) {
define i32 @ctlz_false_bitreverse(i32 %x) {
; CHECK-LABEL: @ctlz_false_bitreverse(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !0
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]]
+; CHECK-NEXT: ret i32 [[B]]
;
%a = tail call i32 @llvm.bitreverse.i32(i32 %x)
%b = tail call i32 @llvm.ctlz.i32(i32 %a, i1 false)
@@ -33,8 +33,8 @@ define i32 @ctlz_false_bitreverse(i32 %x) {
define i32 @cttz_true_bitreverse(i32 %x) {
; CHECK-LABEL: @cttz_true_bitreverse(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range !0
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
+; CHECK-NEXT: ret i32 [[B]]
;
%a = tail call i32 @llvm.bitreverse.i32(i32 %x)
%b = tail call i32 @llvm.cttz.i32(i32 %a, i1 true)
@@ -43,8 +43,8 @@ define i32 @cttz_true_bitreverse(i32 %x) {
define <2 x i64> @cttz_true_bitreverse_vec(<2 x i64> %x) {
; CHECK-LABEL: @cttz_true_bitreverse_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[X:%.*]], i1 true)
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[X:%.*]], i1 true), !range [[RNG1]]
+; CHECK-NEXT: ret <2 x i64> [[B]]
;
%a = tail call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %x)
%b = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
@@ -53,8 +53,8 @@ define <2 x i64> @cttz_true_bitreverse_vec(<2 x i64> %x) {
define i32 @cttz_false_bitreverse(i32 %x) {
; CHECK-LABEL: @cttz_false_bitreverse(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range !0
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]]
+; CHECK-NEXT: ret i32 [[B]]
;
%a = tail call i32 @llvm.bitreverse.i32(i32 %x)
%b = tail call i32 @llvm.cttz.i32(i32 %a, i1 false)
diff --git a/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll b/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll
index 2a308af068fb2..2f523f90edda8 100644
--- a/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll
+++ b/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll
@@ -3,7 +3,7 @@
define i32 @ctpop_bitreverse(i32 %x) {
; CHECK-LABEL: @ctpop_bitreverse(
-; CHECK-NEXT: [[B:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range !0
+; CHECK-NEXT: [[B:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: ret i32 [[B]]
;
%a = tail call i32 @llvm.bitreverse.i32(i32 %x)
@@ -13,7 +13,7 @@ define i32 @ctpop_bitreverse(i32 %x) {
define <2 x i64> @ctpop_bitreverse_vec(<2 x i64> %x) {
; CHECK-LABEL: @ctpop_bitreverse_vec(
-; CHECK-NEXT: [[B:%.*]] = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]])
+; CHECK-NEXT: [[B:%.*]] = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]]), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: ret <2 x i64> [[B]]
;
%a = tail call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %x)
@@ -23,7 +23,7 @@ define <2 x i64> @ctpop_bitreverse_vec(<2 x i64> %x) {
define i32 @ctpop_bswap(i32 %x) {
; CHECK-LABEL: @ctpop_bswap(
-; CHECK-NEXT: [[B:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range !0
+; CHECK-NEXT: [[B:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[B]]
;
%a = tail call i32 @llvm.bswap.i32(i32 %x)
@@ -33,7 +33,7 @@ define i32 @ctpop_bswap(i32 %x) {
define <2 x i64> @ctpop_bswap_vec(<2 x i64> %x) {
; CHECK-LABEL: @ctpop_bswap_vec(
-; CHECK-NEXT: [[B:%.*]] = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]])
+; CHECK-NEXT: [[B:%.*]] = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i64> [[B]]
;
%a = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %x)
diff --git a/llvm/test/Transforms/InstCombine/ctpop-cttz.ll b/llvm/test/Transforms/InstCombine/ctpop-cttz.ll
index ae3f1d49d762b..5d27f374d8921 100644
--- a/llvm/test/Transforms/InstCombine/ctpop-cttz.ll
+++ b/llvm/test/Transforms/InstCombine/ctpop-cttz.ll
@@ -20,7 +20,7 @@ define i32 @ctpop1(i32 %0) {
define <2 x i32> @ctpop1v(<2 x i32> %0) {
; CHECK-LABEL: @ctpop1v(
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false)
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw <2 x i32> <i32 32, i32 32>, [[TMP2]]
; CHECK-NEXT: ret <2 x i32> [[TMP3]]
;
@@ -63,7 +63,7 @@ define i32 @ctpop2(i32 %0) {
define <2 x i32> @ctpop2v(<2 x i32> %0) {
; CHECK-LABEL: @ctpop2v(
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false)
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret <2 x i32> [[TMP2]]
;
%2 = xor <2 x i32> %0, <i32 -1, i32 -1>
@@ -106,7 +106,7 @@ define i32 @ctpop3(i32 %0) {
define <2 x i32> @ctpop3v(<2 x i32> %0) {
; CHECK-LABEL: @ctpop3v(
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false)
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret <2 x i32> [[TMP2]]
;
%2 = sub <2 x i32> zeroinitializer, %0
@@ -118,7 +118,7 @@ define <2 x i32> @ctpop3v(<2 x i32> %0) {
define <2 x i32> @ctpop3v_undef(<2 x i32> %0) {
; CHECK-LABEL: @ctpop3v_undef(
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false)
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret <2 x i32> [[TMP2]]
;
%2 = sub <2 x i32> zeroinitializer, %0
diff --git a/llvm/test/Transforms/InstCombine/ctpop-pow2.ll b/llvm/test/Transforms/InstCombine/ctpop-pow2.ll
index 6ae5d32254120..b73aff5287446 100644
--- a/llvm/test/Transforms/InstCombine/ctpop-pow2.ll
+++ b/llvm/test/Transforms/InstCombine/ctpop-pow2.ll
@@ -104,7 +104,7 @@ define <2 x i32> @ctpop_lshr_intmin_intmin_plus1_vec_nz(<2 x i32> %x) {
; CHECK-LABEL: @ctpop_lshr_intmin_intmin_plus1_vec_nz(
; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i32> <i32 -2147483648, i32 -2147483647>, [[X1]]
-; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHR]])
+; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHR]]), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: ret <2 x i32> [[CNT]]
;
%x1 = or <2 x i32> %x, <i32 1 ,i32 1>
diff --git a/llvm/test/Transforms/InstCombine/cttz-abs.ll b/llvm/test/Transforms/InstCombine/cttz-abs.ll
index 23a9a11e1109d..0141b2cd71cec 100644
--- a/llvm/test/Transforms/InstCombine/cttz-abs.ll
+++ b/llvm/test/Transforms/InstCombine/cttz-abs.ll
@@ -3,7 +3,7 @@
define i32 @cttz_abs(i32 %x) {
; CHECK-LABEL: @cttz_abs(
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), [[RNG0:!range !.*]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 0
@@ -15,7 +15,7 @@ define i32 @cttz_abs(i32 %x) {
define <2 x i64> @cttz_abs_vec(<2 x i64> %x) {
; CHECK-LABEL: @cttz_abs_vec(
-; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: ret <2 x i64> [[R]]
;
%c = icmp slt <2 x i64> %x, zeroinitializer
@@ -29,7 +29,7 @@ define i32 @cttz_abs2(i32 %x) {
; CHECK-LABEL: @cttz_abs2(
; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], 0
; CHECK-NEXT: call void @use_cond(i1 [[C]])
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp sgt i32 %x, 0
@@ -44,7 +44,7 @@ define i32 @cttz_abs3(i32 %x) {
; CHECK-LABEL: @cttz_abs3(
; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: call void @use_cond(i1 [[C]])
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp sgt i32 %x, -1
@@ -57,7 +57,7 @@ define i32 @cttz_abs3(i32 %x) {
define i32 @cttz_abs4(i32 %x) {
; CHECK-LABEL: @cttz_abs4(
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 1
@@ -69,7 +69,7 @@ define i32 @cttz_abs4(i32 %x) {
define i32 @cttz_nabs(i32 %x) {
; CHECK-LABEL: @cttz_nabs(
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 0
@@ -81,7 +81,7 @@ define i32 @cttz_nabs(i32 %x) {
define <2 x i64> @cttz_nabs_vec(<2 x i64> %x) {
; CHECK-LABEL: @cttz_nabs_vec(
-; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i64> [[R]]
;
%c = icmp slt <2 x i64> %x, zeroinitializer
@@ -93,7 +93,7 @@ define <2 x i64> @cttz_nabs_vec(<2 x i64> %x) {
define i64 @cttz_abs_64(i64 %x) {
; CHECK-LABEL: @cttz_abs_64(
-; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), [[RNG1:!range !.*]]
+; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret i64 [[R]]
;
%c = icmp slt i64 %x, 0
@@ -105,9 +105,9 @@ define i64 @cttz_abs_64(i64 %x) {
define i32 @cttz_abs_multiuse(i32 %x) {
; CHECK-LABEL: @cttz_abs_multiuse(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
-; CHECK-NEXT: call void @use_abs(i32 [[TMP1]])
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[D:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT: call void @use_abs(i32 [[D]])
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 1
@@ -123,7 +123,7 @@ define i32 @cttz_nabs_multiuse(i32 %x) {
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
; CHECK-NEXT: [[D:%.*]] = sub i32 0, [[TMP1]]
; CHECK-NEXT: call void @use_abs(i32 [[D]])
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 1
@@ -141,7 +141,7 @@ define i32 @no_cttz_abs(i32 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 2
; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]]
; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]]
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 2
@@ -156,7 +156,7 @@ define i32 @no_cttz_abs2(i32 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 0
; CHECK-NEXT: [[S:%.*]] = sub i32 1, [[X]]
; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]]
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp slt i32 %x, 0
@@ -172,7 +172,7 @@ define i32 @no_cttz_abs3(i32 %x) {
; CHECK-NEXT: call void @use_cond(i1 [[C]])
; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]]
; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[S]]
-; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%c = icmp sgt i32 %x, -2
@@ -188,7 +188,7 @@ define <2 x i64> @no_cttz_abs_vec(<2 x i64> %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[X:%.*]], <i64 2, i64 1>
; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> <i64 1, i64 0>, [[X]]
; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[C]], <2 x i64> [[S]], <2 x i64> [[X]]
-; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false)
+; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i64> [[R]]
;
%c = icmp slt <2 x i64> %x, <i64 2, i64 1>
@@ -203,7 +203,7 @@ define <2 x i64> @no_cttz_nabs_vec(<2 x i64> %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[X:%.*]], <i64 2, i64 1>
; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> <i64 1, i64 0>, [[X]]
; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[C]], <2 x i64> [[X]], <2 x i64> [[S]]
-; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false)
+; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i64> [[R]]
;
%c = icmp slt <2 x i64> %x, <i64 2, i64 1>
@@ -215,7 +215,7 @@ define <2 x i64> @no_cttz_nabs_vec(<2 x i64> %x) {
define i32 @cttz_abs_intrin(i32 %x) {
; CHECK-LABEL: @cttz_abs_intrin(
-; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = call i32 @llvm.abs.i32(i32 %x, i1 false)
@@ -225,7 +225,7 @@ define i32 @cttz_abs_intrin(i32 %x) {
define i32 @cttz_nabs_intrin(i32 %x) {
; CHECK-LABEL: @cttz_nabs_intrin(
-; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), [[RNG0]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[R]]
;
%a = call i32 @llvm.abs.i32(i32 %x, i1 false)
diff --git a/llvm/test/Transforms/InstCombine/cttz-negative.ll b/llvm/test/Transforms/InstCombine/cttz-negative.ll
index 38d264ff7216a..139da840af9e4 100644
--- a/llvm/test/Transforms/InstCombine/cttz-negative.ll
+++ b/llvm/test/Transforms/InstCombine/cttz-negative.ll
@@ -3,7 +3,7 @@
define i32 @cttz_neg_value(i32 %x) {
; CHECK-LABEL: @cttz_neg_value(
-; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range !0
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: ret i32 [[B]]
;
%a = sub i32 0, %x
@@ -15,7 +15,7 @@ define i32 @cttz_neg_value_multiuse(i32 %x) {
; CHECK-LABEL: @cttz_neg_value_multiuse(
; CHECK-NEXT: [[A:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: call void @use(i32 [[A]])
-; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X]], i1 false), !range !0
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[B]]
;
%a = sub i32 0, %x
@@ -26,7 +26,7 @@ define i32 @cttz_neg_value_multiuse(i32 %x) {
define i64 @cttz_neg_value_64(i64 %x) {
; CHECK-LABEL: @cttz_neg_value_64(
-; CHECK-NEXT: [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 true), !range !1
+; CHECK-NEXT: [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: ret i64 [[B]]
;
%a = sub i64 0, %x
@@ -36,7 +36,7 @@ define i64 @cttz_neg_value_64(i64 %x) {
define i64 @cttz_neg_value2_64(i64 %x) {
; CHECK-LABEL: @cttz_neg_value2_64(
-; CHECK-NEXT: [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range !1
+; CHECK-NEXT: [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret i64 [[B]]
;
%a = sub i64 0, %x
@@ -46,7 +46,7 @@ define i64 @cttz_neg_value2_64(i64 %x) {
define <2 x i64> @cttz_neg_value_vec(<2 x i64> %x) {
; CHECK-LABEL: @cttz_neg_value_vec(
-; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i64> [[B]]
;
%a = sub <2 x i64> zeroinitializer, %x
@@ -59,7 +59,7 @@ define <2 x i64> @cttz_neg_value_vec(<2 x i64> %x) {
define i32 @cttz_nonneg_value(i32 %x) {
; CHECK-LABEL: @cttz_nonneg_value(
; CHECK-NEXT: [[A:%.*]] = sub i32 1, [[X:%.*]]
-; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[A]], i1 false), !range !0
+; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[A]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i32 [[B]]
;
%a = sub i32 1, %x
@@ -70,7 +70,7 @@ define i32 @cttz_nonneg_value(i32 %x) {
define <2 x i64> @cttz_nonneg_value_vec(<2 x i64> %x) {
; CHECK-LABEL: @cttz_nonneg_value_vec(
; CHECK-NEXT: [[A:%.*]] = sub <2 x i64> <i64 1, i64 0>, [[X:%.*]]
-; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[A]], i1 false)
+; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[A]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i64> [[B]]
;
%a = sub <2 x i64> <i64 1, i64 0>, %x
diff --git a/llvm/test/Transforms/InstCombine/demorgan.ll b/llvm/test/Transforms/InstCombine/demorgan.ll
index bbc24754e9b70..c9196b6d49aff 100644
--- a/llvm/test/Transforms/InstCombine/demorgan.ll
+++ b/llvm/test/Transforms/InstCombine/demorgan.ll
@@ -459,8 +459,8 @@ define i32 @PR28476(i32 %x, i32 %y) {
; CHECK-LABEL: @PR28476(
; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = or i1 [[CMP0]], [[CMP1]]
-; CHECK-NEXT: [[COND:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: [[AND_NOT:%.*]] = or i1 [[CMP0]], [[CMP1]]
+; CHECK-NEXT: [[COND:%.*]] = zext i1 [[AND_NOT]] to i32
; CHECK-NEXT: ret i32 [[COND]]
;
%cmp0 = icmp ne i32 %x, 0
@@ -475,8 +475,8 @@ define i32 @PR28476_logical(i32 %x, i32 %y) {
; CHECK-LABEL: @PR28476_logical(
; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 0
-; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]]
-; CHECK-NEXT: [[COND:%.*]] = zext i1 [[AND]] to i32
+; CHECK-NEXT: [[AND_NOT:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]]
+; CHECK-NEXT: [[COND:%.*]] = zext i1 [[AND_NOT]] to i32
; CHECK-NEXT: ret i32 [[COND]]
;
%cmp0 = icmp ne i32 %x, 0
diff --git a/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll b/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
index fc0a758d374d5..7390872693c14 100644
--- a/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
+++ b/llvm/test/Transforms/InstCombine/element-atomic-memintrins.ll
@@ -163,8 +163,8 @@ define void @test_memmove_loadstore_2(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memmove_loadstore_2(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 2
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 2
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 2
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 2
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 2
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 2
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 2 [[DEST]], ptr nonnull align 2 [[SRC]], i32 4, i32 2)
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 2 [[DEST]], ptr nonnull align 2 [[SRC]], i32 8, i32 2)
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 2 [[DEST]], ptr nonnull align 2 [[SRC]], i32 16, i32 2)
@@ -182,10 +182,10 @@ define void @test_memmove_loadstore_4(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memmove_loadstore_4(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 4
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 4
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 4
-; CHECK-NEXT: store atomic i32 [[TMP7]], ptr [[DEST]] unordered, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 4
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 4
+; CHECK-NEXT: store atomic i32 [[TMP3]], ptr [[DEST]] unordered, align 4
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 4 [[DEST]], ptr nonnull align 4 [[SRC]], i32 8, i32 4)
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 4 [[DEST]], ptr nonnull align 4 [[SRC]], i32 16, i32 4)
; CHECK-NEXT: ret void
@@ -202,12 +202,12 @@ define void @test_memmove_loadstore_8(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memmove_loadstore_8(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 8
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 8
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 8
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 8
-; CHECK-NEXT: [[TMP7:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 8
-; CHECK-NEXT: store atomic i32 [[TMP7]], ptr [[DEST]] unordered, align 8
-; CHECK-NEXT: [[TMP10:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 8
-; CHECK-NEXT: store atomic i64 [[TMP10]], ptr [[DEST]] unordered, align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 8
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 8
+; CHECK-NEXT: [[TMP3:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 8
+; CHECK-NEXT: store atomic i32 [[TMP3]], ptr [[DEST]] unordered, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 8
+; CHECK-NEXT: store atomic i64 [[TMP4]], ptr [[DEST]] unordered, align 8
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 8 [[DEST]], ptr nonnull align 8 [[SRC]], i32 16, i32 8)
; CHECK-NEXT: ret void
;
@@ -223,12 +223,12 @@ define void @test_memmove_loadstore_16(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memmove_loadstore_16(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 16
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 16
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 16
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 16
-; CHECK-NEXT: [[TMP7:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 16
-; CHECK-NEXT: store atomic i32 [[TMP7]], ptr [[DEST]] unordered, align 16
-; CHECK-NEXT: [[TMP10:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 16
-; CHECK-NEXT: store atomic i64 [[TMP10]], ptr [[DEST]] unordered, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 16
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 16
+; CHECK-NEXT: store atomic i32 [[TMP3]], ptr [[DEST]] unordered, align 16
+; CHECK-NEXT: [[TMP4:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 16
+; CHECK-NEXT: store atomic i64 [[TMP4]], ptr [[DEST]] unordered, align 16
; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i32(ptr nonnull align 16 [[DEST]], ptr nonnull align 16 [[SRC]], i32 16, i32 16)
; CHECK-NEXT: ret void
;
@@ -293,8 +293,8 @@ define void @test_memcpy_loadstore_2(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memcpy_loadstore_2(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 2
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 2
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 2
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 2
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 2
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 2
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 2 [[DEST]], ptr nonnull align 2 [[SRC]], i32 4, i32 2)
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 2 [[DEST]], ptr nonnull align 2 [[SRC]], i32 8, i32 2)
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 2 [[DEST]], ptr nonnull align 2 [[SRC]], i32 16, i32 2)
@@ -312,10 +312,10 @@ define void @test_memcpy_loadstore_4(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memcpy_loadstore_4(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 4
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 4
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 4
-; CHECK-NEXT: store atomic i32 [[TMP7]], ptr [[DEST]] unordered, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 4
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 4
+; CHECK-NEXT: store atomic i32 [[TMP3]], ptr [[DEST]] unordered, align 4
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 4 [[DEST]], ptr nonnull align 4 [[SRC]], i32 8, i32 4)
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 4 [[DEST]], ptr nonnull align 4 [[SRC]], i32 16, i32 4)
; CHECK-NEXT: ret void
@@ -332,12 +332,12 @@ define void @test_memcpy_loadstore_8(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memcpy_loadstore_8(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 8
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 8
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 8
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 8
-; CHECK-NEXT: [[TMP7:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 8
-; CHECK-NEXT: store atomic i32 [[TMP7]], ptr [[DEST]] unordered, align 8
-; CHECK-NEXT: [[TMP10:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 8
-; CHECK-NEXT: store atomic i64 [[TMP10]], ptr [[DEST]] unordered, align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 8
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 8
+; CHECK-NEXT: [[TMP3:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 8
+; CHECK-NEXT: store atomic i32 [[TMP3]], ptr [[DEST]] unordered, align 8
+; CHECK-NEXT: [[TMP4:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 8
+; CHECK-NEXT: store atomic i64 [[TMP4]], ptr [[DEST]] unordered, align 8
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 8 [[DEST]], ptr nonnull align 8 [[SRC]], i32 16, i32 8)
; CHECK-NEXT: ret void
;
@@ -353,12 +353,12 @@ define void @test_memcpy_loadstore_16(ptr %dest, ptr %src) {
; CHECK-LABEL: @test_memcpy_loadstore_16(
; CHECK-NEXT: [[TMP1:%.*]] = load atomic i8, ptr [[SRC:%.*]] unordered, align 16
; CHECK-NEXT: store atomic i8 [[TMP1]], ptr [[DEST:%.*]] unordered, align 16
-; CHECK-NEXT: [[TMP4:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 16
-; CHECK-NEXT: store atomic i16 [[TMP4]], ptr [[DEST]] unordered, align 16
-; CHECK-NEXT: [[TMP7:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 16
-; CHECK-NEXT: store atomic i32 [[TMP7]], ptr [[DEST]] unordered, align 16
-; CHECK-NEXT: [[TMP10:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 16
-; CHECK-NEXT: store atomic i64 [[TMP10]], ptr [[DEST]] unordered, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = load atomic i16, ptr [[SRC]] unordered, align 16
+; CHECK-NEXT: store atomic i16 [[TMP2]], ptr [[DEST]] unordered, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = load atomic i32, ptr [[SRC]] unordered, align 16
+; CHECK-NEXT: store atomic i32 [[TMP3]], ptr [[DEST]] unordered, align 16
+; CHECK-NEXT: [[TMP4:%.*]] = load atomic i64, ptr [[SRC]] unordered, align 16
+; CHECK-NEXT: store atomic i64 [[TMP4]], ptr [[DEST]] unordered, align 16
; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i32(ptr nonnull align 16 [[DEST]], ptr nonnull align 16 [[SRC]], i32 16, i32 16)
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstCombine/eq-of-parts.ll b/llvm/test/Transforms/InstCombine/eq-of-parts.ll
index fd783d15dbb63..dbf671aaaa86b 100644
--- a/llvm/test/Transforms/InstCombine/eq-of-parts.ll
+++ b/llvm/test/Transforms/InstCombine/eq-of-parts.ll
@@ -12,8 +12,8 @@ define i1 @eq_10(i32 %x, i32 %y) {
; CHECK-LABEL: @eq_10(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[Y:%.*]] to i16
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i16 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[C_10:%.*]] = icmp eq i16 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[C_10]]
;
%x.0 = trunc i32 %x to i8
%x.321 = lshr i32 %x, 8
@@ -31,8 +31,8 @@ define i1 @eq_210(i32 %x, i32 %y) {
; CHECK-LABEL: @eq_210(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i24
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[Y:%.*]] to i24
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i24 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i24 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.0 = trunc i32 %x to i8
%x.321 = lshr i32 %x, 8
@@ -54,8 +54,8 @@ define i1 @eq_210(i32 %x, i32 %y) {
define i1 @eq_3210(i32 %x, i32 %y) {
; CHECK-LABEL: @eq_3210(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C_3210:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[C_3210]]
;
%x.0 = trunc i32 %x to i8
%x.321 = lshr i32 %x, 8
@@ -87,8 +87,8 @@ define i1 @eq_21(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -112,8 +112,8 @@ define i1 @eq_21_comm_and(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -135,8 +135,8 @@ define i1 @eq_21_comm_eq(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -158,8 +158,8 @@ define i1 @eq_21_comm_eq2(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -183,8 +183,8 @@ define <2x i1> @eq_21_vector(<2x i32> %x, <2x i32> %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i32> [[Y:%.*]], <i32 8, i32 8>
; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i32> [[TMP3]] to <2 x i16>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <2 x i16> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret <2 x i1> [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq <2 x i16> [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret <2 x i1> [[C_210]]
;
%x.321 = lshr <2x i32> %x, <i32 8, i32 8>
%x.1 = trunc <2x i32> %x.321 to <2x i8>
@@ -209,8 +209,8 @@ define i1 @eq_irregular_bit_widths(i31 %x, i31 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i31 [[TMP1]] to i11
; CHECK-NEXT: [[TMP3:%.*]] = lshr i31 [[Y:%.*]], 7
; CHECK-NEXT: [[TMP4:%.*]] = trunc i31 [[TMP3]] to i11
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i11 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i11 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i31 %x, 7
%x.1 = trunc i31 %x.321 to i6
@@ -360,8 +360,8 @@ define i1 @eq_21_logical(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp eq i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -677,8 +677,8 @@ define i1 @ne_10(i32 %x, i32 %y) {
; CHECK-LABEL: @ne_10(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[Y:%.*]] to i16
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i16 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[C_10:%.*]] = icmp ne i16 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[C_10]]
;
%x.0 = trunc i32 %x to i8
%x.321 = lshr i32 %x, 8
@@ -696,8 +696,8 @@ define i1 @ne_210(i32 %x, i32 %y) {
; CHECK-LABEL: @ne_210(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i24
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[Y:%.*]] to i24
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i24 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i24 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.0 = trunc i32 %x to i8
%x.321 = lshr i32 %x, 8
@@ -719,8 +719,8 @@ define i1 @ne_210(i32 %x, i32 %y) {
define i1 @ne_3210(i32 %x, i32 %y) {
; CHECK-LABEL: @ne_3210(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C_3210:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[C_3210]]
;
%x.0 = trunc i32 %x to i8
%x.321 = lshr i32 %x, 8
@@ -752,8 +752,8 @@ define i1 @ne_21(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -777,8 +777,8 @@ define i1 @ne_21_comm_or(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -800,8 +800,8 @@ define i1 @ne_21_comm_ne(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -823,8 +823,8 @@ define i1 @ne_21_comm_ne2(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
@@ -848,8 +848,8 @@ define <2x i1> @ne_21_vector(<2x i32> %x, <2x i32> %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i32> [[Y:%.*]], <i32 8, i32 8>
; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i32> [[TMP3]] to <2 x i16>
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <2 x i16> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret <2 x i1> [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne <2 x i16> [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret <2 x i1> [[C_210]]
;
%x.321 = lshr <2x i32> %x, <i32 8, i32 8>
%x.1 = trunc <2x i32> %x.321 to <2x i8>
@@ -874,8 +874,8 @@ define i1 @ne_irregular_bit_widths(i31 %x, i31 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i31 [[TMP1]] to i11
; CHECK-NEXT: [[TMP3:%.*]] = lshr i31 [[Y:%.*]], 7
; CHECK-NEXT: [[TMP4:%.*]] = trunc i31 [[TMP3]] to i11
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i11 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i11 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i31 %x, 7
%x.1 = trunc i31 %x.321 to i6
@@ -1025,8 +1025,8 @@ define i1 @ne_21_logical(i32 %x, i32 %y) {
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[Y:%.*]], 8
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[C_210:%.*]] = icmp ne i16 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: ret i1 [[C_210]]
;
%x.321 = lshr i32 %x, 8
%x.1 = trunc i32 %x.321 to i8
diff --git a/llvm/test/Transforms/InstCombine/exact.ll b/llvm/test/Transforms/InstCombine/exact.ll
index a104f0c64e5cb..10d46e7b2dfb3 100644
--- a/llvm/test/Transforms/InstCombine/exact.ll
+++ b/llvm/test/Transforms/InstCombine/exact.ll
@@ -178,8 +178,8 @@ define <2 x i1> @pr9998vec(<2 x i32> %V) {
define i1 @udiv_icmp1(i64 %X) {
; CHECK-LABEL: @udiv_icmp1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[X:%.*]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp ne i64 [[X:%.*]], 0
+; CHECK-NEXT: ret i1 [[B]]
;
%A = udiv exact i64 %X, 5 ; X/5
%B = icmp ne i64 %A, 0
@@ -188,8 +188,8 @@ define i1 @udiv_icmp1(i64 %X) {
define <2 x i1> @udiv_icmp1_vec(<2 x i64> %X) {
; CHECK-LABEL: @udiv_icmp1_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp ne <2 x i64> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = udiv exact <2 x i64> %X, <i64 5, i64 5>
%B = icmp ne <2 x i64> %A, zeroinitializer
@@ -198,8 +198,8 @@ define <2 x i1> @udiv_icmp1_vec(<2 x i64> %X) {
define i1 @udiv_icmp2(i64 %X) {
; CHECK-LABEL: @udiv_icmp2(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 0
+; CHECK-NEXT: ret i1 [[B]]
;
%A = udiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
@@ -208,8 +208,8 @@ define i1 @udiv_icmp2(i64 %X) {
define <2 x i1> @udiv_icmp2_vec(<2 x i64> %X) {
; CHECK-LABEL: @udiv_icmp2_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = udiv exact <2 x i64> %X, <i64 5, i64 5>
%B = icmp eq <2 x i64> %A, zeroinitializer
@@ -218,8 +218,8 @@ define <2 x i1> @udiv_icmp2_vec(<2 x i64> %X) {
define i1 @sdiv_icmp1(i64 %X) {
; CHECK-LABEL: @sdiv_icmp1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 0
+; CHECK-NEXT: ret i1 [[B]]
;
%A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
@@ -228,8 +228,8 @@ define i1 @sdiv_icmp1(i64 %X) {
define <2 x i1> @sdiv_icmp1_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp1_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
%B = icmp eq <2 x i64> %A, zeroinitializer
@@ -238,8 +238,8 @@ define <2 x i1> @sdiv_icmp1_vec(<2 x i64> %X) {
define i1 @sdiv_icmp2(i64 %X) {
; CHECK-LABEL: @sdiv_icmp2(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 5
+; CHECK-NEXT: ret i1 [[B]]
;
%A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5
%B = icmp eq i64 %A, 1
@@ -248,8 +248,8 @@ define i1 @sdiv_icmp2(i64 %X) {
define <2 x i1> @sdiv_icmp2_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp2_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 5, i64 5>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 5, i64 5>
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
%B = icmp eq <2 x i64> %A, <i64 1, i64 1>
@@ -258,8 +258,8 @@ define <2 x i1> @sdiv_icmp2_vec(<2 x i64> %X) {
define i1 @sdiv_icmp3(i64 %X) {
; CHECK-LABEL: @sdiv_icmp3(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], -5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], -5
+; CHECK-NEXT: ret i1 [[B]]
;
%A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5
%B = icmp eq i64 %A, -1
@@ -268,8 +268,8 @@ define i1 @sdiv_icmp3(i64 %X) {
define <2 x i1> @sdiv_icmp3_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp3_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 -5, i64 -5>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 -5, i64 -5>
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
%B = icmp eq <2 x i64> %A, <i64 -1, i64 -1>
@@ -278,8 +278,8 @@ define <2 x i1> @sdiv_icmp3_vec(<2 x i64> %X) {
define i1 @sdiv_icmp4(i64 %X) {
; CHECK-LABEL: @sdiv_icmp4(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 0
+; CHECK-NEXT: ret i1 [[B]]
;
%A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0
%B = icmp eq i64 %A, 0
@@ -288,8 +288,8 @@ define i1 @sdiv_icmp4(i64 %X) {
define <2 x i1> @sdiv_icmp4_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp4_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
%B = icmp eq <2 x i64> %A, zeroinitializer
@@ -298,8 +298,8 @@ define <2 x i1> @sdiv_icmp4_vec(<2 x i64> %X) {
define i1 @sdiv_icmp5(i64 %X) {
; CHECK-LABEL: @sdiv_icmp5(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], -5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], -5
+; CHECK-NEXT: ret i1 [[B]]
;
%A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5
%B = icmp eq i64 %A, 1
@@ -308,8 +308,8 @@ define i1 @sdiv_icmp5(i64 %X) {
define <2 x i1> @sdiv_icmp5_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp5_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 -5, i64 -5>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 -5, i64 -5>
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
%B = icmp eq <2 x i64> %A, <i64 1, i64 1>
@@ -318,8 +318,8 @@ define <2 x i1> @sdiv_icmp5_vec(<2 x i64> %X) {
define i1 @sdiv_icmp6(i64 %X) {
; CHECK-LABEL: @sdiv_icmp6(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 5
+; CHECK-NEXT: ret i1 [[B]]
;
%A = sdiv exact i64 %X, -5 ; X/-5 == -1 --> x == 5
%B = icmp eq i64 %A, -1
@@ -328,8 +328,8 @@ define i1 @sdiv_icmp6(i64 %X) {
define <2 x i1> @sdiv_icmp6_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp6_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 5, i64 5>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 5, i64 5>
+; CHECK-NEXT: ret <2 x i1> [[B]]
;
%A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
%B = icmp eq <2 x i64> %A, <i64 -1, i64 -1>
diff --git a/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
index 244750c923eb6..3f379b405ad83 100644
--- a/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
@@ -127,8 +127,8 @@ define i3 @bitcasted_inselt_wide_source_not_modulo_elt_not_half_weird_types(i15
define i8 @bitcasted_inselt_wide_source_wrong_insert(<2 x i32> %v, i32 %x) {
; ANY-LABEL: @bitcasted_inselt_wide_source_wrong_insert(
-; ANY-NEXT: [[B:%.*]] = bitcast <2 x i32> [[V:%.*]] to <8 x i8>
-; ANY-NEXT: [[R:%.*]] = extractelement <8 x i8> [[B]], i64 2
+; ANY-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[V:%.*]] to <8 x i8>
+; ANY-NEXT: [[R:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; ANY-NEXT: ret i8 [[R]]
;
%i = insertelement <2 x i32> %v, i32 %x, i32 1
diff --git a/llvm/test/Transforms/InstCombine/fabs-copysign.ll b/llvm/test/Transforms/InstCombine/fabs-copysign.ll
index b224f2299e0dd..438760b76f203 100644
--- a/llvm/test/Transforms/InstCombine/fabs-copysign.ll
+++ b/llvm/test/Transforms/InstCombine/fabs-copysign.ll
@@ -11,8 +11,8 @@ declare float @llvm.copysign.f32(float, float)
define double @fabs_copysign(double %x) {
; CHECK-LABEL: @fabs_copysign(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[DIV:%.*]] = call nnan ninf double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
+; CHECK-NEXT: ret double [[DIV]]
;
%f = tail call double @llvm.fabs.f64(double %x)
%div = fdiv nnan ninf double %x, %f
@@ -21,8 +21,8 @@ define double @fabs_copysign(double %x) {
define double @fabs_copysign_commuted(double %x) {
; CHECK-LABEL: @fabs_copysign_commuted(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[DIV:%.*]] = call nnan ninf double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
+; CHECK-NEXT: ret double [[DIV]]
;
%f = tail call double @llvm.fabs.f64(double %x)
%div = fdiv nnan ninf double %f, %x
@@ -31,8 +31,8 @@ define double @fabs_copysign_commuted(double %x) {
define <4 x double> @fabs_copysign_vec(<4 x double> %x) {
; CHECK-LABEL: @fabs_copysign_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf <4 x double> @llvm.copysign.v4f64(<4 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, <4 x double> [[X:%.*]])
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[DIV:%.*]] = call nnan ninf <4 x double> @llvm.copysign.v4f64(<4 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, <4 x double> [[X:%.*]])
+; CHECK-NEXT: ret <4 x double> [[DIV]]
;
%f = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
%div = fdiv nnan ninf <4 x double> %x, %f
@@ -41,8 +41,8 @@ define <4 x double> @fabs_copysign_vec(<4 x double> %x) {
define <4 x double> @fabs_copysign_vec_commuted(<4 x double> %x) {
; CHECK-LABEL: @fabs_copysign_vec_commuted(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf <4 x double> @llvm.copysign.v4f64(<4 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, <4 x double> [[X:%.*]])
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[DIV:%.*]] = call nnan ninf <4 x double> @llvm.copysign.v4f64(<4 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, <4 x double> [[X:%.*]])
+; CHECK-NEXT: ret <4 x double> [[DIV]]
;
%f = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
%div = fdiv nnan ninf <4 x double> %f, %x
@@ -51,8 +51,8 @@ define <4 x double> @fabs_copysign_vec_commuted(<4 x double> %x) {
define float @fabs_copysignf(float %x) {
; CHECK-LABEL: @fabs_copysignf(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.copysign.f32(float 1.000000e+00, float [[X:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[DIV:%.*]] = call nnan ninf float @llvm.copysign.f32(float 1.000000e+00, float [[X:%.*]])
+; CHECK-NEXT: ret float [[DIV]]
;
%f = tail call float @llvm.fabs.f32(float %x)
%div = fdiv nnan ninf float %x, %f
@@ -63,8 +63,8 @@ define double @fabs_copysign_use(double %x) {
; CHECK-LABEL: @fabs_copysign_use(
; CHECK-NEXT: [[F:%.*]] = tail call double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: call void @use(double [[F]])
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf double @llvm.copysign.f64(double 1.000000e+00, double [[X]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[DIV:%.*]] = call nnan ninf double @llvm.copysign.f64(double 1.000000e+00, double [[X]])
+; CHECK-NEXT: ret double [[DIV]]
;
%f = tail call double @llvm.fabs.f64(double %x)
call void @use(double %f)
diff --git a/llvm/test/Transforms/InstCombine/fadd.ll b/llvm/test/Transforms/InstCombine/fadd.ll
index 32ecd8cf196b5..f1e2d8cedfa18 100644
--- a/llvm/test/Transforms/InstCombine/fadd.ll
+++ b/llvm/test/Transforms/InstCombine/fadd.ll
@@ -391,8 +391,8 @@ define float @fmul_fneg2_extra_use3(float %x, float %py, float %z) {
define float @fadd_rdx(float %x, <4 x float> %v) {
; CHECK-LABEL: @fadd_rdx(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[X:%.*]], <4 x float> [[V:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[ADD:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[X:%.*]], <4 x float> [[V:%.*]])
+; CHECK-NEXT: ret float [[ADD]]
;
%rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.0, <4 x float> %v)
%add = fadd fast float %rdx, %x
@@ -402,8 +402,8 @@ define float @fadd_rdx(float %x, <4 x float> %v) {
define float @fadd_rdx_commute(float %x, <4 x float> %v) {
; CHECK-LABEL: @fadd_rdx_commute(
; CHECK-NEXT: [[D:%.*]] = fdiv float 4.200000e+01, [[X:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float [[D]], <4 x float> [[V:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[ADD:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float [[D]], <4 x float> [[V:%.*]])
+; CHECK-NEXT: ret float [[ADD]]
;
%d = fdiv float 42.0, %x
%rdx = call float @llvm.vector.reduce.fadd.v4f32(float -0.0, <4 x float> %v)
@@ -441,8 +441,8 @@ define float @fadd_rdx_extra_use(float %x, <4 x float> %v) {
define float @fadd_rdx_nonzero_start_const_op(<4 x float> %v) {
; CHECK-LABEL: @fadd_rdx_nonzero_start_const_op(
-; CHECK-NEXT: [[TMP1:%.*]] = call reassoc ninf nsz float @llvm.vector.reduce.fadd.v4f32(float 3.300000e+01, <4 x float> [[V:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[ADD:%.*]] = call reassoc ninf nsz float @llvm.vector.reduce.fadd.v4f32(float 3.300000e+01, <4 x float> [[V:%.*]])
+; CHECK-NEXT: ret float [[ADD]]
;
%rdx = call float @llvm.vector.reduce.fadd.v4f32(float 42.0, <4 x float> %v)
%add = fadd reassoc nsz ninf float %rdx, -9.0
diff --git a/llvm/test/Transforms/InstCombine/fast-basictest.ll b/llvm/test/Transforms/InstCombine/fast-basictest.ll
index 1f1c4d3b0c9d1..3c7776a43e55e 100644
--- a/llvm/test/Transforms/InstCombine/fast-basictest.ll
+++ b/llvm/test/Transforms/InstCombine/fast-basictest.ll
@@ -12,8 +12,8 @@
define float @test1(float %arg) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[TMP1:%.*]] = fneg fast float [[ARG:%.*]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T2:%.*]] = fneg fast float [[ARG:%.*]]
+; CHECK-NEXT: ret float [[T2]]
;
%t1 = fsub fast float -1.200000e+01, %arg
%t2 = fadd fast float %t1, 1.200000e+01
@@ -24,8 +24,8 @@ define float @test1(float %arg) {
; Both 'reassoc' and 'nsz' are required.
define float @test1_minimal(float %arg) {
; CHECK-LABEL: @test1_minimal(
-; CHECK-NEXT: [[TMP1:%.*]] = fneg reassoc nsz float [[ARG:%.*]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T2:%.*]] = fneg reassoc nsz float [[ARG:%.*]]
+; CHECK-NEXT: ret float [[T2]]
;
%t1 = fsub reassoc nsz float -1.200000e+01, %arg
%t2 = fadd reassoc nsz float %t1, 1.200000e+01
@@ -141,8 +141,8 @@ define float @test7_reassoc(float %X, float %Y, float %Z) {
define float @test8(float %X) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], 9.400000e+01
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = fmul fast float [[X:%.*]], 9.400000e+01
+; CHECK-NEXT: ret float [[Z]]
;
%Y = fmul fast float %X, 4.700000e+01
%Z = fadd fast float %Y, %Y
@@ -152,8 +152,8 @@ define float @test8(float %X) {
; Check again with 'reassoc' and 'nsz' ('nsz' not technically required).
define float @test8_reassoc_nsz(float %X) {
; CHECK-LABEL: @test8_reassoc_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz float [[X:%.*]], 9.400000e+01
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = fmul reassoc nsz float [[X:%.*]], 9.400000e+01
+; CHECK-NEXT: ret float [[Z]]
;
%Y = fmul reassoc nsz float %X, 4.700000e+01
%Z = fadd reassoc nsz float %Y, %Y
@@ -178,8 +178,8 @@ define float @test8_reassoc(float %X) {
define float @test9(float %X) {
; CHECK-LABEL: @test9(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], 4.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[W:%.*]] = fmul fast float [[X:%.*]], 4.000000e+00
+; CHECK-NEXT: ret float [[W]]
;
%Y = fadd fast float %X ,%X
%Z = fadd fast float %Y, %X
@@ -190,8 +190,8 @@ define float @test9(float %X) {
; Check again with 'reassoc' and 'nsz' ('nsz' not technically required).
define float @test9_reassoc_nsz(float %X) {
; CHECK-LABEL: @test9_reassoc_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz float [[X:%.*]], 4.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[W:%.*]] = fmul reassoc nsz float [[X:%.*]], 4.000000e+00
+; CHECK-NEXT: ret float [[W]]
;
%Y = fadd reassoc nsz float %X ,%X
%Z = fadd reassoc nsz float %Y, %X
@@ -254,8 +254,8 @@ define float @test10_reassoc(float %W) {
define float @test11(float %X) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[X:%.*]], 3.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = fsub fast float 6.000000e+00, [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[Z:%.*]] = fsub fast float 6.000000e+00, [[TMP1]]
+; CHECK-NEXT: ret float [[Z]]
;
%A = fsub fast float 1.000000e+00, %X
%B = fsub fast float 2.000000e+00, %X
@@ -269,8 +269,8 @@ define float @test11(float %X) {
define float @test11_reassoc_nsz(float %X) {
; CHECK-LABEL: @test11_reassoc_nsz(
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz float [[X:%.*]], 3.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = fsub reassoc nsz float 6.000000e+00, [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[Z:%.*]] = fsub reassoc nsz float 6.000000e+00, [[TMP1]]
+; CHECK-NEXT: ret float [[Z]]
;
%A = fsub reassoc nsz float 1.000000e+00, %X
%B = fsub reassoc nsz float 2.000000e+00, %X
diff --git a/llvm/test/Transforms/InstCombine/fast-math.ll b/llvm/test/Transforms/InstCombine/fast-math.ll
index e67696fbf227e..129d7811cfb86 100644
--- a/llvm/test/Transforms/InstCombine/fast-math.ll
+++ b/llvm/test/Transforms/InstCombine/fast-math.ll
@@ -42,8 +42,8 @@ define float @fold2(float %a) {
; That is, (x + x + x) and (3*x) each have only a single rounding.
define double @fold3(double %f1) {
; CHECK-LABEL: @fold3(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[F1:%.*]], 6.000000e+00
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[T2:%.*]] = fmul fast double [[F1:%.*]], 6.000000e+00
+; CHECK-NEXT: ret double [[T2]]
;
%t1 = fmul fast double 5.000000e+00, %f1
%t2 = fadd fast double %f1, %t1
@@ -53,8 +53,8 @@ define double @fold3(double %f1) {
; Check again with 'reassoc' and 'nsz' ('nsz' not technically required).
define double @fold3_reassoc_nsz(double %f1) {
; CHECK-LABEL: @fold3_reassoc_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz double [[F1:%.*]], 6.000000e+00
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[T2:%.*]] = fmul reassoc nsz double [[F1:%.*]], 6.000000e+00
+; CHECK-NEXT: ret double [[T2]]
;
%t1 = fmul reassoc nsz double 5.000000e+00, %f1
%t2 = fadd reassoc nsz double %f1, %t1
@@ -77,8 +77,8 @@ define double @fold3_reassoc(double %f1) {
define float @fold4(float %f1, float %f2) {
; CHECK-LABEL: @fold4(
; CHECK-NEXT: [[TMP1:%.*]] = fadd fast float [[F1:%.*]], [[F2:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = fsub fast float 9.000000e+00, [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub fast float 9.000000e+00, [[TMP1]]
+; CHECK-NEXT: ret float [[ADD]]
;
%sub = fsub float 4.000000e+00, %f1
%sub1 = fsub float 5.000000e+00, %f2
@@ -90,8 +90,8 @@ define float @fold4(float %f1, float %f2) {
define float @fold4_reassoc_nsz(float %f1, float %f2) {
; CHECK-LABEL: @fold4_reassoc_nsz(
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc nsz float [[F1:%.*]], [[F2:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = fsub reassoc nsz float 9.000000e+00, [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[ADD:%.*]] = fsub reassoc nsz float 9.000000e+00, [[TMP1]]
+; CHECK-NEXT: ret float [[ADD]]
;
%sub = fsub float 4.000000e+00, %f1
%sub1 = fsub float 5.000000e+00, %f2
@@ -150,8 +150,8 @@ define float @fold5_reassoc(float %f1) {
; (X + X) + X + X => 4.0 * X
define float @fold6(float %f1) {
; CHECK-LABEL: @fold6(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[F1:%.*]], 4.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fmul fast float [[F1:%.*]], 4.000000e+00
+; CHECK-NEXT: ret float [[T3]]
;
%t1 = fadd fast float %f1, %f1
%t2 = fadd fast float %f1, %t1
@@ -162,8 +162,8 @@ define float @fold6(float %f1) {
; Check again with 'reassoc' and 'nsz' ('nsz' not technically required).
define float @fold6_reassoc_nsz(float %f1) {
; CHECK-LABEL: @fold6_reassoc_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz float [[F1:%.*]], 4.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fmul reassoc nsz float [[F1:%.*]], 4.000000e+00
+; CHECK-NEXT: ret float [[T3]]
;
%t1 = fadd reassoc nsz float %f1, %f1
%t2 = fadd reassoc nsz float %f1, %t1
@@ -188,8 +188,8 @@ define float @fold6_reassoc(float %f1) {
; C1 * X + (X + X) = (C1 + 2) * X
define float @fold7(float %f1) {
; CHECK-LABEL: @fold7(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[F1:%.*]], 7.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fmul fast float [[F1:%.*]], 7.000000e+00
+; CHECK-NEXT: ret float [[T3]]
;
%t1 = fmul fast float %f1, 5.000000e+00
%t2 = fadd fast float %f1, %f1
@@ -200,8 +200,8 @@ define float @fold7(float %f1) {
; Check again with 'reassoc' and 'nsz' ('nsz' not technically required).
define float @fold7_reassoc_nsz(float %f1) {
; CHECK-LABEL: @fold7_reassoc_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz float [[F1:%.*]], 7.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fmul reassoc nsz float [[F1:%.*]], 7.000000e+00
+; CHECK-NEXT: ret float [[T3]]
;
%t1 = fmul reassoc nsz float %f1, 5.000000e+00
%t2 = fadd reassoc nsz float %f1, %f1
@@ -226,8 +226,8 @@ define float @fold7_reassoc(float %f1) {
; (X + X) + (X + X) + X => 5.0 * X
define float @fold8(float %f1) {
; CHECK-LABEL: @fold8(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[F1:%.*]], 5.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T4:%.*]] = fmul fast float [[F1:%.*]], 5.000000e+00
+; CHECK-NEXT: ret float [[T4]]
;
%t1 = fadd fast float %f1, %f1
%t2 = fadd fast float %f1, %f1
@@ -239,8 +239,8 @@ define float @fold8(float %f1) {
; Check again with 'reassoc' and 'nsz' ('nsz' not technically required).
define float @fold8_reassoc_nsz(float %f1) {
; CHECK-LABEL: @fold8_reassoc_nsz(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz float [[F1:%.*]], 5.000000e+00
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[T4:%.*]] = fmul reassoc nsz float [[F1:%.*]], 5.000000e+00
+; CHECK-NEXT: ret float [[T4]]
;
%t1 = fadd reassoc nsz float %f1, %f1
%t2 = fadd reassoc nsz float %f1, %f1
@@ -417,8 +417,8 @@ define float @fold10_reassoc(float %f1, float %f2) {
define float @fail1(float %f1, float %f2) {
; CHECK-LABEL: @fail1(
; CHECK-NEXT: [[TMP1:%.*]] = fmul fast float [[F1:%.*]], 3.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = fadd fast float [[TMP1]], -3.000000e+00
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[ADD2:%.*]] = fadd fast float [[TMP1]], -3.000000e+00
+; CHECK-NEXT: ret float [[ADD2]]
;
%conv3 = fadd fast float %f1, -1.000000e+00
%add = fadd fast float %conv3, %conv3
@@ -429,8 +429,8 @@ define float @fail1(float %f1, float %f2) {
define double @fail2(double %f1, double %f2) {
; CHECK-LABEL: @fail2(
; CHECK-NEXT: [[TMP1:%.*]] = fadd fast double [[F2:%.*]], [[F2]]
-; CHECK-NEXT: [[TMP2:%.*]] = fneg fast double [[TMP1]]
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fneg fast double [[TMP1]]
+; CHECK-NEXT: ret double [[T3]]
;
%t1 = fsub fast double %f1, %f2
%t2 = fadd fast double %f1, %f2
@@ -648,8 +648,8 @@ define double @sqrt_intrinsic_three_args1(double %x, double %y) {
; CHECK-LABEL: @sqrt_intrinsic_three_args1(
; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[Y:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %y, %x
%mul2 = fmul fast double %mul, %x
@@ -661,8 +661,8 @@ define double @sqrt_intrinsic_three_args2(double %x, double %y) {
; CHECK-LABEL: @sqrt_intrinsic_three_args2(
; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[Y:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %x, %y
%mul2 = fmul fast double %mul, %x
@@ -674,8 +674,8 @@ define double @sqrt_intrinsic_three_args3(double %x, double %y) {
; CHECK-LABEL: @sqrt_intrinsic_three_args3(
; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[Y:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %x, %x
%mul2 = fmul fast double %mul, %y
@@ -687,8 +687,8 @@ define double @sqrt_intrinsic_three_args4(double %x, double %y) {
; CHECK-LABEL: @sqrt_intrinsic_three_args4(
; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[Y:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %y, %x
%mul2 = fmul fast double %x, %mul
@@ -700,8 +700,8 @@ define double @sqrt_intrinsic_three_args5(double %x, double %y) {
; CHECK-LABEL: @sqrt_intrinsic_three_args5(
; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[Y:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %x, %y
%mul2 = fmul fast double %x, %mul
@@ -713,8 +713,8 @@ define double @sqrt_intrinsic_three_args6(double %x, double %y) {
; CHECK-LABEL: @sqrt_intrinsic_three_args6(
; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[Y:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %x, %x
%mul2 = fmul fast double %y, %mul
@@ -752,8 +752,8 @@ define double @sqrt_intrinsic_arg_5th(double %x) {
; CHECK-LABEL: @sqrt_intrinsic_arg_5th(
; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[X]]
; CHECK-NEXT: [[SQRT1:%.*]] = call fast double @llvm.sqrt.f64(double [[X]])
-; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[MUL]], [[SQRT1]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[SQRT:%.*]] = fmul fast double [[MUL]], [[SQRT1]]
+; CHECK-NEXT: ret double [[SQRT]]
;
%mul = fmul fast double %x, %x
%mul2 = fmul fast double %mul, %x
@@ -816,8 +816,8 @@ declare fp128 @fminl(fp128, fp128)
; Shrink and replace the call.
define float @max1(float %a, float %b) {
; CHECK-LABEL: @max1(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[FMAXF:%.*]] = call fast float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[FMAXF]]
;
%c = fpext float %a to double
%d = fpext float %b to double
@@ -828,8 +828,8 @@ define float @max1(float %a, float %b) {
define float @fmax_no_fmf(float %a, float %b) {
; CHECK-LABEL: @fmax_no_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call nsz float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[C]]
;
%c = call float @fmaxf(float %a, float %b)
ret float %c
@@ -837,8 +837,8 @@ define float @fmax_no_fmf(float %a, float %b) {
define float @max2(float %a, float %b) {
; CHECK-LABEL: @max2(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call nnan nsz float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[C]]
;
%c = call nnan float @fmaxf(float %a, float %b)
ret float %c
@@ -847,8 +847,8 @@ define float @max2(float %a, float %b) {
define double @max3(double %a, double %b) {
; CHECK-LABEL: @max3(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast double @llvm.maxnum.f64(double [[A:%.*]], double [[B:%.*]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call fast double @llvm.maxnum.f64(double [[A:%.*]], double [[B:%.*]])
+; CHECK-NEXT: ret double [[C]]
;
%c = call fast double @fmax(double %a, double %b)
ret double %c
@@ -856,8 +856,8 @@ define double @max3(double %a, double %b) {
define fp128 @max4(fp128 %a, fp128 %b) {
; CHECK-LABEL: @max4(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz fp128 @llvm.maxnum.f128(fp128 [[A:%.*]], fp128 [[B:%.*]])
-; CHECK-NEXT: ret fp128 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call nnan nsz fp128 @llvm.maxnum.f128(fp128 [[A:%.*]], fp128 [[B:%.*]])
+; CHECK-NEXT: ret fp128 [[C]]
;
%c = call nnan fp128 @fmaxl(fp128 %a, fp128 %b)
ret fp128 %c
@@ -866,8 +866,8 @@ define fp128 @max4(fp128 %a, fp128 %b) {
; Shrink and remove the call.
define float @min1(float %a, float %b) {
; CHECK-LABEL: @min1(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[FMINF:%.*]] = call nnan nsz float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[FMINF]]
;
%c = fpext float %a to double
%d = fpext float %b to double
@@ -878,8 +878,8 @@ define float @min1(float %a, float %b) {
define float @fmin_no_fmf(float %a, float %b) {
; CHECK-LABEL: @fmin_no_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call nsz float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[C]]
;
%c = call float @fminf(float %a, float %b)
ret float %c
@@ -887,8 +887,8 @@ define float @fmin_no_fmf(float %a, float %b) {
define float @min2(float %a, float %b) {
; CHECK-LABEL: @min2(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call fast float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[C]]
;
%c = call fast float @fminf(float %a, float %b)
ret float %c
@@ -896,8 +896,8 @@ define float @min2(float %a, float %b) {
define double @min3(double %a, double %b) {
; CHECK-LABEL: @min3(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz double @llvm.minnum.f64(double [[A:%.*]], double [[B:%.*]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call nnan nsz double @llvm.minnum.f64(double [[A:%.*]], double [[B:%.*]])
+; CHECK-NEXT: ret double [[C]]
;
%c = call nnan double @fmin(double %a, double %b)
ret double %c
@@ -905,8 +905,8 @@ define double @min3(double %a, double %b) {
define fp128 @min4(fp128 %a, fp128 %b) {
; CHECK-LABEL: @min4(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast fp128 @llvm.minnum.f128(fp128 [[A:%.*]], fp128 [[B:%.*]])
-; CHECK-NEXT: ret fp128 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = call fast fp128 @llvm.minnum.f128(fp128 [[A:%.*]], fp128 [[B:%.*]])
+; CHECK-NEXT: ret fp128 [[C]]
;
%c = call fast fp128 @fminl(fp128 %a, fp128 %b)
ret fp128 %c
@@ -919,10 +919,10 @@ define float @test55(i1 %which, float %a) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
-; CHECK-NEXT: [[PHITMP:%.*]] = fadd float [[A:%.*]], 1.000000e+00
+; CHECK-NEXT: [[TMP0:%.*]] = fadd float [[A:%.*]], 1.000000e+00
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi float [ 3.000000e+00, [[ENTRY:%.*]] ], [ [[PHITMP]], [[DELAY]] ]
+; CHECK-NEXT: [[A:%.*]] = phi float [ 3.000000e+00, [[ENTRY:%.*]] ], [ [[TMP0]], [[DELAY]] ]
; CHECK-NEXT: ret float [[A]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll b/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
index b93cd1c988038..6d945ede3b387 100644
--- a/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
+++ b/llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
@@ -29,9 +29,9 @@ define double @fdiv_strict_cos_strict_sin_reassoc(double %a) {
define double @fdiv_reassoc_cos_strict_sin_strict(double %a, ptr dereferenceable(2) %dummy) {
; CHECK-LABEL: @fdiv_reassoc_cos_strict_sin_strict(
-; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #1
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double 1.000000e+00, [[TAN]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc double 1.000000e+00, [[TAN]]
+; CHECK-NEXT: ret double [[DIV]]
;
%1 = call double @llvm.cos.f64(double %a)
%2 = call double @llvm.sin.f64(double %a)
@@ -41,9 +41,9 @@ define double @fdiv_reassoc_cos_strict_sin_strict(double %a, ptr dereferenceable
define double @fdiv_reassoc_cos_reassoc_sin_strict(double %a) {
; CHECK-LABEL: @fdiv_reassoc_cos_reassoc_sin_strict(
-; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #1
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double 1.000000e+00, [[TAN]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #[[ATTR1]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc double 1.000000e+00, [[TAN]]
+; CHECK-NEXT: ret double [[DIV]]
;
%1 = call reassoc double @llvm.cos.f64(double %a)
%2 = call double @llvm.sin.f64(double %a)
@@ -68,9 +68,9 @@ define double @fdiv_cos_sin_reassoc_multiple_uses(double %a) {
define double @fdiv_cos_sin_reassoc(double %a) {
; CHECK-LABEL: @fdiv_cos_sin_reassoc(
-; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #1
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc double 1.000000e+00, [[TAN]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #[[ATTR1]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc double 1.000000e+00, [[TAN]]
+; CHECK-NEXT: ret double [[DIV]]
;
%1 = call reassoc double @llvm.cos.f64(double %a)
%2 = call reassoc double @llvm.sin.f64(double %a)
@@ -93,9 +93,9 @@ define half @fdiv_cosf16_sinf16_reassoc(half %a) {
define float @fdiv_cosf_sinf_reassoc(float %a) {
; CHECK-LABEL: @fdiv_cosf_sinf_reassoc(
-; CHECK-NEXT: [[TANF:%.*]] = call reassoc float @tanf(float [[A:%.*]]) #1
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc float 1.000000e+00, [[TANF]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[TANF:%.*]] = call reassoc float @tanf(float [[A:%.*]]) #[[ATTR1]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc float 1.000000e+00, [[TANF]]
+; CHECK-NEXT: ret float [[DIV]]
;
%1 = call reassoc float @llvm.cos.f32(float %a)
%2 = call reassoc float @llvm.sin.f32(float %a)
@@ -105,9 +105,9 @@ define float @fdiv_cosf_sinf_reassoc(float %a) {
define fp128 @fdiv_cosfp128_sinfp128_reassoc(fp128 %a) {
; CHECK-LABEL: @fdiv_cosfp128_sinfp128_reassoc(
-; CHECK-NEXT: [[TANL:%.*]] = call reassoc fp128 @tanl(fp128 [[A:%.*]]) #1
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc fp128 0xL00000000000000003FFF000000000000, [[TANL]]
-; CHECK-NEXT: ret fp128 [[TMP1]]
+; CHECK-NEXT: [[TANL:%.*]] = call reassoc fp128 @tanl(fp128 [[A:%.*]]) #[[ATTR1]]
+; CHECK-NEXT: [[DIV:%.*]] = fdiv reassoc fp128 0xL00000000000000003FFF000000000000, [[TANL]]
+; CHECK-NEXT: ret fp128 [[DIV]]
;
%1 = call reassoc fp128 @llvm.cos.fp128(fp128 %a)
%2 = call reassoc fp128 @llvm.sin.fp128(fp128 %a)
diff --git a/llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll b/llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
index 90f80c8a0d669..a9b8af345f96d 100644
--- a/llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
+++ b/llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
@@ -29,7 +29,7 @@ define double @fdiv_strict_sin_strict_cos_reassoc(double %a) {
define double @fdiv_reassoc_sin_strict_cos_strict(double %a, ptr dereferenceable(2) %dummy) {
; CHECK-LABEL: @fdiv_reassoc_sin_strict_cos_strict(
-; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #1
+; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret double [[TAN]]
;
%1 = call double @llvm.sin.f64(double %a)
@@ -40,7 +40,7 @@ define double @fdiv_reassoc_sin_strict_cos_strict(double %a, ptr dereferenceable
define double @fdiv_reassoc_sin_reassoc_cos_strict(double %a) {
; CHECK-LABEL: @fdiv_reassoc_sin_reassoc_cos_strict(
-; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #1
+; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #[[ATTR1]]
; CHECK-NEXT: ret double [[TAN]]
;
%1 = call reassoc double @llvm.sin.f64(double %a)
@@ -66,7 +66,7 @@ define double @fdiv_sin_cos_reassoc_multiple_uses(double %a) {
define double @fdiv_sin_cos_reassoc(double %a) {
; CHECK-LABEL: @fdiv_sin_cos_reassoc(
-; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #1
+; CHECK-NEXT: [[TAN:%.*]] = call reassoc double @tan(double [[A:%.*]]) #[[ATTR1]]
; CHECK-NEXT: ret double [[TAN]]
;
%1 = call reassoc double @llvm.sin.f64(double %a)
@@ -77,7 +77,7 @@ define double @fdiv_sin_cos_reassoc(double %a) {
define float @fdiv_sinf_cosf_reassoc(float %a) {
; CHECK-LABEL: @fdiv_sinf_cosf_reassoc(
-; CHECK-NEXT: [[TANF:%.*]] = call reassoc float @tanf(float [[A:%.*]]) #1
+; CHECK-NEXT: [[TANF:%.*]] = call reassoc float @tanf(float [[A:%.*]]) #[[ATTR1]]
; CHECK-NEXT: ret float [[TANF]]
;
%1 = call reassoc float @llvm.sin.f32(float %a)
@@ -88,7 +88,7 @@ define float @fdiv_sinf_cosf_reassoc(float %a) {
define fp128 @fdiv_sinfp128_cosfp128_reassoc(fp128 %a) {
; CHECK-LABEL: @fdiv_sinfp128_cosfp128_reassoc(
-; CHECK-NEXT: [[TANL:%.*]] = call reassoc fp128 @tanl(fp128 [[A:%.*]]) #1
+; CHECK-NEXT: [[TANL:%.*]] = call reassoc fp128 @tanl(fp128 [[A:%.*]]) #[[ATTR1]]
; CHECK-NEXT: ret fp128 [[TANL]]
;
%1 = call reassoc fp128 @llvm.sin.fp128(fp128 %a)
diff --git a/llvm/test/Transforms/InstCombine/ffs-i16.ll b/llvm/test/Transforms/InstCombine/ffs-i16.ll
index 0984724511ef5..f86ae34e340fb 100644
--- a/llvm/test/Transforms/InstCombine/ffs-i16.ll
+++ b/llvm/test/Transforms/InstCombine/ffs-i16.ll
@@ -18,8 +18,8 @@ define void @fold_ffs(i16 %x) {
; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i16 [[CTTZ]], 1
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i16 [[X]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[DOTNOT]], i16 0, i16 [[TMP1]]
-; CHECK-NEXT: call void @sink(i16 [[TMP2]])
+; CHECK-NEXT: [[NX:%.*]] = select i1 [[DOTNOT]], i16 0, i16 [[TMP1]]
+; CHECK-NEXT: call void @sink(i16 [[NX]])
; CHECK-NEXT: ret void
;
%n0 = call i16 @ffs(i16 0)
diff --git a/llvm/test/Transforms/InstCombine/float-shrink-compare.ll b/llvm/test/Transforms/InstCombine/float-shrink-compare.ll
index c8c0a0ddaa8b8..e6e41ad03ce59 100644
--- a/llvm/test/Transforms/InstCombine/float-shrink-compare.ll
+++ b/llvm/test/Transforms/InstCombine/float-shrink-compare.ll
@@ -5,8 +5,8 @@ target triple = "x86_64-apple-macosx10.8.0"
define i1 @test1(float %x, float %y) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[CEIL:%.*]] = call float @llvm.ceil.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[CEIL]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ceil.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -18,8 +18,8 @@ define i1 @test1(float %x, float %y) {
define i1 @test1_intrin(float %x, float %y) {
; CHECK-LABEL: @test1_intrin(
-; CHECK-NEXT: [[CEIL:%.*]] = call float @llvm.ceil.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[CEIL]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ceil.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -31,8 +31,8 @@ define i1 @test1_intrin(float %x, float %y) {
define i1 @test2(float %x, float %y) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -44,8 +44,8 @@ define i1 @test2(float %x, float %y) {
define i1 @test2_intrin(float %x, float %y) {
; CHECK-LABEL: @test2_intrin(
-; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -57,8 +57,8 @@ define i1 @test2_intrin(float %x, float %y) {
define i1 @fmf_test2(float %x, float %y) {
; CHECK-LABEL: @fmf_test2(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[TMP2]]
;
%1 = fpext float %x to double
@@ -70,8 +70,8 @@ define i1 @fmf_test2(float %x, float %y) {
define i1 @test3(float %x, float %y) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FLOOR]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.floor.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -84,8 +84,8 @@ define i1 @test3(float %x, float %y) {
define i1 @test3_intrin(float %x, float %y) {
; CHECK-LABEL: @test3_intrin(
-; CHECK-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FLOOR]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.floor.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -97,8 +97,8 @@ define i1 @test3_intrin(float %x, float %y) {
define i1 @test4(float %x, float %y) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[NEARBYINT:%.*]] = call float @llvm.nearbyint.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[NEARBYINT]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.nearbyint.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -110,8 +110,8 @@ define i1 @test4(float %x, float %y) {
define i1 @shrink_nearbyint_intrin(float %x, float %y) {
; CHECK-LABEL: @shrink_nearbyint_intrin(
-; CHECK-NEXT: [[NEARBYINT:%.*]] = call float @llvm.nearbyint.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[NEARBYINT]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.nearbyint.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -123,8 +123,8 @@ define i1 @shrink_nearbyint_intrin(float %x, float %y) {
define i1 @test5(float %x, float %y) {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[RINT:%.*]] = call float @llvm.rint.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[RINT]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.rint.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -136,8 +136,8 @@ define i1 @test5(float %x, float %y) {
define i1 @test6(float %x, float %y) {
; CHECK-LABEL: @test6(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.round.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.round.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -149,8 +149,8 @@ define i1 @test6(float %x, float %y) {
define i1 @test6_intrin(float %x, float %y) {
; CHECK-LABEL: @test6_intrin(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.round.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.round.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -162,8 +162,8 @@ define i1 @test6_intrin(float %x, float %y) {
define i1 @test6a(float %x, float %y) {
; CHECK-LABEL: @test6a(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.roundeven.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.roundeven.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -175,8 +175,8 @@ define i1 @test6a(float %x, float %y) {
define i1 @test6a_intrin(float %x, float %y) {
; CHECK-LABEL: @test6a_intrin(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.roundeven.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.roundeven.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -188,8 +188,8 @@ define i1 @test6a_intrin(float %x, float %y) {
define i1 @test7(float %x, float %y) {
; CHECK-LABEL: @test7(
-; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.trunc.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TRUNC]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.trunc.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -201,8 +201,8 @@ define i1 @test7(float %x, float %y) {
define i1 @test7_intrin(float %x, float %y) {
; CHECK-LABEL: @test7_intrin(
-; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.trunc.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TRUNC]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.trunc.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -214,8 +214,8 @@ define i1 @test7_intrin(float %x, float %y) {
define i1 @test8(float %x, float %y) {
; CHECK-LABEL: @test8(
-; CHECK-NEXT: [[CEIL:%.*]] = call float @llvm.ceil.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[CEIL]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ceil.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -227,8 +227,8 @@ define i1 @test8(float %x, float %y) {
define i1 @test8_intrin(float %x, float %y) {
; CHECK-LABEL: @test8_intrin(
-; CHECK-NEXT: [[CEIL:%.*]] = call float @llvm.ceil.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[CEIL]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ceil.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -240,8 +240,8 @@ define i1 @test8_intrin(float %x, float %y) {
define i1 @test9(float %x, float %y) {
; CHECK-LABEL: @test9(
-; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -253,8 +253,8 @@ define i1 @test9(float %x, float %y) {
define i1 @test9_intrin(float %x, float %y) {
; CHECK-LABEL: @test9_intrin(
-; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -266,8 +266,8 @@ define i1 @test9_intrin(float %x, float %y) {
define i1 @test10(float %x, float %y) {
; CHECK-LABEL: @test10(
-; CHECK-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FLOOR]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.floor.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -279,8 +279,8 @@ define i1 @test10(float %x, float %y) {
define i1 @test10_intrin(float %x, float %y) {
; CHECK-LABEL: @test10_intrin(
-; CHECK-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FLOOR]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.floor.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -292,8 +292,8 @@ define i1 @test10_intrin(float %x, float %y) {
define i1 @test11(float %x, float %y) {
; CHECK-LABEL: @test11(
-; CHECK-NEXT: [[NEARBYINT:%.*]] = call float @llvm.nearbyint.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[NEARBYINT]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.nearbyint.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -305,8 +305,8 @@ define i1 @test11(float %x, float %y) {
define i1 @test11_intrin(float %x, float %y) {
; CHECK-LABEL: @test11_intrin(
-; CHECK-NEXT: [[NEARBYINT:%.*]] = call float @llvm.nearbyint.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[NEARBYINT]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.nearbyint.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -318,8 +318,8 @@ define i1 @test11_intrin(float %x, float %y) {
define i1 @test12(float %x, float %y) {
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[RINT:%.*]] = call float @llvm.rint.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[RINT]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.rint.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -331,8 +331,8 @@ define i1 @test12(float %x, float %y) {
define i1 @test13(float %x, float %y) {
; CHECK-LABEL: @test13(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.round.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.round.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -344,8 +344,8 @@ define i1 @test13(float %x, float %y) {
define i1 @test13_intrin(float %x, float %y) {
; CHECK-LABEL: @test13_intrin(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.round.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.round.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -357,8 +357,8 @@ define i1 @test13_intrin(float %x, float %y) {
define i1 @test13a(float %x, float %y) {
; CHECK-LABEL: @test13a(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.roundeven.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.roundeven.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -370,8 +370,8 @@ define i1 @test13a(float %x, float %y) {
define i1 @test13a_intrin(float %x, float %y) {
; CHECK-LABEL: @test13a_intrin(
-; CHECK-NEXT: [[ROUND:%.*]] = call float @llvm.roundeven.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ROUND]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.roundeven.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -383,8 +383,8 @@ define i1 @test13a_intrin(float %x, float %y) {
define i1 @test14(float %x, float %y) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.trunc.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TRUNC]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.trunc.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -396,8 +396,8 @@ define i1 @test14(float %x, float %y) {
define i1 @test14_intrin(float %x, float %y) {
; CHECK-LABEL: @test14_intrin(
-; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.trunc.f32(float %x)
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TRUNC]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.trunc.f32(float [[X:%.*]])
+; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%x.ext = fpext float %x to double
@@ -409,9 +409,9 @@ define i1 @test14_intrin(float %x, float %y) {
define i1 @test15(float %x, float %y, float %z) {
; CHECK-LABEL: @test15(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], [[Z:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[FMINF:%.*]] = call nsz float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[FMINF]], [[Z:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%1 = fpext float %x to double
%2 = fpext float %y to double
@@ -423,9 +423,9 @@ define i1 @test15(float %x, float %y, float %z) {
define i1 @test16(float %x, float %y, float %z) {
; CHECK-LABEL: @test16(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], [[Z:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[FMINF:%.*]] = call nsz float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[FMINF]], [[Z:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%1 = fpext float %z to double
%2 = fpext float %x to double
@@ -437,9 +437,9 @@ define i1 @test16(float %x, float %y, float %z) {
define i1 @test17(float %x, float %y, float %z) {
; CHECK-LABEL: @test17(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], [[Z:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[FMAXF:%.*]] = call nsz float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[FMAXF]], [[Z:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%1 = fpext float %x to double
%2 = fpext float %y to double
@@ -451,9 +451,9 @@ define i1 @test17(float %x, float %y, float %z) {
define i1 @test18(float %x, float %y, float %z) {
; CHECK-LABEL: @test18(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], [[Z:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[FMAXF:%.*]] = call nsz float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[FMAXF]], [[Z:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%1 = fpext float %z to double
%2 = fpext float %x to double
@@ -465,8 +465,8 @@ define i1 @test18(float %x, float %y, float %z) {
define i1 @test19(float %x, float %y, float %z) {
; CHECK-LABEL: @test19(
-; CHECK-NEXT: [[COPYSIGNF:%.*]] = call float @copysignf(float %x, float %y) #0
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[COPYSIGNF]], %z
+; CHECK-NEXT: [[COPYSIGNF:%.*]] = call float @copysignf(float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[COPYSIGNF]], [[Z:%.*]]
; CHECK-NEXT: ret i1 [[TMP1]]
;
%1 = fpext float %x to double
@@ -479,9 +479,9 @@ define i1 @test19(float %x, float %y, float %z) {
define i1 @test20(float %x, float %y) {
; CHECK-LABEL: @test20(
-; CHECK-NEXT: [[TMP1:%.*]] = call nsz float @llvm.minnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq float [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[FMINF:%.*]] = call nsz float @llvm.minnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq float [[FMINF]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%1 = fpext float %y to double
%2 = fpext float %x to double
diff --git a/llvm/test/Transforms/InstCombine/fls-i16.ll b/llvm/test/Transforms/InstCombine/fls-i16.ll
index 83f3dbd339463..e19b230d3163d 100644
--- a/llvm/test/Transforms/InstCombine/fls-i16.ll
+++ b/llvm/test/Transforms/InstCombine/fls-i16.ll
@@ -17,8 +17,8 @@ define void @fold_fls(i16 %x) {
; CHECK-NEXT: call void @sink(i16 0)
; CHECK-NEXT: call void @sink(i16 1)
; CHECK-NEXT: [[CTLZ:%.*]] = call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]]
-; CHECK-NEXT: [[TMP1:%.*]] = sub nuw nsw i16 16, [[CTLZ]]
-; CHECK-NEXT: call void @sink(i16 [[TMP1]])
+; CHECK-NEXT: [[NX:%.*]] = sub nuw nsw i16 16, [[CTLZ]]
+; CHECK-NEXT: call void @sink(i16 [[NX]])
; CHECK-NEXT: ret void
;
%n0 = call i16 @fls(i16 0)
diff --git a/llvm/test/Transforms/InstCombine/fmul-exp.ll b/llvm/test/Transforms/InstCombine/fmul-exp.ll
index f5908d94e5bb0..62d22b8c085c2 100644
--- a/llvm/test/Transforms/InstCombine/fmul-exp.ll
+++ b/llvm/test/Transforms/InstCombine/fmul-exp.ll
@@ -23,9 +23,9 @@ define double @exp_a_exp_b_multiple_uses(double %a, double %b) {
; CHECK-LABEL: @exp_a_exp_b_multiple_uses(
; CHECK-NEXT: [[T1:%.*]] = call double @llvm.exp.f64(double [[B:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[B]]
-; CHECK-NEXT: [[TMP2:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP1]])
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP1]])
; CHECK-NEXT: call void @use(double [[T1]])
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: ret double [[MUL]]
;
%t = call double @llvm.exp.f64(double %a)
%t1 = call double @llvm.exp.f64(double %b)
@@ -56,8 +56,8 @@ define double @exp_a_exp_b_multiple_uses_both(double %a, double %b) {
define double @exp_a_exp_b_reassoc(double %a, double %b) {
; CHECK-LABEL: @exp_a_exp_b_reassoc(
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP1]])
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP1]])
+; CHECK-NEXT: ret double [[MUL]]
;
%t = call double @llvm.exp.f64(double %a)
%t1 = call double @llvm.exp.f64(double %b)
@@ -67,9 +67,9 @@ define double @exp_a_exp_b_reassoc(double %a, double %b) {
define double @exp_a_a(double %a) {
; CHECK-LABEL: @exp_a_a(
-; CHECK-NEXT: [[T:%.*]] = fadd reassoc double [[A:%.*]], [[A]]
-; CHECK-NEXT: [[E:%.*]] = call reassoc double @llvm.exp.f64(double [[T]])
-; CHECK-NEXT: ret double [[E]]
+; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[A]]
+; CHECK-NEXT: [[M:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP1]])
+; CHECK-NEXT: ret double [[M]]
;
%t = call double @llvm.exp.f64(double %a)
%m = fmul reassoc double %t, %t
@@ -97,8 +97,8 @@ define double @exp_a_exp_b_exp_c_exp_d_fast(double %a, double %b, double %c, dou
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = fadd reassoc double [[TMP1]], [[C:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = fadd reassoc double [[TMP2]], [[D:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP3]])
-; CHECK-NEXT: ret double [[TMP4]]
+; CHECK-NEXT: [[MUL2:%.*]] = call reassoc double @llvm.exp.f64(double [[TMP3]])
+; CHECK-NEXT: ret double [[MUL2]]
;
%t = call double @llvm.exp.f64(double %a)
%t1 = call double @llvm.exp.f64(double %b)
diff --git a/llvm/test/Transforms/InstCombine/fmul-exp2.ll b/llvm/test/Transforms/InstCombine/fmul-exp2.ll
index 54c723c8deded..35756cc043518 100644
--- a/llvm/test/Transforms/InstCombine/fmul-exp2.ll
+++ b/llvm/test/Transforms/InstCombine/fmul-exp2.ll
@@ -23,9 +23,9 @@ define double @exp2_a_exp2_b_multiple_uses(double %a, double %b) {
; CHECK-LABEL: @exp2_a_exp2_b_multiple_uses(
; CHECK-NEXT: [[T1:%.*]] = call double @llvm.exp2.f64(double [[B:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[B]]
-; CHECK-NEXT: [[TMP2:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP1]])
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP1]])
; CHECK-NEXT: call void @use(double [[T1]])
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: ret double [[MUL]]
;
%t = call double @llvm.exp2.f64(double %a)
%t1 = call double @llvm.exp2.f64(double %b)
@@ -36,9 +36,9 @@ define double @exp2_a_exp2_b_multiple_uses(double %a, double %b) {
define double @exp2_a_a(double %a) {
; CHECK-LABEL: @exp2_a_a(
-; CHECK-NEXT: [[T:%.*]] = fadd reassoc double [[A:%.*]], [[A]]
-; CHECK-NEXT: [[E:%.*]] = call reassoc double @llvm.exp2.f64(double [[T]])
-; CHECK-NEXT: ret double [[E]]
+; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[A]]
+; CHECK-NEXT: [[M:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP1]])
+; CHECK-NEXT: ret double [[M]]
;
%t = call double @llvm.exp2.f64(double %a)
%m = fmul reassoc double %t, %t
@@ -67,8 +67,8 @@ define double @exp2_a_exp2_b_multiple_uses_both(double %a, double %b) {
define double @exp2_a_exp2_b_reassoc(double %a, double %b) {
; CHECK-LABEL: @exp2_a_exp2_b_reassoc(
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP1]])
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP1]])
+; CHECK-NEXT: ret double [[MUL]]
;
%t = call double @llvm.exp2.f64(double %a)
%t1 = call double @llvm.exp2.f64(double %b)
@@ -82,8 +82,8 @@ define double @exp2_a_exp2_b_exp2_c_exp2_d(double %a, double %b, double %c, doub
; CHECK-NEXT: [[TMP1:%.*]] = fadd reassoc double [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = fadd reassoc double [[TMP1]], [[C:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = fadd reassoc double [[TMP2]], [[D:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP3]])
-; CHECK-NEXT: ret double [[TMP4]]
+; CHECK-NEXT: [[MUL2:%.*]] = call reassoc double @llvm.exp2.f64(double [[TMP3]])
+; CHECK-NEXT: ret double [[MUL2]]
;
%t = call double @llvm.exp2.f64(double %a)
%t1 = call double @llvm.exp2.f64(double %b)
diff --git a/llvm/test/Transforms/InstCombine/fmul-sqrt.ll b/llvm/test/Transforms/InstCombine/fmul-sqrt.ll
index 2cea44069b47f..72ac2f18f113a 100644
--- a/llvm/test/Transforms/InstCombine/fmul-sqrt.ll
+++ b/llvm/test/Transforms/InstCombine/fmul-sqrt.ll
@@ -42,8 +42,8 @@ define double @sqrt_a_sqrt_b_multiple_uses(double %a, double %b) {
define double @sqrt_a_sqrt_b_reassoc_nnan(double %a, double %b) {
; CHECK-LABEL: @sqrt_a_sqrt_b_reassoc_nnan(
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call reassoc nnan double @llvm.sqrt.f64(double [[TMP1]])
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc nnan double @llvm.sqrt.f64(double [[TMP1]])
+; CHECK-NEXT: ret double [[MUL]]
;
%1 = call double @llvm.sqrt.f64(double %a)
%2 = call double @llvm.sqrt.f64(double %b)
@@ -75,8 +75,8 @@ define double @sqrt_a_sqrt_b_sqrt_c_sqrt_d_reassoc(double %a, double %b, double
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nnan arcp double [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = fmul reassoc nnan double [[TMP1]], [[C:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = fmul reassoc nnan ninf double [[TMP2]], [[D:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = call reassoc nnan ninf double @llvm.sqrt.f64(double [[TMP3]])
-; CHECK-NEXT: ret double [[TMP4]]
+; CHECK-NEXT: [[MUL2:%.*]] = call reassoc nnan ninf double @llvm.sqrt.f64(double [[TMP3]])
+; CHECK-NEXT: ret double [[MUL2]]
;
%1 = call double @llvm.sqrt.f64(double %a)
%2 = call double @llvm.sqrt.f64(double %b)
@@ -103,7 +103,7 @@ define double @rsqrt_x_reassociate_extra_use(double %x, ptr %p) {
; CHECK-LABEL: @rsqrt_x_reassociate_extra_use(
; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[RSQRT:%.*]] = fdiv double 1.000000e+00, [[SQRT]]
-; CHECK-NEXT: [[RES:%.*]] = fdiv reassoc nsz double [[X:%.*]], [[SQRT]]
+; CHECK-NEXT: [[RES:%.*]] = fdiv reassoc nsz double [[X]], [[SQRT]]
; CHECK-NEXT: store double [[RSQRT]], ptr [[P:%.*]], align 8
; CHECK-NEXT: ret double [[RES]]
;
diff --git a/llvm/test/Transforms/InstCombine/fneg.ll b/llvm/test/Transforms/InstCombine/fneg.ll
index 24f70770c590a..207e38f0953ed 100644
--- a/llvm/test/Transforms/InstCombine/fneg.ll
+++ b/llvm/test/Transforms/InstCombine/fneg.ll
@@ -706,8 +706,8 @@ define float @select_common_op_fneg_false(float %x, i1 %b) {
define float @fabs(float %a) {
; CHECK-LABEL: @fabs(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.fabs.f32(float [[A:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[FNEG1:%.*]] = call nnan ninf nsz float @llvm.fabs.f32(float [[A:%.*]])
+; CHECK-NEXT: ret float [[FNEG1]]
;
%fneg = fneg float %a
%cmp = fcmp ogt float %a, %fneg
@@ -761,8 +761,8 @@ define float @fnabs_2_nsz(float %a) {
define float @fnabs_2_nsz_nnan(float %a) {
; CHECK-LABEL: @fnabs_2_nsz_nnan(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz float @llvm.fabs.f32(float [[A:%.*]])
-; CHECK-NEXT: [[FNEG1:%.*]] = fneg float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call nnan nsz float @llvm.fabs.f32(float [[A:%.*]])
+; CHECK-NEXT: [[FNEG1:%.*]] = fneg float [[SEL]]
; CHECK-NEXT: ret float [[FNEG1]]
;
%fneg = fneg float %a
diff --git a/llvm/test/Transforms/InstCombine/fold-bin-operand.ll b/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
index 3d53f451f9d03..e225b201d743e 100644
--- a/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
+++ b/llvm/test/Transforms/InstCombine/fold-bin-operand.ll
@@ -29,8 +29,8 @@ define i32 @g(i32 %x) {
define i32 @h(i1 %A, i32 %B) {
; CHECK-LABEL: @h(
; CHECK-NEXT: EntryBlock:
-; CHECK-NEXT: [[B_OP:%.*]] = add i32 [[B:%.*]], 2
-; CHECK-NEXT: [[OP:%.*]] = select i1 [[A:%.*]], i32 3, i32 [[B_OP]]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[B:%.*]], 2
+; CHECK-NEXT: [[OP:%.*]] = select i1 [[A:%.*]], i32 3, i32 [[TMP0]]
; CHECK-NEXT: ret i32 [[OP]]
;
EntryBlock:
diff --git a/llvm/test/Transforms/InstCombine/freeze-phi.ll b/llvm/test/Transforms/InstCombine/freeze-phi.ll
index 2b8f56b504bb2..8bdfc90f20a4e 100644
--- a/llvm/test/Transforms/InstCombine/freeze-phi.ll
+++ b/llvm/test/Transforms/InstCombine/freeze-phi.ll
@@ -73,10 +73,10 @@ define i32 @one(i1 %cond, i32 %x) {
; CHECK: A:
; CHECK-NEXT: br label [[C:%.*]]
; CHECK: B:
-; CHECK-NEXT: [[PHI_FR:%.*]] = freeze i32 [[X:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[X:%.*]]
; CHECK-NEXT: br label [[C]]
; CHECK: C:
-; CHECK-NEXT: [[Y:%.*]] = phi i32 [ 0, [[A]] ], [ [[PHI_FR]], [[B]] ]
+; CHECK-NEXT: [[Y:%.*]] = phi i32 [ 0, [[A]] ], [ [[TMP1]], [[B]] ]
; CHECK-NEXT: ret i32 [[Y]]
;
br i1 %cond, label %A, label %B
@@ -187,14 +187,14 @@ define i32 @one_constexpr(i8 %cond, i32 %x) {
; CHECK-NEXT: i8 1, label [[C:%.*]]
; CHECK-NEXT: ]
; CHECK: A:
-; CHECK-NEXT: [[PHI_FR:%.*]] = freeze i32 ptrtoint (ptr getelementptr inbounds (i8, ptr @glb, i64 2) to i32)
+; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 ptrtoint (ptr getelementptr inbounds (i8, ptr @glb, i64 2) to i32)
; CHECK-NEXT: br label [[D:%.*]]
; CHECK: B:
; CHECK-NEXT: br label [[D]]
; CHECK: C:
; CHECK-NEXT: br label [[D]]
; CHECK: D:
-; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[PHI_FR]], [[A]] ], [ 32, [[B]] ], [ 0, [[C]] ]
+; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[TMP1]], [[A]] ], [ 32, [[B]] ], [ 0, [[C]] ]
; CHECK-NEXT: ret i32 [[Y]]
;
switch i8 %cond, label %A [
diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll
index 969957ce6ffa4..a2d0c3eb39d69 100644
--- a/llvm/test/Transforms/InstCombine/icmp-add.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-add.ll
@@ -980,8 +980,8 @@ define i1 @slt_offset_nsw(i8 %a, i8 %c) {
define i32 @increment_max(i32 %x) {
; CHECK-LABEL: @increment_max(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -1)
-; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], 1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = add nsw i32 [[TMP1]], 1
+; CHECK-NEXT: ret i32 [[S]]
;
%a = add nsw i32 %x, 1
%c = icmp sgt i32 %a, 0
@@ -992,8 +992,8 @@ define i32 @increment_max(i32 %x) {
define i32 @decrement_max(i32 %x) {
; CHECK-LABEL: @decrement_max(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = add nsw i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[S]]
;
%a = add nsw i32 %x, -1
%c = icmp sgt i32 %a, 0
@@ -1004,8 +1004,8 @@ define i32 @decrement_max(i32 %x) {
define i32 @increment_min(i32 %x) {
; CHECK-LABEL: @increment_min(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 -1)
-; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], 1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = add nsw i32 [[TMP1]], 1
+; CHECK-NEXT: ret i32 [[S]]
;
%a = add nsw i32 %x, 1
%c = icmp slt i32 %a, 0
@@ -1016,8 +1016,8 @@ define i32 @increment_min(i32 %x) {
define i32 @decrement_min(i32 %x) {
; CHECK-LABEL: @decrement_min(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = add nsw i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[S]]
;
%a = add nsw i32 %x, -1
%c = icmp slt i32 %a, 0
diff --git a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
index 891e40274a37d..050033b93edae 100644
--- a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
@@ -12,8 +12,8 @@ define i1 @test_eq(i1 %cond) {
; CHECK: merge:
; CHECK-NEXT: br label [[EXIT:%.*]]
; CHECK: exit:
-; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND]], true
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[COMPARE:%.*]] = xor i1 [[COND]], true
+; CHECK-NEXT: ret i1 [[COMPARE]]
;
entry:
br i1 %cond, label %if.true, label %if.false
diff --git a/llvm/test/Transforms/InstCombine/icmp-custom-dl.ll b/llvm/test/Transforms/InstCombine/icmp-custom-dl.ll
index e83d5055c8257..330825e1055ea 100644
--- a/llvm/test/Transforms/InstCombine/icmp-custom-dl.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-custom-dl.ll
@@ -72,8 +72,8 @@ define i1 @test60_addrspacecast(ptr %foo, i64 %i, i64 %j) {
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[J:%.*]] to i32
; CHECK-NEXT: [[I_TR:%.*]] = trunc i64 [[I:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[I_TR]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[CMP]]
;
%bit = addrspacecast ptr %foo to ptr addrspace(3)
%gep1 = getelementptr inbounds i32, ptr addrspace(3) %bit, i64 %i
@@ -87,8 +87,8 @@ define i1 @test60_addrspacecast_smaller(ptr %foo, i16 %i, i64 %j) {
; CHECK-LABEL: @test60_addrspacecast_smaller(
; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nsw i16 [[I:%.*]], 2
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[J:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i16 [[GEP1_IDX]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[GEP1_IDX]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[CMP]]
;
%bit = addrspacecast ptr %foo to ptr addrspace(1)
%gep1 = getelementptr inbounds i32, ptr addrspace(1) %bit, i16 %i
@@ -102,8 +102,8 @@ define i1 @test60_addrspacecast_larger(ptr addrspace(1) %foo, i32 %i, i16 %j) {
; CHECK-LABEL: @test60_addrspacecast_larger(
; CHECK-NEXT: [[I_TR:%.*]] = trunc i32 [[I:%.*]] to i16
; CHECK-NEXT: [[TMP1:%.*]] = shl i16 [[I_TR]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i16 [[TMP1]], [[J:%.*]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[TMP1]], [[J:%.*]]
+; CHECK-NEXT: ret i1 [[CMP]]
;
%bit = addrspacecast ptr addrspace(1) %foo to ptr addrspace(2)
%gep1 = getelementptr inbounds i32, ptr addrspace(2) %bit, i32 %i
diff --git a/llvm/test/Transforms/InstCombine/icmp-div-constant.ll b/llvm/test/Transforms/InstCombine/icmp-div-constant.ll
index 9348af51f4ae6..8dcb96284685f 100644
--- a/llvm/test/Transforms/InstCombine/icmp-div-constant.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-div-constant.ll
@@ -119,10 +119,10 @@ define i32 @icmp_div(i16 %a, i16 %c) {
; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]]
; CHECK: then:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[C:%.*]], 0
-; CHECK-NEXT: [[PHI_BO:%.*]] = sext i1 [[CMP]] to i32
+; CHECK-NEXT: [[TMP0:%.*]] = sext i1 [[CMP]] to i32
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[PHI_BO]], [[THEN]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[TMP0]], [[THEN]] ]
; CHECK-NEXT: ret i32 [[PHI]]
;
entry:
@@ -174,10 +174,10 @@ define i32 @icmp_div3(i16 %a, i16 %c) {
; CHECK-NEXT: br i1 [[TOBOOL]], label [[THEN:%.*]], label [[EXIT:%.*]]
; CHECK: then:
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[C:%.*]], 0
-; CHECK-NEXT: [[PHI_BO:%.*]] = sext i1 [[CMP]] to i32
+; CHECK-NEXT: [[TMP0:%.*]] = sext i1 [[CMP]] to i32
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[PHI_BO]], [[THEN]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[TMP0]], [[THEN]] ]
; CHECK-NEXT: ret i32 [[PHI]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/icmp-dom.ll b/llvm/test/Transforms/InstCombine/icmp-dom.ll
index a356a5aa78278..f4b9022d14349 100644
--- a/llvm/test/Transforms/InstCombine/icmp-dom.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-dom.ll
@@ -353,12 +353,12 @@ f:
define i32 @PR48900(i32 %i, ptr %p) {
; CHECK-LABEL: @PR48900(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[I:%.*]], i32 1)
-; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[TMP1]], 0
+; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[I:%.*]], i32 1)
+; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[UMAX]], 0
; CHECK-NEXT: br i1 [[I4]], label [[TRUELABEL:%.*]], label [[FALSELABEL:%.*]]
; CHECK: truelabel:
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP1]], i32 2)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[UMAX]], i32 2)
+; CHECK-NEXT: ret i32 [[SMIN]]
; CHECK: falselabel:
; CHECK-NEXT: ret i32 0
;
@@ -381,12 +381,12 @@ falselabel:
define i8 @PR48900_alt(i8 %i, ptr %p) {
; CHECK-LABEL: @PR48900_alt(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[I:%.*]], i8 -127)
-; CHECK-NEXT: [[I4:%.*]] = icmp ugt i8 [[TMP1]], -128
+; CHECK-NEXT: [[SMAX:%.*]] = call i8 @llvm.smax.i8(i8 [[I:%.*]], i8 -127)
+; CHECK-NEXT: [[I4:%.*]] = icmp ugt i8 [[SMAX]], -128
; CHECK-NEXT: br i1 [[I4]], label [[TRUELABEL:%.*]], label [[FALSELABEL:%.*]]
; CHECK: truelabel:
-; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smin.i8(i8 [[TMP1]], i8 -126)
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i8 @llvm.smin.i8(i8 [[SMAX]], i8 -126)
+; CHECK-NEXT: ret i8 [[UMIN]]
; CHECK: falselabel:
; CHECK-NEXT: ret i8 0
;
diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-and.ll b/llvm/test/Transforms/InstCombine/icmp-mul-and.ll
index a2df53e84ef5a..3a202be58245f 100644
--- a/llvm/test/Transforms/InstCombine/icmp-mul-and.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-mul-and.ll
@@ -269,8 +269,8 @@ define i1 @pr51551_neg2(i32 %x, i32 %y) {
; CHECK-LABEL: @pr51551_neg2(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[Y:%.*]], 1
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[X_OP:%.*]] = and i32 [[X:%.*]], 7
-; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[X_OP]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X:%.*]], 7
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[TMP2]], 0
; CHECK-NEXT: [[CMP:%.*]] = select i1 [[DOTNOT]], i1 true, i1 [[CMP1]]
; CHECK-NEXT: ret i1 [[CMP]]
;
diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
index 581f9452929fc..74b8bfab82ed4 100644
--- a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
@@ -13,17 +13,17 @@ define i32 @sterix(i32, i8, i64) {
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], [[SH_PROM]]
; CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[SHR]] to i64
; CHECK-NEXT: [[MUL3:%.*]] = mul nuw nsw i64 [[CONV]], [[CONV2]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[MUL3]], 4294967296
-; CHECK-NEXT: br i1 [[TMP3]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
+; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp ult i64 [[MUL3]], 4294967296
+; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
; CHECK: lor.rhs:
; CHECK-NEXT: [[AND:%.*]] = and i64 [[MUL3]], [[TMP2]]
; CHECK-NEXT: [[CONV4:%.*]] = trunc i64 [[AND]] to i32
; CHECK-NEXT: [[TOBOOL7_NOT:%.*]] = icmp eq i32 [[CONV4]], 0
-; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL7_NOT]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL7_NOT]] to i32
; CHECK-NEXT: br label [[LOR_END]]
; CHECK: lor.end:
-; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[PHI_CAST]], [[LOR_RHS]] ]
-; CHECK-NEXT: ret i32 [[TMP4]]
+; CHECK-NEXT: [[CONV8:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[TMP3]], [[LOR_RHS]] ]
+; CHECK-NEXT: ret i32 [[CONV8]]
;
entry:
%conv = zext i32 %0 to i64
@@ -131,10 +131,10 @@ define i1 @PR46561(i1 %a, i1 %x, i1 %y, i8 %z) {
; CHECK-NEXT: [[MULBOOL:%.*]] = and i1 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[Z:%.*]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[TMP0]], 0
-; CHECK-NEXT: [[PHI_CMP:%.*]] = xor i1 [[TMP1]], [[MULBOOL]]
+; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP1]], [[MULBOOL]]
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P:%.*]] = phi i1 [ [[PHI_CMP]], [[COND_TRUE]] ], [ false, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[P:%.*]] = phi i1 [ [[TMP2]], [[COND_TRUE]] ], [ false, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i1 [[P]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/icmp-shl-nuw.ll b/llvm/test/Transforms/InstCombine/icmp-shl-nuw.ll
index e0b39a452b652..57c3abc7b9841 100644
--- a/llvm/test/Transforms/InstCombine/icmp-shl-nuw.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-shl-nuw.ll
@@ -3,7 +3,7 @@
define i1 @icmp_ugt_32(i64) {
; CHECK-LABEL: @icmp_ugt_32(
-; CHECK-NEXT: [[D:%.*]] = icmp ne i64 %0, 0
+; CHECK-NEXT: [[D:%.*]] = icmp ne i64 [[TMP0:%.*]], 0
; CHECK-NEXT: ret i1 [[D]]
;
%c = shl nuw i64 %0, 32
@@ -13,7 +13,7 @@ define i1 @icmp_ugt_32(i64) {
define i1 @icmp_ule_64(i128) {
; CHECK-LABEL: @icmp_ule_64(
-; CHECK-NEXT: [[D:%.*]] = icmp eq i128 %0, 0
+; CHECK-NEXT: [[D:%.*]] = icmp eq i128 [[TMP0:%.*]], 0
; CHECK-NEXT: ret i1 [[D]]
;
%c = shl nuw i128 %0, 64
@@ -23,7 +23,7 @@ define i1 @icmp_ule_64(i128) {
define i1 @icmp_ugt_16(i64) {
; CHECK-LABEL: @icmp_ugt_16(
-; CHECK-NEXT: [[D:%.*]] = icmp ugt i64 %0, 15
+; CHECK-NEXT: [[D:%.*]] = icmp ugt i64 [[TMP0:%.*]], 15
; CHECK-NEXT: ret i1 [[D]]
;
%c = shl nuw i64 %0, 16
@@ -33,7 +33,7 @@ define i1 @icmp_ugt_16(i64) {
define <2 x i1> @icmp_ule_16x2(<2 x i64>) {
; CHECK-LABEL: @icmp_ule_16x2(
-; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i64> %0, zeroinitializer
+; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i64> [[TMP0:%.*]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[D]]
;
%c = shl nuw <2 x i64> %0, <i64 16, i64 16>
@@ -43,7 +43,7 @@ define <2 x i1> @icmp_ule_16x2(<2 x i64>) {
define <2 x i1> @icmp_ule_16x2_nonzero(<2 x i64>) {
; CHECK-LABEL: @icmp_ule_16x2_nonzero(
-; CHECK-NEXT: [[D:%.*]] = icmp ult <2 x i64> %0, <i64 4, i64 4>
+; CHECK-NEXT: [[D:%.*]] = icmp ult <2 x i64> [[TMP0:%.*]], <i64 4, i64 4>
; CHECK-NEXT: ret <2 x i1> [[D]]
;
%c = shl nuw <2 x i64> %0, <i64 16, i64 16>
@@ -53,7 +53,7 @@ define <2 x i1> @icmp_ule_16x2_nonzero(<2 x i64>) {
define <2 x i1> @icmp_ule_12x2(<2 x i64>) {
; CHECK-LABEL: @icmp_ule_12x2(
-; CHECK-NEXT: [[D:%.*]] = icmp ult <2 x i64> %0, <i64 4, i64 4>
+; CHECK-NEXT: [[D:%.*]] = icmp ult <2 x i64> [[TMP0:%.*]], <i64 4, i64 4>
; CHECK-NEXT: ret <2 x i1> [[D]]
;
%c = shl nuw <2 x i64> %0, <i64 12, i64 12>
@@ -63,7 +63,7 @@ define <2 x i1> @icmp_ule_12x2(<2 x i64>) {
define i1 @icmp_ult_8(i64) {
; CHECK-LABEL: @icmp_ult_8(
-; CHECK-NEXT: [[D:%.*]] = icmp ult i64 %0, 16
+; CHECK-NEXT: [[D:%.*]] = icmp ult i64 [[TMP0:%.*]], 16
; CHECK-NEXT: ret i1 [[D]]
;
%c = shl nuw i64 %0, 8
@@ -73,7 +73,7 @@ define i1 @icmp_ult_8(i64) {
define <2 x i1> @icmp_uge_8x2(<2 x i16>) {
; CHECK-LABEL: @icmp_uge_8x2(
-; CHECK-NEXT: [[D:%.*]] = icmp ugt <2 x i16> %0, <i16 15, i16 15>
+; CHECK-NEXT: [[D:%.*]] = icmp ugt <2 x i16> [[TMP0:%.*]], <i16 15, i16 15>
; CHECK-NEXT: ret <2 x i1> [[D]]
;
%c = shl nuw <2 x i16> %0, <i16 8, i16 8>
@@ -83,7 +83,7 @@ define <2 x i1> @icmp_uge_8x2(<2 x i16>) {
define <2 x i1> @icmp_ugt_16x2(<2 x i32>) {
; CHECK-LABEL: @icmp_ugt_16x2(
-; CHECK-NEXT: [[D:%.*]] = icmp ugt <2 x i32> %0, <i32 15, i32 15>
+; CHECK-NEXT: [[D:%.*]] = icmp ugt <2 x i32> [[TMP0:%.*]], <i32 15, i32 15>
; CHECK-NEXT: ret <2 x i1> [[D]]
;
%c = shl nuw <2 x i32> %0, <i32 16, i32 16>
diff --git a/llvm/test/Transforms/InstCombine/icmp-xor-signbit.ll b/llvm/test/Transforms/InstCombine/icmp-xor-signbit.ll
index 110c2a34e3d52..27f154ad23bb1 100644
--- a/llvm/test/Transforms/InstCombine/icmp-xor-signbit.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-xor-signbit.ll
@@ -5,7 +5,7 @@
define i1 @slt_to_ult(i8 %x, i8 %y) {
; CHECK-LABEL: @slt_to_ult(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 128
@@ -18,7 +18,7 @@ define i1 @slt_to_ult(i8 %x, i8 %y) {
define <2 x i1> @slt_to_ult_splat(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @slt_to_ult_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 128, i8 128>
@@ -31,7 +31,7 @@ define <2 x i1> @slt_to_ult_splat(<2 x i8> %x, <2 x i8> %y) {
define i1 @ult_to_slt(i8 %x, i8 %y) {
; CHECK-LABEL: @ult_to_slt(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 128
@@ -42,7 +42,7 @@ define i1 @ult_to_slt(i8 %x, i8 %y) {
define <2 x i1> @ult_to_slt_splat(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @ult_to_slt_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 128, i8 128>
@@ -55,7 +55,7 @@ define <2 x i1> @ult_to_slt_splat(<2 x i8> %x, <2 x i8> %y) {
define i1 @slt_to_ugt(i8 %x, i8 %y) {
; CHECK-LABEL: @slt_to_ugt(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 127
@@ -66,7 +66,7 @@ define i1 @slt_to_ugt(i8 %x, i8 %y) {
define <2 x i1> @slt_to_ugt_splat(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @slt_to_ugt_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 127, i8 127>
@@ -79,7 +79,7 @@ define <2 x i1> @slt_to_ugt_splat(<2 x i8> %x, <2 x i8> %y) {
define i1 @ult_to_sgt(i8 %x, i8 %y) {
; CHECK-LABEL: @ult_to_sgt(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 127
@@ -90,7 +90,7 @@ define i1 @ult_to_sgt(i8 %x, i8 %y) {
define <2 x i1> @ult_to_sgt_splat(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @ult_to_sgt_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> %x, %y
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 127, i8 127>
@@ -103,7 +103,7 @@ define <2 x i1> @ult_to_sgt_splat(<2 x i8> %x, <2 x i8> %y) {
define i1 @sge_to_ugt(i8 %x) {
; CHECK-LABEL: @sge_to_ugt(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 %x, -114
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[X:%.*]], -114
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 128
@@ -113,7 +113,7 @@ define i1 @sge_to_ugt(i8 %x) {
define <2 x i1> @sge_to_ugt_splat(<2 x i8> %x) {
; CHECK-LABEL: @sge_to_ugt_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> %x, <i8 -114, i8 -114>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 -114, i8 -114>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 128, i8 128>
@@ -125,7 +125,7 @@ define <2 x i1> @sge_to_ugt_splat(<2 x i8> %x) {
define i1 @uge_to_sgt(i8 %x) {
; CHECK-LABEL: @uge_to_sgt(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 %x, -114
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[X:%.*]], -114
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 128
@@ -135,7 +135,7 @@ define i1 @uge_to_sgt(i8 %x) {
define <2 x i1> @uge_to_sgt_splat(<2 x i8> %x) {
; CHECK-LABEL: @uge_to_sgt_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> %x, <i8 -114, i8 -114>
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 -114, i8 -114>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 128, i8 128>
@@ -147,7 +147,7 @@ define <2 x i1> @uge_to_sgt_splat(<2 x i8> %x) {
define i1 @sge_to_ult(i8 %x) {
; CHECK-LABEL: @sge_to_ult(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 %x, 113
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[X:%.*]], 113
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 127
@@ -157,7 +157,7 @@ define i1 @sge_to_ult(i8 %x) {
define <2 x i1> @sge_to_ult_splat(<2 x i8> %x) {
; CHECK-LABEL: @sge_to_ult_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> %x, <i8 113, i8 113>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 113, i8 113>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 127, i8 127>
@@ -169,7 +169,7 @@ define <2 x i1> @sge_to_ult_splat(<2 x i8> %x) {
define i1 @uge_to_slt(i8 %x) {
; CHECK-LABEL: @uge_to_slt(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 %x, 113
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 113
; CHECK-NEXT: ret i1 [[CMP]]
;
%a = xor i8 %x, 127
@@ -179,7 +179,7 @@ define i1 @uge_to_slt(i8 %x) {
define <2 x i1> @uge_to_slt_splat(<2 x i8> %x) {
; CHECK-LABEL: @uge_to_slt_splat(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> %x, <i8 113, i8 113>
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], <i8 113, i8 113>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%a = xor <2 x i8> %x, <i8 127, i8 127>
@@ -192,8 +192,8 @@ define <2 x i1> @uge_to_slt_splat(<2 x i8> %x) {
define <8 x i1> @sgt_to_ugt_bitcasted_splat(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @sgt_to_ugt_bitcasted_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> %x to <8 x i8>
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> %y to <8 x i8>
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[X:%.*]] to <8 x i8>
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[Y:%.*]] to <8 x i8>
; CHECK-NEXT: [[E:%.*]] = icmp ugt <8 x i8> [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret <8 x i1> [[E]]
;
diff --git a/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll b/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
index 0b7b8faf0adfe..5407254001561 100644
--- a/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
@@ -269,8 +269,8 @@ define <4 x i32> @extractelt_insertion(<2 x i32> %x, i32 %y) {
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: [[B:%.*]] = shufflevector <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, <4 x i32> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
; CHECK-NEXT: [[C:%.*]] = add i32 [[Y:%.*]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 [[C]]
-; CHECK-NEXT: [[E:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[D:%.*]] = extractelement <4 x i32> [[TMP0]], i32 [[C]]
+; CHECK-NEXT: [[E:%.*]] = icmp eq i32 [[D]], 0
; CHECK-NEXT: [[RET:%.*]] = select i1 [[E]], <4 x i32> [[B]], <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[RET]]
;
diff --git a/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll b/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
index d34ca0c247ef0..f94935513f531 100644
--- a/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
@@ -269,8 +269,8 @@ define <4 x i32> @extractelt_insertion(<2 x i32> %x, i32 %y) {
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
; CHECK-NEXT: [[B:%.*]] = shufflevector <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, <4 x i32> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
; CHECK-NEXT: [[C:%.*]] = add i32 [[Y:%.*]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 [[C]]
-; CHECK-NEXT: [[E:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: [[D:%.*]] = extractelement <4 x i32> [[TMP0]], i32 [[C]]
+; CHECK-NEXT: [[E:%.*]] = icmp eq i32 [[D]], 0
; CHECK-NEXT: [[RET:%.*]] = select i1 [[E]], <4 x i32> [[B]], <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[RET]]
;
diff --git a/llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll b/llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
index 04f8d2c2a2e7a..7cef922eaf0ce 100644
--- a/llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
+++ b/llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
@@ -10,8 +10,8 @@ declare void @llvm.assume(i1)
; Basic pattern
define i8 @t0(i8 %x) {
; CHECK-LABEL: @t0(
-; CHECK-NEXT: [[X_BIASED1:%.*]] = add i8 [[X:%.*]], 15
-; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and i8 [[X_BIASED1]], -16
+; CHECK-NEXT: [[X_BIASED:%.*]] = add i8 [[X:%.*]], 15
+; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and i8 [[X_BIASED]], -16
; CHECK-NEXT: ret i8 [[X_ROUNDEDUP]]
;
%x.lowbits = and i8 %x, 15
@@ -25,8 +25,8 @@ define i8 @t0(i8 %x) {
; Another alignment is fine
define i8 @t1(i8 %x) {
; CHECK-LABEL: @t1(
-; CHECK-NEXT: [[X_BIASED1:%.*]] = add i8 [[X:%.*]], 31
-; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and i8 [[X_BIASED1]], -32
+; CHECK-NEXT: [[X_BIASED:%.*]] = add i8 [[X:%.*]], 31
+; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and i8 [[X_BIASED]], -32
; CHECK-NEXT: ret i8 [[X_ROUNDEDUP]]
;
%x.lowbits = and i8 %x, 31
@@ -58,8 +58,8 @@ define i8 @t3_commutative(i8 %x) {
; CHECK-NEXT: [[X_LOWBITS:%.*]] = and i8 [[X:%.*]], 15
; CHECK-NEXT: [[X_LOWBITS_ARE_NOT_ZERO:%.*]] = icmp ne i8 [[X_LOWBITS]], 0
; CHECK-NEXT: call void @use.i1(i1 [[X_LOWBITS_ARE_NOT_ZERO]])
-; CHECK-NEXT: [[X_BIASED1:%.*]] = add i8 [[X]], 15
-; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and i8 [[X_BIASED1]], -16
+; CHECK-NEXT: [[X_BIASED:%.*]] = add i8 [[X]], 15
+; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and i8 [[X_BIASED]], -16
; CHECK-NEXT: ret i8 [[X_ROUNDEDUP]]
;
%x.lowbits = and i8 %x, 15
@@ -74,8 +74,8 @@ define i8 @t3_commutative(i8 %x) {
; Basic splat vector test
define <2 x i8> @t4_splat(<2 x i8> %x) {
; CHECK-LABEL: @t4_splat(
-; CHECK-NEXT: [[X_BIASED1:%.*]] = add <2 x i8> [[X:%.*]], <i8 15, i8 15>
-; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and <2 x i8> [[X_BIASED1]], <i8 -16, i8 -16>
+; CHECK-NEXT: [[X_BIASED:%.*]] = add <2 x i8> [[X:%.*]], <i8 15, i8 15>
+; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and <2 x i8> [[X_BIASED]], <i8 -16, i8 -16>
; CHECK-NEXT: ret <2 x i8> [[X_ROUNDEDUP]]
;
%x.lowbits = and <2 x i8> %x, <i8 15, i8 15>
@@ -115,8 +115,8 @@ define <2 x i8> @t5_splat_undef_0b0010(<2 x i8> %x) {
}
define <2 x i8> @t5_splat_undef_0b0100(<2 x i8> %x) {
; CHECK-LABEL: @t5_splat_undef_0b0100(
-; CHECK-NEXT: [[X_BIASED1:%.*]] = add <2 x i8> [[X:%.*]], <i8 15, i8 15>
-; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and <2 x i8> [[X_BIASED1]], <i8 -16, i8 -16>
+; CHECK-NEXT: [[X_BIASED:%.*]] = add <2 x i8> [[X:%.*]], <i8 15, i8 15>
+; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and <2 x i8> [[X_BIASED]], <i8 -16, i8 -16>
; CHECK-NEXT: ret <2 x i8> [[X_ROUNDEDUP]]
;
%x.lowbits = and <2 x i8> %x, <i8 15, i8 15>
@@ -128,8 +128,8 @@ define <2 x i8> @t5_splat_undef_0b0100(<2 x i8> %x) {
}
define <2 x i8> @t5_splat_undef_0b1000(<2 x i8> %x) {
; CHECK-LABEL: @t5_splat_undef_0b1000(
-; CHECK-NEXT: [[X_BIASED1:%.*]] = add <2 x i8> [[X:%.*]], <i8 15, i8 15>
-; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and <2 x i8> [[X_BIASED1]], <i8 -16, i8 -16>
+; CHECK-NEXT: [[X_BIASED:%.*]] = add <2 x i8> [[X:%.*]], <i8 15, i8 15>
+; CHECK-NEXT: [[X_ROUNDEDUP:%.*]] = and <2 x i8> [[X_BIASED]], <i8 -16, i8 -16>
; CHECK-NEXT: ret <2 x i8> [[X_ROUNDEDUP]]
;
%x.lowbits = and <2 x i8> %x, <i8 15, i8 undef>
diff --git a/llvm/test/Transforms/InstCombine/intptr2.ll b/llvm/test/Transforms/InstCombine/intptr2.ll
index da178ecd9981d..6ace82bc8e09e 100644
--- a/llvm/test/Transforms/InstCombine/intptr2.ll
+++ b/llvm/test/Transforms/InstCombine/intptr2.ll
@@ -11,11 +11,11 @@ define void @test1(ptr %a, ptr readnone %a_end, ptr %b.i) {
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[A_ADDR_03:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ], [ [[A]], [[FOR_BODY_PREHEADER]] ]
-; CHECK-NEXT: [[B_ADDR_02_PTR:%.*]] = phi ptr [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[B_I]], [[FOR_BODY_PREHEADER]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[B_ADDR_02_PTR]], align 4
+; CHECK-NEXT: [[B_ADDR_02_IN:%.*]] = phi ptr [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[B_I]], [[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[B_ADDR_02_IN]], align 4
; CHECK-NEXT: [[MUL_I:%.*]] = fmul float [[TMP1]], 4.200000e+01
; CHECK-NEXT: store float [[MUL_I]], ptr [[A_ADDR_03]], align 4
-; CHECK-NEXT: [[ADD]] = getelementptr inbounds float, ptr [[B_ADDR_02_PTR]], i64 1
+; CHECK-NEXT: [[ADD]] = getelementptr inbounds float, ptr [[B_ADDR_02_IN]], i64 1
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds float, ptr [[A_ADDR_03]], i64 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult ptr [[INCDEC_PTR]], [[A_END]]
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]]
diff --git a/llvm/test/Transforms/InstCombine/intrinsics.ll b/llvm/test/Transforms/InstCombine/intrinsics.ll
index dd9fd68660604..3ac7c728e1984 100644
--- a/llvm/test/Transforms/InstCombine/intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/intrinsics.ll
@@ -150,7 +150,7 @@ define i32 @cttz_knownbits2(i32 %arg) {
define <2 x i32> @cttz_knownbits2_vec(<2 x i32> %arg) {
; CHECK-LABEL: @cttz_knownbits2_vec(
; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[ARG:%.*]], <i32 4, i32 4>
-; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true) #[[ATTR2]]
+; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true) #[[ATTR2]], !range [[RNG0]]
; CHECK-NEXT: ret <2 x i32> [[CNT]]
;
%or = or <2 x i32> %arg, <i32 4, i32 4>
@@ -267,7 +267,7 @@ define i8 @ctlz_knownbits2(i8 %arg) {
define <2 x i8> @ctlz_knownbits2_vec(<2 x i8> %arg) {
; CHECK-LABEL: @ctlz_knownbits2_vec(
; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[ARG:%.*]], <i8 32, i8 32>
-; CHECK-NEXT: [[CNT:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[OR]], i1 true) #[[ATTR2]]
+; CHECK-NEXT: [[CNT:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[OR]], i1 true) #[[ATTR2]], !range [[RNG1]]
; CHECK-NEXT: ret <2 x i8> [[CNT]]
;
%or = or <2 x i8> %arg, <i8 32, i8 32>
@@ -325,7 +325,7 @@ define i32 @ctlz_no_zero(i32 %a) {
define <2 x i32> @ctlz_no_zero_vec(<2 x i32> %a) {
; CHECK-LABEL: @ctlz_no_zero_vec(
; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[A:%.*]], <i32 8, i32 8>
-; CHECK-NEXT: [[CTLZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[OR]], i1 true)
+; CHECK-NEXT: [[CTLZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[OR]], i1 true), !range [[RNG2]]
; CHECK-NEXT: ret <2 x i32> [[CTLZ]]
;
%or = or <2 x i32> %a, <i32 8, i32 8>
@@ -363,7 +363,7 @@ define i32 @cttz_no_zero(i32 %a) {
define <2 x i32> @cttz_no_zero_vec(<2 x i32> %a) {
; CHECK-LABEL: @cttz_no_zero_vec(
; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[A:%.*]], <i32 8, i32 8>
-; CHECK-NEXT: [[CTTZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true)
+; CHECK-NEXT: [[CTTZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true), !range [[RNG3]]
; CHECK-NEXT: ret <2 x i32> [[CTTZ]]
;
%or = or <2 x i32> %a, <i32 8, i32 8>
@@ -384,7 +384,7 @@ define i32 @ctlz_select(i32 %Value) nounwind {
define <2 x i32> @ctlz_select_vec(<2 x i32> %Value) nounwind {
; CHECK-LABEL: @ctlz_select_vec(
-; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false)
+; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false), !range [[RNG4]]
; CHECK-NEXT: ret <2 x i32> [[CTLZ]]
;
%tobool = icmp ne <2 x i32> %Value, zeroinitializer
@@ -406,7 +406,7 @@ define i32 @cttz_select(i32 %Value) nounwind {
define <2 x i32> @cttz_select_vec(<2 x i32> %Value) nounwind {
; CHECK-LABEL: @cttz_select_vec(
-; CHECK-NEXT: [[CTTZ:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false)
+; CHECK-NEXT: [[CTTZ:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false), !range [[RNG4]]
; CHECK-NEXT: ret <2 x i32> [[CTTZ]]
;
%tobool = icmp ne <2 x i32> %Value, zeroinitializer
diff --git a/llvm/test/Transforms/InstCombine/invariant.group.ll b/llvm/test/Transforms/InstCombine/invariant.group.ll
index 521be47d12099..08193e7af3f5e 100644
--- a/llvm/test/Transforms/InstCombine/invariant.group.ll
+++ b/llvm/test/Transforms/InstCombine/invariant.group.ll
@@ -87,8 +87,8 @@ define ptr addrspace(42) @simplifyUndefStrip2() {
define ptr @simplifyLaunderOfLaunder(ptr %a) {
; CHECK-LABEL: @simplifyLaunderOfLaunder(
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.launder.invariant.group.p0(ptr [[A:%.*]])
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[A3:%.*]] = call ptr @llvm.launder.invariant.group.p0(ptr [[A:%.*]])
+; CHECK-NEXT: ret ptr [[A3]]
;
%a2 = call ptr @llvm.launder.invariant.group.p0(ptr %a)
%a3 = call ptr @llvm.launder.invariant.group.p0(ptr %a2)
@@ -97,8 +97,8 @@ define ptr @simplifyLaunderOfLaunder(ptr %a) {
define ptr @simplifyStripOfLaunder(ptr %a) {
; CHECK-LABEL: @simplifyStripOfLaunder(
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[A3:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
+; CHECK-NEXT: ret ptr [[A3]]
;
%a2 = call ptr @llvm.launder.invariant.group.p0(ptr %a)
%a3 = call ptr @llvm.strip.invariant.group.p0(ptr %a2)
@@ -107,7 +107,7 @@ define ptr @simplifyStripOfLaunder(ptr %a) {
define i1 @simplifyForCompare(ptr %a) {
; CHECK-LABEL: @simplifyForCompare(
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
+; CHECK-NEXT: [[A3:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
; CHECK-NEXT: ret i1 true
;
%a2 = call ptr @llvm.launder.invariant.group.p0(ptr %a)
@@ -120,8 +120,8 @@ define i1 @simplifyForCompare(ptr %a) {
define ptr @skipWithDifferentTypes(ptr %a) {
; CHECK-LABEL: @skipWithDifferentTypes(
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[A3:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
+; CHECK-NEXT: ret ptr [[A3]]
;
%a2 = call ptr @llvm.launder.invariant.group.p0(ptr %a)
@@ -131,8 +131,8 @@ define ptr @skipWithDifferentTypes(ptr %a) {
define ptr addrspace(42) @skipWithDifferentTypesAddrspace(ptr addrspace(42) %a) {
; CHECK-LABEL: @skipWithDifferentTypesAddrspace(
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr addrspace(42) @llvm.strip.invariant.group.p42(ptr addrspace(42) [[A:%.*]])
-; CHECK-NEXT: ret ptr addrspace(42) [[TMP1]]
+; CHECK-NEXT: [[A3:%.*]] = call ptr addrspace(42) @llvm.strip.invariant.group.p42(ptr addrspace(42) [[A:%.*]])
+; CHECK-NEXT: ret ptr addrspace(42) [[A3]]
;
%a2 = call ptr addrspace(42) @llvm.launder.invariant.group.p42(ptr addrspace(42) %a)
@@ -143,8 +143,8 @@ define ptr addrspace(42) @skipWithDifferentTypesAddrspace(ptr addrspace(42) %a)
define ptr addrspace(42) @skipWithDifferentTypesDifferentAddrspace(ptr %a) {
; CHECK-LABEL: @skipWithDifferentTypesDifferentAddrspace(
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.strip.invariant.group.p0(ptr [[A:%.*]])
-; CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr [[TMP1]] to ptr addrspace(42)
-; CHECK-NEXT: ret ptr addrspace(42) [[TMP3]]
+; CHECK-NEXT: [[A3:%.*]] = addrspacecast ptr [[TMP1]] to ptr addrspace(42)
+; CHECK-NEXT: ret ptr addrspace(42) [[A3]]
;
%cast = addrspacecast ptr %a to ptr addrspace(42)
%a2 = call ptr addrspace(42) @llvm.launder.invariant.group.p42(ptr addrspace(42) %cast)
diff --git a/llvm/test/Transforms/InstCombine/isascii-i16.ll b/llvm/test/Transforms/InstCombine/isascii-i16.ll
index 131906d798a39..ef5d8c75d80c8 100644
--- a/llvm/test/Transforms/InstCombine/isascii-i16.ll
+++ b/llvm/test/Transforms/InstCombine/isascii-i16.ll
@@ -21,8 +21,8 @@ define void @fold_isascii(i16 %c) {
; CHECK-NEXT: call void @sink(i16 0)
; CHECK-NEXT: call void @sink(i16 0)
; CHECK-NEXT: [[ISASCII:%.*]] = icmp ult i16 [[C:%.*]], 128
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[ISASCII]] to i16
-; CHECK-NEXT: call void @sink(i16 [[TMP1]])
+; CHECK-NEXT: [[IC:%.*]] = zext i1 [[ISASCII]] to i16
+; CHECK-NEXT: call void @sink(i16 [[IC]])
; CHECK-NEXT: ret void
;
%i0 = call i16 @isascii(i16 0)
diff --git a/llvm/test/Transforms/InstCombine/isdigit-i16.ll b/llvm/test/Transforms/InstCombine/isdigit-i16.ll
index 35c58c282a8a9..7e63798ca438c 100644
--- a/llvm/test/Transforms/InstCombine/isdigit-i16.ll
+++ b/llvm/test/Transforms/InstCombine/isdigit-i16.ll
@@ -25,8 +25,8 @@ define void @fold_isdigit(i16 %c) {
; CHECK-NEXT: call void @sink(i16 0)
; CHECK-NEXT: [[ISDIGITTMP:%.*]] = add i16 [[C:%.*]], -48
; CHECK-NEXT: [[ISDIGIT:%.*]] = icmp ult i16 [[ISDIGITTMP]], 10
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[ISDIGIT]] to i16
-; CHECK-NEXT: call void @sink(i16 [[TMP1]])
+; CHECK-NEXT: [[IC:%.*]] = zext i1 [[ISDIGIT]] to i16
+; CHECK-NEXT: call void @sink(i16 [[IC]])
; CHECK-NEXT: ret void
;
%i0 = call i16 @isdigit(i16 0)
diff --git a/llvm/test/Transforms/InstCombine/ispow2.ll b/llvm/test/Transforms/InstCombine/ispow2.ll
index a05f9d87c9270..191ff9f005a5d 100644
--- a/llvm/test/Transforms/InstCombine/ispow2.ll
+++ b/llvm/test/Transforms/InstCombine/ispow2.ll
@@ -15,7 +15,7 @@ define i1 @is_pow2or0_negate_op(i32 %x) {
define <2 x i1> @is_pow2or0_negate_op_vec(<2 x i32> %x) {
; CHECK-LABEL: @is_pow2or0_negate_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 2, i32 2>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
@@ -39,7 +39,7 @@ define i1 @is_pow2or0_decrement_op(i8 %x) {
define <2 x i1> @is_pow2or0_decrement_op_vec(<2 x i8> %x) {
; CHECK-LABEL: @is_pow2or0_decrement_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[TMP1]], <i8 2, i8 2>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
@@ -63,7 +63,7 @@ define i1 @isnot_pow2or0_negate_op(i32 %x) {
define <2 x i1> @isnot_pow2or0_negate_op_vec(<2 x i32> %x) {
; CHECK-LABEL: @isnot_pow2or0_negate_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[TMP1]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
@@ -87,7 +87,7 @@ define i1 @isnot_pow2or0_decrement_op(i8 %x) {
define <2 x i1> @isnot_pow2or0_decrement_op_vec(<2 x i8> %x) {
; CHECK-LABEL: @isnot_pow2or0_decrement_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> [[TMP1]], <i8 1, i8 1>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
@@ -249,7 +249,7 @@ define i1 @is_pow2_ctpop_extra_uses_logical(i32 %x) {
define <2 x i1> @is_pow2_ctpop_commute_vec(<2 x i8> %x) {
; CHECK-LABEL: @is_pow2_ctpop_commute_vec(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[T0]], <i8 1, i8 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -460,7 +460,7 @@ define i1 @isnot_pow2_ctpop_extra_uses_logical(i32 %x) {
define <2 x i1> @isnot_pow2_ctpop_commute_vec(<2 x i8> %x) {
; CHECK-LABEL: @isnot_pow2_ctpop_commute_vec(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[T0]], <i8 1, i8 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -597,7 +597,7 @@ define i1 @is_pow2_negate_op_logical(i32 %x) {
define <2 x i1> @is_pow2_negate_op_vec(<2 x i32> %x) {
; CHECK-LABEL: @is_pow2_negate_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]]
; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -639,7 +639,7 @@ define i1 @is_pow2_decrement_op_logical(i8 %x) {
define <2 x i1> @is_pow2_decrement_op_vec(<2 x i8> %x) {
; CHECK-LABEL: @is_pow2_decrement_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[TMP1]], <i8 1, i8 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -681,7 +681,7 @@ define i1 @isnot_pow2_negate_op_logical(i32 %x) {
define <2 x i1> @isnot_pow2_negate_op_vec(<2 x i32> %x) {
; CHECK-LABEL: @isnot_pow2_negate_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]]
; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i32> [[TMP1]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -723,7 +723,7 @@ define i1 @isnot_pow2_decrement_op_logical(i8 %x) {
define <2 x i1> @isnot_pow2_decrement_op_vec(<2 x i8> %x) {
; CHECK-LABEL: @isnot_pow2_decrement_op_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[TMP1]], <i8 1, i8 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -778,7 +778,7 @@ define i1 @is_pow2or0_ctpop_logical(i32 %x) {
define <2 x i1> @is_pow2or0_ctpop_commute_vec(<2 x i8> %x) {
; CHECK-LABEL: @is_pow2or0_ctpop_commute_vec(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T0]], <i8 2, i8 2>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -867,7 +867,7 @@ define i1 @is_pow2or0_ctpop_wrong_cmp_op1_logical(i32 %x) {
define <2 x i1> @is_pow2or0_ctpop_commute_vec_wrong_cmp_op1(<2 x i8> %x) {
; CHECK-LABEL: @is_pow2or0_ctpop_commute_vec_wrong_cmp_op1(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[T0]], <i8 -1, i8 1>
; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq <2 x i8> [[X]], zeroinitializer
; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[CMP]], [[ISZERO]]
@@ -925,7 +925,7 @@ define i1 @is_pow2or0_ctpop_wrong_pred2_logical(i32 %x) {
define <2 x i1> @is_pow2or0_ctpop_commute_vec_wrong_pred3(<2 x i8> %x) {
; CHECK-LABEL: @is_pow2or0_ctpop_commute_vec_wrong_pred3(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[T0]], <i8 1, i8 1>
; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq <2 x i8> [[X]], zeroinitializer
; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[CMP]], [[ISZERO]]
@@ -981,7 +981,7 @@ define i1 @isnot_pow2nor0_ctpop_logical(i32 %x) {
define <2 x i1> @isnot_pow2nor0_ctpop_commute_vec(<2 x i8> %x) {
; CHECK-LABEL: @isnot_pow2nor0_ctpop_commute_vec(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[T0]], <i8 1, i8 1>
; CHECK-NEXT: ret <2 x i1> [[R]]
;
@@ -1070,7 +1070,7 @@ define i1 @isnot_pow2nor0_ctpop_wrong_cmp_op1_logical(i32 %x) {
define <2 x i1> @isnot_pow2nor0_ctpop_commute_vec_wrong_cmp_op1(<2 x i8> %x) {
; CHECK-LABEL: @isnot_pow2nor0_ctpop_commute_vec_wrong_cmp_op1(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i8> [[T0]], <i8 0, i8 -1>
; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne <2 x i8> [[X]], zeroinitializer
; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[CMP]], [[NOTZERO]]
@@ -1128,7 +1128,7 @@ define i1 @isnot_pow2nor0_ctpop_wrong_pred2_logical(i32 %x) {
define <2 x i1> @isnot_pow2nor0_wrong_pred3_ctpop_commute_vec(<2 x i8> %x) {
; CHECK-LABEL: @isnot_pow2nor0_wrong_pred3_ctpop_commute_vec(
-; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]])
+; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i8> [[T0]], <i8 1, i8 1>
; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne <2 x i8> [[X]], zeroinitializer
; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[CMP]], [[NOTZERO]]
diff --git a/llvm/test/Transforms/InstCombine/known-non-zero.ll b/llvm/test/Transforms/InstCombine/known-non-zero.ll
index 225477fd5dbd4..b5755700e2a41 100644
--- a/llvm/test/Transforms/InstCombine/known-non-zero.ll
+++ b/llvm/test/Transforms/InstCombine/known-non-zero.ll
@@ -13,7 +13,7 @@ define i32 @test0(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.cttz.i64(i64 [[X]], i1 true), [[RNG0:!range !.*]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.cttz.i64(i64 [[X]], i1 true), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
@@ -40,7 +40,7 @@ define i32 @test1(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
@@ -69,7 +69,7 @@ define <8 x i64> @test2(<8 x i64> %x) {
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B]], 0
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> [[X]], i1 false)
+; CHECK-NEXT: [[CTZ:%.*]] = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> [[X]], i1 false), !range [[RNG0]]
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: [[RES:%.*]] = phi <8 x i64> [ [[CTZ]], [[NON_ZERO]] ], [ zeroinitializer, [[START:%.*]] ]
@@ -140,7 +140,7 @@ define i64 @test_sgt_zero(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -163,7 +163,7 @@ define i64 @test_slt_neg_ten(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], -10
; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -186,7 +186,7 @@ define i64 @test_slt_ten(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], 10
; CHECK-NEXT: br i1 [[C]], label [[MAYBE_ZERO:%.*]], label [[EXIT:%.*]]
; CHECK: maybe_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -209,7 +209,7 @@ define i64 @test_ugt_unknown(i64 %x, i64 %y) {
; CHECK-NEXT: [[C:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -232,7 +232,7 @@ define i64 @test_sle_zero(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], 1
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -255,7 +255,7 @@ define i64 @test_sge_neg_ten(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], -11
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -278,7 +278,7 @@ define i64 @test_sge_ten(i64 %x) {
; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], 9
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[MAYBE_ZERO:%.*]]
; CHECK: maybe_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
@@ -301,7 +301,7 @@ define i64 @test_ule_unknown(i64 %x, i64 %y) {
; CHECK-NEXT: [[C_NOT:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: br i1 [[C_NOT]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
; CHECK: non_zero:
-; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret i64 [[CTZ]]
; CHECK: exit:
; CHECK-NEXT: ret i64 -1
diff --git a/llvm/test/Transforms/InstCombine/load-bitcast-select.ll b/llvm/test/Transforms/InstCombine/load-bitcast-select.ll
index 9e4bcfcdd8380..85eb17ae3d9d5 100644
--- a/llvm/test/Transforms/InstCombine/load-bitcast-select.ll
+++ b/llvm/test/Transforms/InstCombine/load-bitcast-select.ll
@@ -21,8 +21,8 @@ define void @_Z3foov() {
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp fast olt float [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[CMP_I]], float [[TMP2]], float [[TMP1]]
-; CHECK-NEXT: store float [[TMP3]], ptr [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[CMP_I]], float [[TMP2]], float [[TMP1]]
+; CHECK-NEXT: store float [[DOTV]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]]
;
@@ -80,8 +80,8 @@ define void @bitcasted_minmax_with_select_of_pointers(ptr %loadaddr1, ptr %loada
; CHECK-NEXT: [[LD1:%.*]] = load float, ptr [[LOADADDR1:%.*]], align 4
; CHECK-NEXT: [[LD2:%.*]] = load float, ptr [[LOADADDR2:%.*]], align 4
; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
-; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
-; CHECK-NEXT: store float [[LD3]], ptr [[STOREADDR:%.*]], align 4
+; CHECK-NEXT: [[LD_V:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
+; CHECK-NEXT: store float [[LD_V]], ptr [[STOREADDR:%.*]], align 4
; CHECK-NEXT: ret void
;
%ld1 = load float, ptr %loadaddr1, align 4
diff --git a/llvm/test/Transforms/InstCombine/load-cmp.ll b/llvm/test/Transforms/InstCombine/load-cmp.ll
index 883a73f96fe32..7fb6e7a3a37b3 100644
--- a/llvm/test/Transforms/InstCombine/load-cmp.ll
+++ b/llvm/test/Transforms/InstCombine/load-cmp.ll
@@ -174,8 +174,8 @@ define i1 @test7(i32 %X) {
define i1 @test8(i32 %X) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 8
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = icmp eq i32 [[TMP1]], 8
+; CHECK-NEXT: ret i1 [[S]]
;
%P = getelementptr inbounds [10 x i16], ptr @G16, i32 0, i32 %X
%Q = load i16, ptr %P
@@ -194,8 +194,8 @@ define i1 @test8(i32 %X) {
define i1 @test9(i32 %X) {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT: ret i1 [[R]]
;
%P = getelementptr inbounds [4 x { i32, i32 } ], ptr @GA, i32 0, i32 %X, i32 1
%Q = load i32, ptr %P
diff --git a/llvm/test/Transforms/InstCombine/loadstore-metadata.ll b/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
index 1ba9661f2c5d6..e7ad7600a3f5f 100644
--- a/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
+++ b/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
@@ -151,7 +151,7 @@ exit:
define void @test_load_cast_combine_nonnull(ptr %ptr) {
; CHECK-LABEL: @test_load_cast_combine_nonnull(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[PTR:%.*]], align 8, !nonnull
+; CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[PTR:%.*]], align 8, !nonnull !6
; CHECK-NEXT: [[GEP:%.*]] = getelementptr ptr, ptr [[PTR]], i64 42
; CHECK-NEXT: store ptr [[P]], ptr [[GEP]], align 8
; CHECK-NEXT: ret void
@@ -165,7 +165,7 @@ entry:
define i32 @test_load_cast_combine_noundef(ptr %ptr) {
; CHECK-LABEL: @test_load_cast_combine_noundef(
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[PTR:%.*]], align 4, !noundef
+; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[PTR:%.*]], align 4, !noundef !6
; CHECK-NEXT: ret i32 [[L1]]
;
%l = load float, ptr %ptr, !noundef !{}
diff --git a/llvm/test/Transforms/InstCombine/log-pow.ll b/llvm/test/Transforms/InstCombine/log-pow.ll
index b1f8f1c703856..58f04da280bee 100644
--- a/llvm/test/Transforms/InstCombine/log-pow.ll
+++ b/llvm/test/Transforms/InstCombine/log-pow.ll
@@ -98,6 +98,14 @@ define double @log_exp2_not_fast(double %x) {
}
define double @pr43617(double %d, i32 %i, ptr %f) {
+; CHECK-LABEL: @pr43617(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SUB:%.*]] = fneg double [[D:%.*]]
+; CHECK-NEXT: [[ICALL:%.*]] = tail call fast double [[F:%.*]](i32 [[I:%.*]])
+; CHECK-NEXT: [[LOG:%.*]] = tail call fast double @llvm.log.f64(double [[ICALL]])
+; CHECK-NEXT: [[MUL:%.*]] = fmul double [[LOG]], [[SUB]]
+; CHECK-NEXT: ret double [[MUL]]
+;
entry:
%sub = fsub double -0.000000e+00, %d
%icall = tail call fast double %f(i32 %i)
diff --git a/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll b/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
index d17a90d3e9706..29e2cb42e1bef 100644
--- a/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
@@ -5,8 +5,8 @@
define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: [[E:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[E]], i32 [[C:%.*]], i32 [[D:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[J:%.*]] = select i1 [[E]], i32 [[C:%.*]], i32 [[D:%.*]]
+; CHECK-NEXT: ret i32 [[J]]
;
%e = icmp slt i32 %a, %b
%f = sext i1 %e to i32
@@ -20,8 +20,8 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {
define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @bar(
; CHECK-NEXT: [[E:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[E]], i32 [[C:%.*]], i32 [[D:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[J:%.*]] = select i1 [[E]], i32 [[C:%.*]], i32 [[D:%.*]]
+; CHECK-NEXT: ret i32 [[J]]
;
%e = icmp slt i32 %a, %b
%f = sext i1 %e to i32
@@ -35,8 +35,8 @@ define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d) {
define i32 @goo(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @goo(
; CHECK-NEXT: [[T0:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[T0]], i32 [[C:%.*]], i32 [[D:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T0]], i32 [[C:%.*]], i32 [[D:%.*]]
+; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = icmp slt i32 %a, %b
%iftmp.0.0 = select i1 %t0, i32 -1, i32 0
@@ -49,8 +49,8 @@ define i32 @goo(i32 %a, i32 %b, i32 %c, i32 %d) {
define i32 @poo(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @poo(
-; CHECK-NEXT: [[T0:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[T3:%.*]] = select i1 [[T0]], i32 [[C:%.*]], i32 [[D:%.*]]
+; CHECK-NEXT: [[T0_NOT:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T0_NOT]], i32 [[C:%.*]], i32 [[D:%.*]]
; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = icmp slt i32 %a, %b
@@ -142,8 +142,8 @@ define <2 x i32> @fold_inverted_icmp_vector_preds(<2 x i32> %a, <2 x i32> %b, <2
define i32 @par(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @par(
; CHECK-NEXT: [[T0:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[T0]], i32 [[C:%.*]], i32 [[D:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T0]], i32 [[C:%.*]], i32 [[D:%.*]]
+; CHECK-NEXT: ret i32 [[T3]]
;
%t0 = icmp slt i32 %a, %b
%iftmp.1.0 = select i1 %t0, i32 -1, i32 0
@@ -170,8 +170,8 @@ define <2 x i64> @bitcast_select_swap0(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -192,8 +192,8 @@ define <2 x i64> @bitcast_select_swap1(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -214,8 +214,8 @@ define <2 x i64> @bitcast_select_swap2(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -236,8 +236,8 @@ define <2 x i64> @bitcast_select_swap3(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -258,8 +258,8 @@ define <2 x i64> @bitcast_select_swap4(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -280,8 +280,8 @@ define <2 x i64> @bitcast_select_swap5(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -302,8 +302,8 @@ define <2 x i64> @bitcast_select_swap6(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -324,8 +324,8 @@ define <2 x i64> @bitcast_select_swap7(<4 x i1> %cmp, <2 x double> %a, <2 x doub
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[SIA]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[SIB]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[OR]]
;
%sia = fptosi <2 x double> %a to <2 x i64>
%sib = fptosi <2 x double> %b to <2 x i64>
@@ -366,8 +366,8 @@ define <2 x i64> @bitcast_select_multi_uses(<4 x i1> %cmp, <2 x i64> %a, <2 x i6
define i1 @bools(i1 %a, i1 %b, i1 %c) {
; CHECK-LABEL: @bools(
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%not = xor i1 %c, -1
%and1 = and i1 %not, %a
@@ -394,8 +394,8 @@ define i1 @bools_multi_uses1(i1 %a, i1 %b, i1 %c) {
; CHECK-LABEL: @bools_multi_uses1(
; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[C:%.*]], true
; CHECK-NEXT: [[AND1:%.*]] = and i1 [[NOT]], [[A:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]]
-; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[TMP1]], [[AND1]]
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 [[A]]
+; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[OR]], [[AND1]]
; CHECK-NEXT: ret i1 [[XOR]]
;
%not = xor i1 %c, -1
@@ -427,8 +427,8 @@ define i1 @bools_multi_uses1_logical(i1 %a, i1 %b, i1 %c) {
define i1 @bools_multi_uses2(i1 %a, i1 %b, i1 %c) {
; CHECK-LABEL: @bools_multi_uses2(
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[C:%.*]], i1 [[B:%.*]], i1 [[A:%.*]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%not = xor i1 %c, -1
%and1 = and i1 %not, %a
@@ -460,8 +460,8 @@ define i1 @bools_multi_uses2_logical(i1 %a, i1 %b, i1 %c) {
define <4 x i1> @vec_of_bools(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c) {
; CHECK-LABEL: @vec_of_bools(
-; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[C:%.*]], <4 x i1> [[B:%.*]], <4 x i1> [[A:%.*]]
-; CHECK-NEXT: ret <4 x i1> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = select <4 x i1> [[C:%.*]], <4 x i1> [[B:%.*]], <4 x i1> [[A:%.*]]
+; CHECK-NEXT: ret <4 x i1> [[OR]]
;
%not = xor <4 x i1> %c, <i1 true, i1 true, i1 true, i1 true>
%and1 = and <4 x i1> %not, %a
@@ -475,8 +475,8 @@ define i4 @vec_of_casted_bools(i4 %a, i4 %b, <4 x i1> %c) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i4 [[B:%.*]] to <4 x i1>
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i4 [[A:%.*]] to <4 x i1>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[C:%.*]], <4 x i1> [[TMP1]], <4 x i1> [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4
-; CHECK-NEXT: ret i4 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast <4 x i1> [[TMP3]] to i4
+; CHECK-NEXT: ret i4 [[OR]]
;
%not = xor <4 x i1> %c, <i1 true, i1 true, i1 true, i1 true>
%bc1 = bitcast <4 x i1> %not to i4
@@ -491,8 +491,8 @@ define i4 @vec_of_casted_bools(i4 %a, i4 %b, <4 x i1> %c) {
define <4 x i32> @vec_sel_consts(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @vec_sel_consts(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 -1>
%and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 0>
@@ -502,8 +502,8 @@ define <4 x i32> @vec_sel_consts(<4 x i32> %a, <4 x i32> %b) {
define <3 x i129> @vec_sel_consts_weird(<3 x i129> %a, <3 x i129> %b) {
; CHECK-LABEL: @vec_sel_consts_weird(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i129> [[A:%.*]], <3 x i129> [[B:%.*]], <3 x i32> <i32 0, i32 4, i32 2>
-; CHECK-NEXT: ret <3 x i129> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = shufflevector <3 x i129> [[A:%.*]], <3 x i129> [[B:%.*]], <3 x i32> <i32 0, i32 4, i32 2>
+; CHECK-NEXT: ret <3 x i129> [[OR]]
;
%and1 = and <3 x i129> %a, <i129 -1, i129 0, i129 -1>
%and2 = and <3 x i129> %b, <i129 0, i129 -1, i129 0>
@@ -544,8 +544,8 @@ define <4 x i32> @vec_not_sel_consts_undef_elts(<4 x i32> %a, <4 x i32> %b) {
define <4 x i32> @vec_sel_xor(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c) {
; CHECK-LABEL: @vec_sel_xor(
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i1> [[C:%.*]], <i1 false, i1 true, i1 true, i1 true>
-; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[OR]]
;
%mask = sext <4 x i1> %c to <4 x i32>
%mask_flip1 = xor <4 x i32> %mask, <i32 -1, i32 0, i32 0, i32 0>
@@ -564,8 +564,8 @@ define <4 x i32> @vec_sel_xor_multi_use(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c)
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i1> [[C:%.*]], <i1 true, i1 false, i1 false, i1 false>
; CHECK-NEXT: [[MASK_FLIP1:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i1> [[C]], <i1 false, i1 true, i1 true, i1 true>
-; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
-; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[TMP3]], [[MASK_FLIP1]]
+; CHECK-NEXT: [[OR:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[OR]], [[MASK_FLIP1]]
; CHECK-NEXT: ret <4 x i32> [[ADD]]
;
%mask = sext <4 x i1> %c to <4 x i32>
@@ -648,9 +648,9 @@ define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> %
; CHECK-NEXT: [[S4:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
; CHECK-NEXT: [[SHUF_OR2:%.*]] = or <4 x i32> [[S3]], [[S4]]
; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[SHUF_OR2]] to <4 x i1>
-; CHECK-NEXT: [[DOTV:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[Z:%.*]], <4 x float> [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x float> [[DOTV]] to <4 x i32>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[SEL_V:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[Z:%.*]], <4 x float> [[X]]
+; CHECK-NEXT: [[SEL:%.*]] = bitcast <4 x float> [[SEL_V]] to <4 x i32>
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
;
%cmp = fcmp ole <4 x float> %x, %y
%sext = sext <4 x i1> %cmp to <4 x i32>
@@ -675,8 +675,8 @@ define <4 x i32> @computesignbits_through_two_input_shuffle(<4 x i32> %x, <4 x i
; CHECK-NEXT: [[SEXT2:%.*]] = sext <4 x i1> [[COND2:%.*]] to <4 x i32>
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i32> [[SEXT1]], <4 x i32> [[SEXT2]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[COND]] to <4 x i1>
-; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
;
%sext1 = sext <4 x i1> %cond1 to <4 x i32>
%sext2 = sext <4 x i1> %cond2 to <4 x i32>
diff --git a/llvm/test/Transforms/InstCombine/malloc-free-mismatched.ll b/llvm/test/Transforms/InstCombine/malloc-free-mismatched.ll
index d3f5d09ac1a3a..658dbd662508c 100644
--- a/llvm/test/Transforms/InstCombine/malloc-free-mismatched.ll
+++ b/llvm/test/Transforms/InstCombine/malloc-free-mismatched.ll
@@ -15,6 +15,11 @@ define dso_local i32 @_Z6answeri(i32 %0) {
; All we care about with this function is that LLVM doesn't crash
; when optimizing it.
define void @test_alloca() {
+; CHECK-LABEL: @test_alloca(
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 1
+; CHECK-NEXT: call void @free(ptr [[TMP1]])
+; CHECK-NEXT: ret void
+;
%1 = alloca i8
call void @free(ptr %1)
ret void
diff --git a/llvm/test/Transforms/InstCombine/malloc-free.ll b/llvm/test/Transforms/InstCombine/malloc-free.ll
index 1ffd4d825950c..dc918a7fc8080 100644
--- a/llvm/test/Transforms/InstCombine/malloc-free.ll
+++ b/llvm/test/Transforms/InstCombine/malloc-free.ll
@@ -268,7 +268,7 @@ define void @test14(ptr %foo) nofree {
; TODO: free call marked no-free -> %foo must be null
define void @test15(ptr %foo) {
; CHECK-LABEL: @test15(
-; CHECK-NEXT: call void @free(ptr [[FOO:%.*]]) #[[ATTR5:[0-9]+]]
+; CHECK-NEXT: call void @free(ptr [[FOO:%.*]]) #[[ATTR8:[0-9]+]]
; CHECK-NEXT: ret void
;
call void @free(ptr %foo) nofree
diff --git a/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll b/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
index 6ed34aed5a2dd..58d7d08594b3f 100644
--- a/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
@@ -87,8 +87,8 @@ define <2 x double> @load_speculative(ptr dereferenceable(16) align 4 %ptr, doub
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%ptv1 = insertelement <2 x double> poison, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
@@ -101,8 +101,8 @@ define <2 x double> @load_speculative_less_aligned(ptr dereferenceable(16) %ptr,
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%ptv1 = insertelement <2 x double> poison, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
diff --git a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
index b1b77bf2b89fd..12bd8660d574f 100644
--- a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
@@ -87,8 +87,8 @@ define <2 x double> @load_speculative(ptr dereferenceable(16) align 4 %ptr, doub
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
@@ -101,8 +101,8 @@ define <2 x double> @load_speculative_less_aligned(ptr dereferenceable(16) %ptr,
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
diff --git a/llvm/test/Transforms/InstCombine/masked_intrinsics_keep_metadata.ll b/llvm/test/Transforms/InstCombine/masked_intrinsics_keep_metadata.ll
index c5ff1ef81672c..1a571100323ff 100644
--- a/llvm/test/Transforms/InstCombine/masked_intrinsics_keep_metadata.ll
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics_keep_metadata.ll
@@ -18,8 +18,8 @@ define inreg <4 x i32> @mload2() #0 {
; CHECK-LABEL: @mload2(
; CHECK-NEXT: b0:
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <4 x i32>, ptr @g0, align 16, !tbaa [[TBAA0]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> [[UNMASKEDLOAD]], i32 0, i64 0
-; CHECK-NEXT: ret <4 x i32> [[TMP0]]
+; CHECK-NEXT: [[V01:%.*]] = insertelement <4 x i32> [[UNMASKEDLOAD]], i32 0, i64 0
+; CHECK-NEXT: ret <4 x i32> [[V01]]
;
b0:
%v0 = call <4 x i32> @llvm.masked.load.v4i1.p0(ptr @g0, i32 16, <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> zeroinitializer), !tbaa !0
diff --git a/llvm/test/Transforms/InstCombine/matrix-multiplication-negation.ll b/llvm/test/Transforms/InstCombine/matrix-multiplication-negation.ll
index bd1050efc160f..889bad5f2f76d 100644
--- a/llvm/test/Transforms/InstCombine/matrix-multiplication-negation.ll
+++ b/llvm/test/Transforms/InstCombine/matrix-multiplication-negation.ll
@@ -5,8 +5,8 @@
define <2 x double> @test_negation_move_to_result(<6 x double> %a, <3 x double> %b) {
; CHECK-LABEL: @test_negation_move_to_result(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> [[A:%.*]], <3 x double> [[B:%.*]], i32 2, i32 3, i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = fneg <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = fneg <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%a.neg = fneg <6 x double> %a
%res = tail call <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> %a.neg, <3 x double> %b, i32 2, i32 3, i32 1)
@@ -18,8 +18,8 @@ define <2 x double> @test_negation_move_to_result(<6 x double> %a, <3 x double>
define <2 x double> @test_negation_move_to_result_with_fastflags(<6 x double> %a, <3 x double> %b) {
; CHECK-LABEL: @test_negation_move_to_result_with_fastflags(
; CHECK-NEXT: [[TMP1:%.*]] = call fast <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> [[A:%.*]], <3 x double> [[B:%.*]], i32 2, i32 3, i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = fneg fast <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = fneg fast <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%a.neg = fneg <6 x double> %a
%res = tail call fast <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> %a.neg, <3 x double> %b, i32 2, i32 3, i32 1)
@@ -29,8 +29,8 @@ define <2 x double> @test_negation_move_to_result_with_fastflags(<6 x double> %a
define <2 x double> @test_negation_move_to_result_with_nnan_flag(<6 x double> %a, <3 x double> %b) {
; CHECK-LABEL: @test_negation_move_to_result_with_nnan_flag(
; CHECK-NEXT: [[TMP1:%.*]] = call nnan <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> [[A:%.*]], <3 x double> [[B:%.*]], i32 2, i32 3, i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = fneg nnan <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = fneg nnan <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%a.neg = fneg <6 x double> %a
%res = tail call nnan <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> %a.neg, <3 x double> %b, i32 2, i32 3, i32 1)
@@ -40,8 +40,8 @@ define <2 x double> @test_negation_move_to_result_with_nnan_flag(<6 x double> %a
define <2 x double> @test_negation_move_to_result_with_nsz_flag(<6 x double> %a, <3 x double> %b) {
; CHECK-LABEL: @test_negation_move_to_result_with_nsz_flag(
; CHECK-NEXT: [[TMP1:%.*]] = call nsz <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> [[A:%.*]], <3 x double> [[B:%.*]], i32 2, i32 3, i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = fneg nsz <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = fneg nsz <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%a.neg = fneg <6 x double> %a
%res = tail call nsz <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> %a.neg, <3 x double> %b, i32 2, i32 3, i32 1)
@@ -51,8 +51,8 @@ define <2 x double> @test_negation_move_to_result_with_nsz_flag(<6 x double> %a,
define <2 x double> @test_negation_move_to_result_with_fastflag_on_negation(<6 x double> %a, <3 x double> %b) {
; CHECK-LABEL: @test_negation_move_to_result_with_fastflag_on_negation(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> [[A:%.*]], <3 x double> [[B:%.*]], i32 2, i32 3, i32 1)
-; CHECK-NEXT: [[TMP2:%.*]] = fneg <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = fneg <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%a.neg = fneg fast<6 x double> %a
%res = tail call <2 x double> @llvm.matrix.multiply.v2f64.v6f64.v3f64(<6 x double> %a.neg, <3 x double> %b, i32 2, i32 3, i32 1)
@@ -88,8 +88,8 @@ define <9 x double> @test_move_negation_to_second_operand_with_fast_flags(<27 x
define <2 x double> @test_negation_move_to_result_from_second_operand(<3 x double> %a, <6 x double> %b){
; CHECK-LABEL: @test_negation_move_to_result_from_second_operand(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.matrix.multiply.v2f64.v3f64.v6f64(<3 x double> [[A:%.*]], <6 x double> [[B:%.*]], i32 1, i32 3, i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = fneg <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = fneg <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[RES]]
;
%b.neg = fneg <6 x double> %b
%res = tail call <2 x double> @llvm.matrix.multiply.v2f64.v3f64.v6f64(<3 x double> %a, <6 x double> %b.neg, i32 1, i32 3, i32 2)
@@ -285,8 +285,8 @@ define <6 x double> @chain_of_matrix_mutliplies_with_two_negations(<3 x double>
; CHECK-NEXT: [[TMP1:%.*]] = fneg <3 x double> [[A:%.*]]
; CHECK-NEXT: [[RES:%.*]] = tail call <15 x double> @llvm.matrix.multiply.v15f64.v3f64.v5f64(<3 x double> [[TMP1]], <5 x double> [[B:%.*]], i32 3, i32 1, i32 5)
; CHECK-NEXT: [[TMP2:%.*]] = call <6 x double> @llvm.matrix.multiply.v6f64.v15f64.v10f64(<15 x double> [[RES]], <10 x double> [[C:%.*]], i32 3, i32 5, i32 2)
-; CHECK-NEXT: [[TMP3:%.*]] = fneg <6 x double> [[TMP2]]
-; CHECK-NEXT: ret <6 x double> [[TMP3]]
+; CHECK-NEXT: [[RES_2:%.*]] = fneg <6 x double> [[TMP2]]
+; CHECK-NEXT: ret <6 x double> [[RES_2]]
;
%b.neg = fneg <5 x double> %b
%res = tail call <15 x double> @llvm.matrix.multiply.v15f64.v3f64.v5f64(<3 x double> %a, <5 x double> %b.neg, i32 3, i32 1, i32 5)
@@ -300,8 +300,8 @@ define <6 x double> @chain_of_matrix_mutliplies_propagation(<15 x double> %a, <2
; CHECK-LABEL: @chain_of_matrix_mutliplies_propagation(
; CHECK-NEXT: [[TMP1:%.*]] = call <12 x double> @llvm.matrix.multiply.v12f64.v15f64.v20f64(<15 x double> [[A:%.*]], <20 x double> [[B:%.*]], i32 3, i32 5, i32 4)
; CHECK-NEXT: [[TMP2:%.*]] = call <6 x double> @llvm.matrix.multiply.v6f64.v12f64.v8f64(<12 x double> [[TMP1]], <8 x double> [[C:%.*]], i32 3, i32 4, i32 2)
-; CHECK-NEXT: [[TMP3:%.*]] = fneg <6 x double> [[TMP2]]
-; CHECK-NEXT: ret <6 x double> [[TMP3]]
+; CHECK-NEXT: [[RES_2:%.*]] = fneg <6 x double> [[TMP2]]
+; CHECK-NEXT: ret <6 x double> [[RES_2]]
;
%a.neg = fneg <15 x double> %a
%res = tail call <12 x double> @llvm.matrix.multiply.v12f64.v15f64.v20f64(<15 x double> %a.neg, <20 x double> %b, i32 3, i32 5, i32 4)
diff --git a/llvm/test/Transforms/InstCombine/max-of-nots.ll b/llvm/test/Transforms/InstCombine/max-of-nots.ll
index 1b51ae3553b6d..acce89b38be83 100644
--- a/llvm/test/Transforms/InstCombine/max-of-nots.ll
+++ b/llvm/test/Transforms/InstCombine/max-of-nots.ll
@@ -4,8 +4,8 @@
define <2 x i32> @umin_of_nots(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @umin_of_nots(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], <i32 -1, i32 -1>
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = xor <2 x i32> [[TMP1]], <i32 -1, i32 -1>
+; CHECK-NEXT: ret <2 x i32> [[MIN]]
;
%notx = xor <2 x i32> %x, <i32 -1, i32 -1>
%noty = xor <2 x i32> %y, <i32 -1, i32 -1>
@@ -17,8 +17,8 @@ define <2 x i32> @umin_of_nots(<2 x i32> %x, <2 x i32> %y) {
define <2 x i32> @smin_of_nots(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @smin_of_nots(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], <i32 -1, i32 -1>
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = xor <2 x i32> [[TMP1]], <i32 -1, i32 -1>
+; CHECK-NEXT: ret <2 x i32> [[MIN]]
;
%notx = xor <2 x i32> %x, <i32 -1, i32 -1>
%noty = xor <2 x i32> %y, <i32 -1, i32 -1>
@@ -45,9 +45,9 @@ define i8 @umin_not_1_extra_use(i8 %x, i8 %y) {
; CHECK-LABEL: @umin_not_1_extra_use(
; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[Y:%.*]], i8 [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], -1
+; CHECK-NEXT: [[MINXY:%.*]] = xor i8 [[TMP1]], -1
; CHECK-NEXT: call void @extra_use(i8 [[NX]])
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: ret i8 [[MINXY]]
;
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
@@ -61,10 +61,10 @@ define i8 @umin_not_2_extra_use(i8 %x, i8 %y) {
; CHECK-LABEL: @umin_not_2_extra_use(
; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: [[NY:%.*]] = xor i8 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[NX]], i8 [[NY]])
+; CHECK-NEXT: [[MINXY:%.*]] = call i8 @llvm.umin.i8(i8 [[NX]], i8 [[NY]])
; CHECK-NEXT: call void @extra_use(i8 [[NX]])
; CHECK-NEXT: call void @extra_use(i8 [[NY]])
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: ret i8 [[MINXY]]
;
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
@@ -79,8 +79,8 @@ define i8 @umin_not_2_extra_use(i8 %x, i8 %y) {
define i8 @umin3_not(i8 %x, i8 %y, i8 %z) {
; CHECK-LABEL: @umin3_not(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[Y:%.*]], i8 [[X:%.*]])
-; CHECK-NEXT: [[R_V:%.*]] = call i8 @llvm.umax.i8(i8 [[TMP1]], i8 [[Z:%.*]])
+; CHECK-NEXT: [[MINMAXOP:%.*]] = call i8 @llvm.umax.i8(i8 [[Y:%.*]], i8 [[X:%.*]])
+; CHECK-NEXT: [[R_V:%.*]] = call i8 @llvm.umax.i8(i8 [[MINMAXOP]], i8 [[Z:%.*]])
; CHECK-NEXT: [[R:%.*]] = xor i8 [[R_V]], -1
; CHECK-NEXT: ret i8 [[R]]
;
@@ -130,12 +130,12 @@ define i8 @umin3_not_all_ops_extra_uses(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[XN:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: [[YN:%.*]] = xor i8 [[Y:%.*]], -1
; CHECK-NEXT: [[ZN:%.*]] = xor i8 [[Z:%.*]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[XN]], i8 [[ZN]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.umin.i8(i8 [[TMP1]], i8 [[YN]])
+; CHECK-NEXT: [[MINXZ:%.*]] = call i8 @llvm.umin.i8(i8 [[XN]], i8 [[ZN]])
+; CHECK-NEXT: [[MINXYZ:%.*]] = call i8 @llvm.umin.i8(i8 [[MINXZ]], i8 [[YN]])
; CHECK-NEXT: call void @use8(i8 [[XN]])
; CHECK-NEXT: call void @use8(i8 [[YN]])
; CHECK-NEXT: call void @use8(i8 [[ZN]])
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: ret i8 [[MINXYZ]]
;
%xn = xor i8 %x, -1
%yn = xor i8 %y, -1
@@ -173,8 +173,8 @@ define i32 @compute_min_arithmetic(i32 %x, i32 %y) {
; CHECK-LABEL: @compute_min_arithmetic(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -4
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], -1
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[NOT_MIN:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[NOT_MIN]]
;
%not_value = sub i32 3, %x
%not_y = sub i32 -1, %y
@@ -190,8 +190,8 @@ define i32 @compute_min_pessimization(i32 %x, i32 %y) {
; CHECK-NEXT: [[NOT_VALUE:%.*]] = sub i32 3, [[X:%.*]]
; CHECK-NEXT: call void @fake_use(i32 [[NOT_VALUE]])
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -4
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[TMP1]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%not_value = sub i32 3, %x
call void @fake_use(i32 %not_value)
@@ -206,8 +206,8 @@ define i32 @max_of_nots(i32 %x, i32 %y) {
; CHECK-LABEL: @max_of_nots(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[Y:%.*]], i32 0)
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[X:%.*]])
-; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], -1
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[SMAX96:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: ret i32 [[SMAX96]]
;
%c0 = icmp sgt i32 %y, 0
%xor_y = xor i32 %y, -1
@@ -223,9 +223,9 @@ define i32 @abs_of_min_of_not(i32 %x, i32 %y) {
; CHECK-LABEL: @abs_of_min_of_not(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 -3, [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], -1
-; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.abs.i32(i32 [[TMP3]], i1 false)
-; CHECK-NEXT: ret i32 [[TMP4]]
+; CHECK-NEXT: [[MIN:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[MIN]], i1 false)
+; CHECK-NEXT: ret i32 [[ABS]]
;
%xord = xor i32 %x, -1
@@ -242,8 +242,8 @@ define <2 x i32> @max_of_nots_vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @max_of_nots_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[Y:%.*]], <2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[X:%.*]])
-; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP2]], <i32 -1, i32 -1>
-; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+; CHECK-NEXT: [[SMAX96:%.*]] = xor <2 x i32> [[TMP2]], <i32 -1, i32 -1>
+; CHECK-NEXT: ret <2 x i32> [[SMAX96]]
;
%c0 = icmp sgt <2 x i32> %y, zeroinitializer
%xor_y = xor <2 x i32> %y, <i32 -1, i32 -1>
@@ -258,8 +258,8 @@ define <2 x i37> @max_of_nots_weird_type_vec(<2 x i37> %x, <2 x i37> %y) {
; CHECK-LABEL: @max_of_nots_weird_type_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i37> @llvm.smax.v2i37(<2 x i37> [[Y:%.*]], <2 x i37> zeroinitializer)
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i37> @llvm.smin.v2i37(<2 x i37> [[TMP1]], <2 x i37> [[X:%.*]])
-; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i37> [[TMP2]], <i37 -1, i37 -1>
-; CHECK-NEXT: ret <2 x i37> [[TMP3]]
+; CHECK-NEXT: [[SMAX96:%.*]] = xor <2 x i37> [[TMP2]], <i37 -1, i37 -1>
+; CHECK-NEXT: ret <2 x i37> [[SMAX96]]
;
%c0 = icmp sgt <2 x i37> %y, zeroinitializer
%xor_y = xor <2 x i37> %y, <i37 -1, i37 -1>
diff --git a/llvm/test/Transforms/InstCombine/max_known_bits.ll b/llvm/test/Transforms/InstCombine/max_known_bits.ll
index 78e76af482b25..3eb53b32efecc 100644
--- a/llvm/test/Transforms/InstCombine/max_known_bits.ll
+++ b/llvm/test/Transforms/InstCombine/max_known_bits.ll
@@ -19,9 +19,9 @@ define i16 @foo(i16 %x) {
; By analyzing the clamp pattern, we can tell the add doesn't have signed overflow.
define i16 @min_max_clamp(i16 %x) {
; CHECK-LABEL: @min_max_clamp(
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 2047)
-; CHECK-NEXT: [[E:%.*]] = add nsw i16 [[TMP2]], 1
+; CHECK-NEXT: [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
+; CHECK-NEXT: [[D:%.*]] = call i16 @llvm.smin.i16(i16 [[B]], i16 2047)
+; CHECK-NEXT: [[E:%.*]] = add nsw i16 [[D]], 1
; CHECK-NEXT: ret i16 [[E]]
;
%a = icmp sgt i16 %x, -2048
@@ -35,9 +35,9 @@ define i16 @min_max_clamp(i16 %x) {
; Same as above with min/max reversed.
define i16 @min_max_clamp_2(i16 %x) {
; CHECK-LABEL: @min_max_clamp_2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP1]], i16 -2048)
-; CHECK-NEXT: [[E:%.*]] = add nsw i16 [[TMP2]], 1
+; CHECK-NEXT: [[B:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
+; CHECK-NEXT: [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B]], i16 -2048)
+; CHECK-NEXT: [[E:%.*]] = add nsw i16 [[D]], 1
; CHECK-NEXT: ret i16 [[E]]
;
%a = icmp slt i16 %x, 2047
@@ -53,10 +53,10 @@ define i16 @min_max_clamp_2(i16 %x) {
; overflow the original type and can be moved before the extend.
define i32 @min_max_clamp_3(i16 %x) {
; CHECK-LABEL: @min_max_clamp_3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 2047)
-; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
+; CHECK-NEXT: [[D:%.*]] = call i16 @llvm.smin.i16(i16 [[B]], i16 2047)
+; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%a = icmp sgt i16 %x, -2048
%b = select i1 %a, i16 %x, i16 -2048
@@ -71,10 +71,10 @@ define i32 @min_max_clamp_3(i16 %x) {
; Same as above with min/max order reversed
define i32 @min_max_clamp_4(i16 %x) {
; CHECK-LABEL: @min_max_clamp_4(
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP1]], i16 -2048)
-; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[B:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
+; CHECK-NEXT: [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B]], i16 -2048)
+; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT: ret i32 [[TMP1]]
;
%a = icmp slt i16 %x, 2047
%b = select i1 %a, i16 %x, i16 2047
diff --git a/llvm/test/Transforms/InstCombine/maximum.ll b/llvm/test/Transforms/InstCombine/maximum.ll
index 180c4ed141c07..82e4c8794c1c8 100644
--- a/llvm/test/Transforms/InstCombine/maximum.ll
+++ b/llvm/test/Transforms/InstCombine/maximum.ll
@@ -147,8 +147,8 @@ define float @maximum_f32_val_nan(float %x) {
define float @maximum_f32_1_maximum_val_p0(float %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_val_p0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maximum.f32(float %x, float 0.0)
%z = call float @llvm.maximum.f32(float %y, float 1.0)
@@ -157,8 +157,8 @@ define float @maximum_f32_1_maximum_val_p0(float %x) {
define float @maximum_f32_1_maximum_p0_val_fast(float %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fast(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maximum.f32(float 0.0, float %x)
%z = call fast float @llvm.maximum.f32(float %y, float 1.0)
@@ -167,8 +167,8 @@ define float @maximum_f32_1_maximum_p0_val_fast(float %x) {
define float @maximum_f32_1_maximum_p0_val_fmf1(float %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fmf1(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan arcp float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan arcp float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call arcp nnan float @llvm.maximum.f32(float 0.0, float %x)
%z = call arcp nnan ninf float @llvm.maximum.f32(float %y, float 1.0)
@@ -177,8 +177,8 @@ define float @maximum_f32_1_maximum_p0_val_fmf1(float %x) {
define float @maximum_f32_1_maximum_p0_val_fmf2(float %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fmf2(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call arcp nnan ninf float @llvm.maximum.f32(float 0.0, float %x)
%z = call nnan float @llvm.maximum.f32(float %y, float 1.0)
@@ -187,8 +187,8 @@ define float @maximum_f32_1_maximum_p0_val_fmf2(float %x) {
define float @maximum_f32_1_maximum_p0_val_fmf3(float %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fmf3(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan ninf float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nnan ninf float @llvm.maximum.f32(float 0.0, float %x)
%z = call arcp nnan ninf float @llvm.maximum.f32(float %y, float 1.0)
@@ -197,8 +197,8 @@ define float @maximum_f32_1_maximum_p0_val_fmf3(float %x) {
define float @maximum_f32_p0_maximum_val_n0(float %x) {
; CHECK-LABEL: @maximum_f32_p0_maximum_val_n0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maximum.f32(float %x, float -0.0)
%z = call float @llvm.maximum.f32(float %y, float 0.0)
@@ -207,8 +207,8 @@ define float @maximum_f32_p0_maximum_val_n0(float %x) {
define float @maximum_f32_1_maximum_p0_val(float %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_p0_val(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maximum.f32(float 0.0, float %x)
%z = call float @llvm.maximum.f32(float %y, float 1.0)
@@ -217,8 +217,8 @@ define float @maximum_f32_1_maximum_p0_val(float %x) {
define <2 x float> @maximum_f32_1_maximum_val_p0_val_v2f32(<2 x float> %x) {
; CHECK-LABEL: @maximum_f32_1_maximum_val_p0_val_v2f32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.maximum.v2f32(<2 x float> [[X:%.*]], <2 x float> <float 1.000000e+00, float 1.000000e+00>)
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call <2 x float> @llvm.maximum.v2f32(<2 x float> [[X:%.*]], <2 x float> <float 1.000000e+00, float 1.000000e+00>)
+; CHECK-NEXT: ret <2 x float> [[Z]]
;
%y = call <2 x float> @llvm.maximum.v2f32(<2 x float> %x, <2 x float> zeroinitializer)
%z = call <2 x float> @llvm.maximum.v2f32(<2 x float> %y, <2 x float><float 1.0, float 1.0>)
@@ -390,8 +390,8 @@ define float @unary_neg_neg_extra_use_x_and_y(float %x, float %y) {
define float @reduce_precision(float %x, float %y) {
; CHECK-LABEL: @reduce_precision(
-; CHECK-NEXT: [[MAXIMUM:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MAXIMUM]]
+; CHECK-NEXT: [[MAXIMUM1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MAXIMUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -402,8 +402,8 @@ define float @reduce_precision(float %x, float %y) {
define float @reduce_precision_fmf(float %x, float %y) {
; CHECK-LABEL: @reduce_precision_fmf(
-; CHECK-NEXT: [[MAXIMUM:%.*]] = call nnan float @llvm.maximum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MAXIMUM]]
+; CHECK-NEXT: [[MAXIMUM1:%.*]] = call nnan float @llvm.maximum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MAXIMUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -414,8 +414,8 @@ define float @reduce_precision_fmf(float %x, float %y) {
define float @negated_op(float %x) {
; CHECK-LABEL: @negated_op(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: ret float [[R]]
;
%negx = fneg float %x
%r = call float @llvm.maximum.f32(float %x, float %negx)
@@ -424,8 +424,8 @@ define float @negated_op(float %x) {
define <2 x double> @negated_op_fmf_commute_vec(<2 x double> %x) {
; CHECK-LABEL: @negated_op_fmf_commute_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> [[X:%.*]])
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: ret <2 x double> [[R]]
;
%negx = fneg <2 x double> %x
%r = call nsz nnan ninf <2 x double> @llvm.maximum.v2f64(<2 x double> %negx, <2 x double> %x)
diff --git a/llvm/test/Transforms/InstCombine/maxnum.ll b/llvm/test/Transforms/InstCombine/maxnum.ll
index ca6e29ec19760..27a2c70333b3b 100644
--- a/llvm/test/Transforms/InstCombine/maxnum.ll
+++ b/llvm/test/Transforms/InstCombine/maxnum.ll
@@ -147,8 +147,8 @@ define float @maxnum_f32_val_nan(float %x) {
define float @maxnum_f32_1_maxnum_val_p0(float %x) {
; CHECK-LABEL: @maxnum_f32_1_maxnum_val_p0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maxnum.f32(float %x, float 0.0)
%z = call float @llvm.maxnum.f32(float %y, float 1.0)
@@ -157,8 +157,8 @@ define float @maxnum_f32_1_maxnum_val_p0(float %x) {
define float @maxnum_f32_1_maxnum_p0_val_fast(float %x) {
; CHECK-LABEL: @maxnum_f32_1_maxnum_p0_val_fast(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maxnum.f32(float 0.0, float %x)
%z = call fast float @llvm.maxnum.f32(float %y, float 1.0)
@@ -167,8 +167,8 @@ define float @maxnum_f32_1_maxnum_p0_val_fast(float %x) {
define float @minnum_f32_1_maxnum_p0_val_fmf1(float %x) {
; CHECK-LABEL: @minnum_f32_1_maxnum_p0_val_fmf1(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nnan float @llvm.maxnum.f32(float 0.0, float %x)
%z = call nnan ninf float @llvm.maxnum.f32(float %y, float 1.0)
@@ -177,8 +177,8 @@ define float @minnum_f32_1_maxnum_p0_val_fmf1(float %x) {
define float @minnum_f32_1_maxnum_p0_val_fmf2(float %x) {
; CHECK-LABEL: @minnum_f32_1_maxnum_p0_val_fmf2(
-; CHECK-NEXT: [[TMP1:%.*]] = call ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nnan ninf float @llvm.maxnum.f32(float 0.0, float %x)
%z = call ninf float @llvm.maxnum.f32(float %y, float 1.0)
@@ -187,8 +187,8 @@ define float @minnum_f32_1_maxnum_p0_val_fmf2(float %x) {
define float @minnum_f32_1_maxnum_p0_val_fmf3(float %x) {
; CHECK-LABEL: @minnum_f32_1_maxnum_p0_val_fmf3(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call ninf nnan float @llvm.maxnum.f32(float 0.0, float %x)
%z = call ninf nnan float @llvm.maxnum.f32(float %y, float 1.0)
@@ -197,8 +197,8 @@ define float @minnum_f32_1_maxnum_p0_val_fmf3(float %x) {
define float @maxnum_f32_p0_maxnum_val_n0(float %x) {
; CHECK-LABEL: @maxnum_f32_p0_maxnum_val_n0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maxnum.f32(float %x, float -0.0)
%z = call float @llvm.maxnum.f32(float %y, float 0.0)
@@ -207,8 +207,8 @@ define float @maxnum_f32_p0_maxnum_val_n0(float %x) {
define float @maxnum_f32_1_maxnum_p0_val(float %x) {
; CHECK-LABEL: @maxnum_f32_1_maxnum_p0_val(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.maxnum.f32(float 0.0, float %x)
%z = call float @llvm.maxnum.f32(float %y, float 1.0)
@@ -217,8 +217,8 @@ define float @maxnum_f32_1_maxnum_p0_val(float %x) {
define <2 x float> @maxnum_f32_1_maxnum_val_p0_val_v2f32(<2 x float> %x) {
; CHECK-LABEL: @maxnum_f32_1_maxnum_val_p0_val_v2f32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.maxnum.v2f32(<2 x float> [[X:%.*]], <2 x float> <float 1.000000e+00, float 1.000000e+00>)
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call <2 x float> @llvm.maxnum.v2f32(<2 x float> [[X:%.*]], <2 x float> <float 1.000000e+00, float 1.000000e+00>)
+; CHECK-NEXT: ret <2 x float> [[Z]]
;
%y = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %x, <2 x float> zeroinitializer)
%z = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %y, <2 x float><float 1.0, float 1.0>)
@@ -378,8 +378,8 @@ define float @unary_neg_neg_extra_use_x_and_y(float %x, float %y) {
define float @reduce_precision(float %x, float %y) {
; CHECK-LABEL: @reduce_precision(
-; CHECK-NEXT: [[MAXNUM:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MAXNUM]]
+; CHECK-NEXT: [[MAXNUM1:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MAXNUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -390,8 +390,8 @@ define float @reduce_precision(float %x, float %y) {
define float @reduce_precision_fmf(float %x, float %y) {
; CHECK-LABEL: @reduce_precision_fmf(
-; CHECK-NEXT: [[MAXNUM:%.*]] = call nnan float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MAXNUM]]
+; CHECK-NEXT: [[MAXNUM1:%.*]] = call nnan float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MAXNUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -436,8 +436,8 @@ define float @reduce_precision_multi_use_1(float %x, float %y) {
define float @negated_op(float %x) {
; CHECK-LABEL: @negated_op(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
+; CHECK-NEXT: ret float [[R]]
;
%negx = fneg float %x
%r = call float @llvm.maxnum.f32(float %negx, float %x)
@@ -446,8 +446,8 @@ define float @negated_op(float %x) {
define <2 x double> @negated_op_fmf_commute_vec(<2 x double> %x) {
; CHECK-LABEL: @negated_op_fmf_commute_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> [[X:%.*]])
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> [[X:%.*]])
+; CHECK-NEXT: ret <2 x double> [[R]]
;
%negx = fneg <2 x double> %x
%r = call nsz nnan ninf <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double> %negx)
diff --git a/llvm/test/Transforms/InstCombine/mem-gep-zidx.ll b/llvm/test/Transforms/InstCombine/mem-gep-zidx.ll
index 264f4dbc37313..f0580edd12073 100644
--- a/llvm/test/Transforms/InstCombine/mem-gep-zidx.ll
+++ b/llvm/test/Transforms/InstCombine/mem-gep-zidx.ll
@@ -22,7 +22,7 @@ define void @test2(i32 signext %x, i64 %v) #0 {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[P:%.*]] = alloca i64, align 8
; CHECK-NEXT: store i64 [[V:%.*]], ptr [[P]], align 8
-; CHECK-NEXT: call void @foo(ptr nonnull [[P]]) #1
+; CHECK-NEXT: call void @foo(ptr nonnull [[P]]) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret void
;
%p = alloca i64
diff --git a/llvm/test/Transforms/InstCombine/memccpy.ll b/llvm/test/Transforms/InstCombine/memccpy.ll
index f3714a99f320c..91a1e5cbc1fe5 100644
--- a/llvm/test/Transforms/InstCombine/memccpy.ll
+++ b/llvm/test/Transforms/InstCombine/memccpy.ll
@@ -11,8 +11,8 @@ declare ptr @memccpy(ptr, ptr, i32, i64)
define ptr @memccpy_to_memcpy(ptr %dst) {
; CHECK-LABEL: @memccpy_to_memcpy(
; CHECK-NEXT: store i64 8245940763182785896, ptr [[DST:%.*]], align 1
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
-; CHECK-NEXT: ret ptr [[TMP2]]
+; CHECK-NEXT: [[CALL:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
+; CHECK-NEXT: ret ptr [[CALL]]
;
%call = call ptr @memccpy(ptr %dst, ptr @hello, i32 114, i64 12) ; 114 is 'r'
ret ptr %call
@@ -21,8 +21,8 @@ define ptr @memccpy_to_memcpy(ptr %dst) {
define ptr @memccpy_to_memcpy2(ptr %dst) {
; CHECK-LABEL: @memccpy_to_memcpy2(
; CHECK-NEXT: store i64 8245940763182785896, ptr [[DST:%.*]], align 1
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
-; CHECK-NEXT: ret ptr [[TMP2]]
+; CHECK-NEXT: [[CALL:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
+; CHECK-NEXT: ret ptr [[CALL]]
;
%call = call ptr @memccpy(ptr %dst, ptr @hello, i32 114, i64 8); ; 114 is 'r'
ret ptr %call
@@ -122,8 +122,8 @@ define ptr @memccpy_to_memcpy8(ptr %dst) {
define ptr @memccpy_to_memcpy9(ptr %dst, i64 %n) {
; CHECK-LABEL: @memccpy_to_memcpy9(
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(12) [[DST:%.*]], ptr noundef nonnull align 1 dereferenceable(12) @StopCharAfterNulTerminator, i64 12, i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 12
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 12
+; CHECK-NEXT: ret ptr [[CALL]]
;
%call = call ptr @memccpy(ptr %dst, ptr @StopCharAfterNulTerminator, i32 120, i64 15) ; 120 is 'x'
ret ptr %call
@@ -132,8 +132,8 @@ define ptr @memccpy_to_memcpy9(ptr %dst, i64 %n) {
define ptr @memccpy_to_memcpy10(ptr %dst, i64 %n) {
; CHECK-LABEL: @memccpy_to_memcpy10(
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(11) [[DST:%.*]], ptr noundef nonnull align 1 dereferenceable(11) @StringWithEOF, i64 11, i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 11
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 11
+; CHECK-NEXT: ret ptr [[CALL]]
;
%call = call ptr @memccpy(ptr %dst, ptr @StringWithEOF, i32 255, i64 15)
ret ptr %call
@@ -142,8 +142,8 @@ define ptr @memccpy_to_memcpy10(ptr %dst, i64 %n) {
define ptr @memccpy_to_memcpy11(ptr %dst, i64 %n) {
; CHECK-LABEL: @memccpy_to_memcpy11(
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(11) [[DST:%.*]], ptr noundef nonnull align 1 dereferenceable(11) @StringWithEOF, i64 11, i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 11
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 11
+; CHECK-NEXT: ret ptr [[CALL]]
;
%call = call ptr @memccpy(ptr %dst, ptr @StringWithEOF, i32 -1, i64 15)
ret ptr %call
@@ -152,8 +152,8 @@ define ptr @memccpy_to_memcpy11(ptr %dst, i64 %n) {
define ptr @memccpy_to_memcpy12(ptr %dst, i64 %n) {
; CHECK-LABEL: @memccpy_to_memcpy12(
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(11) [[DST:%.*]], ptr noundef nonnull align 1 dereferenceable(11) @StringWithEOF, i64 11, i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 11
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[CALL:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 11
+; CHECK-NEXT: ret ptr [[CALL]]
;
%call = call ptr @memccpy(ptr %dst, ptr @StringWithEOF, i32 1023, i64 15)
ret ptr %call
diff --git a/llvm/test/Transforms/InstCombine/memchr-10.ll b/llvm/test/Transforms/InstCombine/memchr-10.ll
index e96508d386f8f..709a131d5c138 100644
--- a/llvm/test/Transforms/InstCombine/memchr-10.ll
+++ b/llvm/test/Transforms/InstCombine/memchr-10.ll
@@ -18,7 +18,7 @@ declare ptr @memchr(ptr, i32, i64)
define i1 @call_memchr_ap5_c_1_eq_a(i32 %c, i64 %n) {
; CHECK-LABEL: @call_memchr_ap5_c_1_eq_a(
-; CHECK-NEXT: ret i1
+; CHECK-NEXT: ret i1 poison
;
%pap5 = getelementptr [5 x i8], ptr @a5, i32 0, i32 5
%qap5 = getelementptr [5 x i8], ptr @a5, i32 1, i32 0
@@ -32,7 +32,7 @@ define i1 @call_memchr_ap5_c_1_eq_a(i32 %c, i64 %n) {
define i1 @call_memchr_ap5_c_5_eq_a(i32 %c, i64 %n) {
; CHECK-LABEL: @call_memchr_ap5_c_5_eq_a(
-; CHECK-NEXT: ret i1
+; CHECK-NEXT: ret i1 poison
;
%pap5 = getelementptr [5 x i8], ptr @a5, i32 0, i32 5
%qap5 = getelementptr [5 x i8], ptr @a5, i32 1, i32 0
diff --git a/llvm/test/Transforms/InstCombine/memchr-2.ll b/llvm/test/Transforms/InstCombine/memchr-2.ll
index 89ebcd21f5a27..22aae6edcf920 100644
--- a/llvm/test/Transforms/InstCombine/memchr-2.ll
+++ b/llvm/test/Transforms/InstCombine/memchr-2.ll
@@ -89,8 +89,8 @@ define ptr @fold_memchr_a123f45_500_9() {
define ptr @fold_a12345_3_n(i64 %n) {
; CHECK-LABEL: @fold_a12345_3_n(
; CHECK-NEXT: [[MEMCHR_CMP:%.*]] = icmp ult i64 [[N:%.*]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[MEMCHR_CMP]], ptr null, ptr getelementptr inbounds ([5 x i8], ptr @a12345, i64 0, i64 2)
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[MEMCHR_CMP]], ptr null, ptr getelementptr inbounds ([5 x i8], ptr @a12345, i64 0, i64 2)
+; CHECK-NEXT: ret ptr [[RES]]
;
%res = call ptr @memchr(ptr @a12345, i32 3, i64 %n)
@@ -104,8 +104,8 @@ define ptr @fold_a12345_3_n(i64 %n) {
define ptr @fold_a12345_259_n(i64 %n) {
; CHECK-LABEL: @fold_a12345_259_n(
; CHECK-NEXT: [[MEMCHR_CMP:%.*]] = icmp ult i64 [[N:%.*]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[MEMCHR_CMP]], ptr null, ptr getelementptr inbounds ([5 x i8], ptr @a12345, i64 0, i64 2)
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[MEMCHR_CMP]], ptr null, ptr getelementptr inbounds ([5 x i8], ptr @a12345, i64 0, i64 2)
+; CHECK-NEXT: ret ptr [[RES]]
;
%res = call ptr @memchr(ptr @a12345, i32 259, i64 %n)
diff --git a/llvm/test/Transforms/InstCombine/memcmp-5.ll b/llvm/test/Transforms/InstCombine/memcmp-5.ll
index d857b01836cad..591131cdb7907 100644
--- a/llvm/test/Transforms/InstCombine/memcmp-5.ll
+++ b/llvm/test/Transforms/InstCombine/memcmp-5.ll
@@ -19,23 +19,23 @@ define void @fold_memcmp_a_b_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_memcmp_a_b_n(
; CHECK-NEXT: store i32 0, ptr [[PCMP:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[N:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: [[C0_1:%.*]] = sext i1 [[TMP1]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[S0_1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_2:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S0_2:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S0_2]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[C0_2]], ptr [[S0_2]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_3:%.*]] = sext i1 [[TMP3]] to i32
; CHECK-NEXT: [[S0_3:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[S0_3]], align 4
+; CHECK-NEXT: store i32 [[C0_3]], ptr [[S0_3]], align 4
; CHECK-NEXT: [[S0_4:%.*]] = getelementptr i32, ptr [[PCMP]], i64 4
; CHECK-NEXT: store i32 0, ptr [[S0_4]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_5:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[S0_5:%.*]] = getelementptr i32, ptr [[PCMP]], i64 5
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[S0_5]], align 4
+; CHECK-NEXT: store i32 [[C0_5]], ptr [[S0_5]], align 4
; CHECK-NEXT: ret void
;
@@ -103,28 +103,28 @@ define void @call_memcmp_a_ax_n(ptr %pcmp, i64 %n) {
define void @fold_memcmp_a_c_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_memcmp_a_c_n(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[N:%.*]], 7
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[PCMP:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: [[C0_0:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: store i32 [[C0_0]], ptr [[PCMP:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_1:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S0_1]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_2:%.*]] = sext i1 [[TMP3]] to i32
; CHECK-NEXT: [[S0_2:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[S0_2]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i32
+; CHECK-NEXT: store i32 [[C0_2]], ptr [[S0_2]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_3:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[S0_3:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[S0_3]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 3
-; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i32
+; CHECK-NEXT: store i32 [[C0_3]], ptr [[S0_3]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[N]], 3
+; CHECK-NEXT: [[C0_4:%.*]] = sext i1 [[TMP5]] to i32
; CHECK-NEXT: [[S0_4:%.*]] = getelementptr i32, ptr [[PCMP]], i64 4
-; CHECK-NEXT: store i32 [[TMP10]], ptr [[S0_4]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[N]], 3
-; CHECK-NEXT: [[TMP12:%.*]] = sext i1 [[TMP11]] to i32
+; CHECK-NEXT: store i32 [[C0_4]], ptr [[S0_4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[N]], 3
+; CHECK-NEXT: [[C0_5:%.*]] = sext i1 [[TMP6]] to i32
; CHECK-NEXT: [[S0_5:%.*]] = getelementptr i32, ptr [[PCMP]], i64 5
-; CHECK-NEXT: store i32 [[TMP12]], ptr [[S0_5]], align 4
+; CHECK-NEXT: store i32 [[C0_5]], ptr [[S0_5]], align 4
; CHECK-NEXT: ret void
;
@@ -174,12 +174,12 @@ define void @fold_memcmp_a_c_n(ptr %pcmp, i64 %n) {
define void @fold_memcmp_a_d_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_memcmp_a_d_n(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[N:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[PCMP:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: [[C0_0:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: store i32 [[C0_0]], ptr [[PCMP:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_1:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S0_1]], align 4
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
; CHECK-NEXT: [[S1_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
; CHECK-NEXT: store i32 0, ptr [[S1_1]], align 4
; CHECK-NEXT: [[S6_6:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
diff --git a/llvm/test/Transforms/InstCombine/memcmp-6.ll b/llvm/test/Transforms/InstCombine/memcmp-6.ll
index cf95c7bac5692..e5e304895135c 100644
--- a/llvm/test/Transforms/InstCombine/memcmp-6.ll
+++ b/llvm/test/Transforms/InstCombine/memcmp-6.ll
@@ -59,20 +59,20 @@ define void @fold_memcmp_cst_cst(ptr %pcmp) {
define void @fold_memcmp_cst_var(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_memcmp_cst_var(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[N:%.*]], 6
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[PCMP:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[N]], 6
-; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT: [[CA0_B0:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: store i32 [[CA0_B0]], ptr [[PCMP:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[N]], 6
+; CHECK-NEXT: [[CB0_A0:%.*]] = zext i1 [[TMP2]] to i32
; CHECK-NEXT: [[SB0_A0:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[SB0_A0]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[CB0_A0]], ptr [[SB0_A0]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[CA6_B6:%.*]] = sext i1 [[TMP3]] to i32
; CHECK-NEXT: [[SA6_B6:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[SA6_B6]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
+; CHECK-NEXT: store i32 [[CA6_B6]], ptr [[SA6_B6]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[CB6_A6:%.*]] = zext i1 [[TMP4]] to i32
; CHECK-NEXT: [[SB6_A6:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[SB6_A6]], align 4
+; CHECK-NEXT: store i32 [[CB6_A6]], ptr [[SB6_A6]], align 4
; CHECK-NEXT: ret void
;
%p6 = getelementptr [7 x i8], ptr @a, i64 0, i64 6
diff --git a/llvm/test/Transforms/InstCombine/memcpy-to-load.ll b/llvm/test/Transforms/InstCombine/memcpy-to-load.ll
index 4ee6ed2220241..2f13394b5e477 100644
--- a/llvm/test/Transforms/InstCombine/memcpy-to-load.ll
+++ b/llvm/test/Transforms/InstCombine/memcpy-to-load.ll
@@ -20,8 +20,8 @@ define void @copy_1_byte(ptr %d, ptr %s) {
define void @copy_2_bytes(ptr %d, ptr %s) {
; CHECK-LABEL: @copy_2_bytes(
-; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[S:%.*]], align 1
-; CHECK-NEXT: store i16 [[TMP3]], ptr [[D:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[S:%.*]], align 1
+; CHECK-NEXT: store i16 [[TMP1]], ptr [[D:%.*]], align 1
; CHECK-NEXT: ret void
;
call void @llvm.memcpy.p0.p0.i32(ptr %d, ptr %s, i32 2, i1 false)
@@ -41,8 +41,8 @@ define void @copy_3_bytes(ptr %d, ptr %s) {
define void @copy_4_bytes(ptr %d, ptr %s) {
; CHECK-LABEL: @copy_4_bytes(
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[S:%.*]], align 1
-; CHECK-NEXT: store i32 [[TMP3]], ptr [[D:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[S:%.*]], align 1
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[D:%.*]], align 1
; CHECK-NEXT: ret void
;
call void @llvm.memcpy.p0.p0.i32(ptr %d, ptr %s, i32 4, i1 false)
@@ -62,8 +62,8 @@ define void @copy_5_bytes(ptr %d, ptr %s) {
define void @copy_8_bytes(ptr %d, ptr %s) {
; CHECK-LABEL: @copy_8_bytes(
-; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[S:%.*]], align 1
-; CHECK-NEXT: store i64 [[TMP3]], ptr [[D:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[S:%.*]], align 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[D:%.*]], align 1
; CHECK-NEXT: ret void
;
call void @llvm.memcpy.p0.p0.i32(ptr %d, ptr %s, i32 8, i1 false)
diff --git a/llvm/test/Transforms/InstCombine/mempcpy.ll b/llvm/test/Transforms/InstCombine/mempcpy.ll
index 7f1e856a5a40c..c996758a919d9 100644
--- a/llvm/test/Transforms/InstCombine/mempcpy.ll
+++ b/llvm/test/Transforms/InstCombine/mempcpy.ll
@@ -3,9 +3,9 @@
define ptr @memcpy_nonconst_n(ptr %d, ptr nocapture readonly %s, i64 %n) {
; CHECK-LABEL: @memcpy_nonconst_n(
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[D:%.*]], ptr align 1 [[S:%.*]], i64 [[N:%.*]], i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 [[N]]
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[D:%.*]], ptr align 1 [[S:%.*]], i64 [[N:%.*]], i1 false)
+; CHECK-NEXT: [[R:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 [[N]]
+; CHECK-NEXT: ret ptr [[R]]
;
%r = tail call ptr @mempcpy(ptr %d, ptr %s, i64 %n)
ret ptr %r
@@ -13,9 +13,9 @@ define ptr @memcpy_nonconst_n(ptr %d, ptr nocapture readonly %s, i64 %n) {
define ptr @memcpy_nonconst_n_copy_attrs(ptr %d, ptr nocapture readonly %s, i64 %n) {
; CHECK-LABEL: @memcpy_nonconst_n_copy_attrs(
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 dereferenceable(16) [[D:%.*]], ptr align 1 [[S:%.*]], i64 [[N:%.*]], i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 [[N]]
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 dereferenceable(16) [[D:%.*]], ptr align 1 [[S:%.*]], i64 [[N:%.*]], i1 false)
+; CHECK-NEXT: [[R:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 [[N]]
+; CHECK-NEXT: ret ptr [[R]]
;
%r = tail call ptr @mempcpy(ptr dereferenceable(16) %d, ptr %s, i64 %n)
ret ptr %r
@@ -32,10 +32,10 @@ define void @memcpy_nonconst_n_unused_retval(ptr %d, ptr nocapture readonly %s,
define ptr @memcpy_small_const_n(ptr %d, ptr nocapture readonly %s) {
; CHECK-LABEL: @memcpy_small_const_n(
-; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[S:%.*]], align 1
-; CHECK-NEXT: store i64 [[TMP3]], ptr [[D:%.*]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 8
-; CHECK-NEXT: ret ptr [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[S:%.*]], align 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[D:%.*]], align 1
+; CHECK-NEXT: [[R:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 8
+; CHECK-NEXT: ret ptr [[R]]
;
%r = tail call ptr @mempcpy(ptr %d, ptr %s, i64 8)
ret ptr %r
@@ -43,9 +43,9 @@ define ptr @memcpy_small_const_n(ptr %d, ptr nocapture readonly %s) {
define ptr @memcpy_big_const_n(ptr %d, ptr nocapture readonly %s) {
; CHECK-LABEL: @memcpy_big_const_n(
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(1024) [[D:%.*]], ptr noundef nonnull align 1 dereferenceable(1024) [[S:%.*]], i64 1024, i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 1024
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(1024) [[D:%.*]], ptr noundef nonnull align 1 dereferenceable(1024) [[S:%.*]], i64 1024, i1 false)
+; CHECK-NEXT: [[R:%.*]] = getelementptr inbounds i8, ptr [[D]], i64 1024
+; CHECK-NEXT: ret ptr [[R]]
;
%r = tail call ptr @mempcpy(ptr %d, ptr %s, i64 1024)
ret ptr %r
@@ -64,8 +64,8 @@ define i32 @PR48810() {
define ptr @memcpy_no_simplify1(ptr %d, ptr nocapture readonly %s, i64 %n) {
; CHECK-LABEL: @memcpy_no_simplify1(
-; CHECK-NEXT: %r = musttail call ptr @mempcpy(ptr %d, ptr %s, i64 %n)
-; CHECK-NEXT: ret ptr %r
+; CHECK-NEXT: [[R:%.*]] = musttail call ptr @mempcpy(ptr [[D:%.*]], ptr [[S:%.*]], i64 [[N:%.*]])
+; CHECK-NEXT: ret ptr [[R]]
;
%r = musttail call ptr @mempcpy(ptr %d, ptr %s, i64 %n)
ret ptr %r
diff --git a/llvm/test/Transforms/InstCombine/memrchr-7.ll b/llvm/test/Transforms/InstCombine/memrchr-7.ll
index 3e92a0db9c093..686e1d5bc4e91 100644
--- a/llvm/test/Transforms/InstCombine/memrchr-7.ll
+++ b/llvm/test/Transforms/InstCombine/memrchr-7.ll
@@ -18,7 +18,7 @@ declare ptr @memrchr(ptr, i32, i64)
define i1 @call_memrchr_ap5_c_1_eq_a(i32 %c, i64 %n) {
; CHECK-LABEL: @call_memrchr_ap5_c_1_eq_a(
-; CHECK-NEXT: ret i1
+; CHECK-NEXT: ret i1 poison
;
%pap5 = getelementptr [5 x i8], ptr @a5, i32 0, i32 5
%qap5 = getelementptr [5 x i8], ptr @a5, i32 1, i32 0
@@ -32,7 +32,7 @@ define i1 @call_memrchr_ap5_c_1_eq_a(i32 %c, i64 %n) {
define i1 @call_memrchr_ap5_c_5_eq_a(i32 %c, i64 %n) {
; CHECK-LABEL: @call_memrchr_ap5_c_5_eq_a(
-; CHECK-NEXT: ret i1
+; CHECK-NEXT: ret i1 false
;
%pap5 = getelementptr [5 x i8], ptr @a5, i32 0, i32 5
%qap5 = getelementptr [5 x i8], ptr @a5, i32 1, i32 0
diff --git a/llvm/test/Transforms/InstCombine/merge-icmp.ll b/llvm/test/Transforms/InstCombine/merge-icmp.ll
index 362d5cb321a0a..4e8ef07dba04c 100644
--- a/llvm/test/Transforms/InstCombine/merge-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/merge-icmp.ll
@@ -8,8 +8,8 @@ declare void @use.i16(i16)
define i1 @and_test1(ptr %x) {
; CHECK-LABEL: @and_test1(
; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[LOAD]], 17791
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i16 [[LOAD]], 17791
+; CHECK-NEXT: ret i1 [[OR]]
;
%load = load i16, ptr %x, align 4
%trunc = trunc i16 %load to i8
@@ -23,8 +23,8 @@ define i1 @and_test1(ptr %x) {
define i1 @and_test1_logical(ptr %x) {
; CHECK-LABEL: @and_test1_logical(
; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[LOAD]], 17791
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i16 [[LOAD]], 17791
+; CHECK-NEXT: ret i1 [[OR]]
;
%load = load i16, ptr %x, align 4
%trunc = trunc i16 %load to i8
@@ -38,8 +38,8 @@ define i1 @and_test1_logical(ptr %x) {
define <2 x i1> @and_test1_vector(ptr %x) {
; CHECK-LABEL: @and_test1_vector(
; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i16>, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i16> [[LOAD]], <i16 17791, i16 17791>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i16> [[LOAD]], <i16 17791, i16 17791>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%load = load <2 x i16>, ptr %x, align 4
%trunc = trunc <2 x i16> %load to <2 x i8>
@@ -53,8 +53,8 @@ define <2 x i1> @and_test1_vector(ptr %x) {
define i1 @and_test2(ptr %x) {
; CHECK-LABEL: @and_test2(
; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[LOAD]], 32581
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i16 [[LOAD]], 32581
+; CHECK-NEXT: ret i1 [[OR]]
;
%load = load i16, ptr %x, align 4
%and = and i16 %load, -256
@@ -68,8 +68,8 @@ define i1 @and_test2(ptr %x) {
define i1 @and_test2_logical(ptr %x) {
; CHECK-LABEL: @and_test2_logical(
; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[LOAD]], 32581
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i16 [[LOAD]], 32581
+; CHECK-NEXT: ret i1 [[OR]]
;
%load = load i16, ptr %x, align 4
%and = and i16 %load, -256
@@ -83,8 +83,8 @@ define i1 @and_test2_logical(ptr %x) {
define <2 x i1> @and_test2_vector(ptr %x) {
; CHECK-LABEL: @and_test2_vector(
; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i16>, ptr [[X:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i16> [[LOAD]], <i16 32581, i16 32581>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i16> [[LOAD]], <i16 32581, i16 32581>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%load = load <2 x i16>, ptr %x, align 4
%and = and <2 x i16> %load, <i16 -256, i16 -256>
@@ -97,8 +97,8 @@ define <2 x i1> @and_test2_vector(ptr %x) {
define i1 @or_basic(i16 %load) {
; CHECK-LABEL: @or_basic(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i16 [[LOAD:%.*]], 17791
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i16 [[LOAD:%.*]], 17791
+; CHECK-NEXT: ret i1 [[OR]]
;
%trunc = trunc i16 %load to i8
%cmp1 = icmp ne i8 %trunc, 127
@@ -110,8 +110,8 @@ define i1 @or_basic(i16 %load) {
define i1 @or_basic_commuted(i16 %load) {
; CHECK-LABEL: @or_basic_commuted(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i16 [[LOAD:%.*]], 32581
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i16 [[LOAD:%.*]], 32581
+; CHECK-NEXT: ret i1 [[OR]]
;
%and = and i16 %load, -256
%cmp1 = icmp ne i16 %and, 32512
@@ -123,8 +123,8 @@ define i1 @or_basic_commuted(i16 %load) {
define <2 x i1> @or_vector(<2 x i16> %load) {
; CHECK-LABEL: @or_vector(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i16> [[LOAD:%.*]], <i16 17791, i16 17791>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i16> [[LOAD:%.*]], <i16 17791, i16 17791>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%trunc = trunc <2 x i16> %load to <2 x i8>
%cmp1 = icmp ne <2 x i8> %trunc, <i8 127, i8 127>
@@ -137,8 +137,8 @@ define <2 x i1> @or_vector(<2 x i16> %load) {
define i1 @or_nontrivial_mask1(i16 %load) {
; CHECK-LABEL: @or_nontrivial_mask1(
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[LOAD:%.*]], 4095
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 1407
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i16 [[TMP1]], 1407
+; CHECK-NEXT: ret i1 [[OR]]
;
%trunc = trunc i16 %load to i8
%cmp1 = icmp ne i8 %trunc, 127
@@ -151,8 +151,8 @@ define i1 @or_nontrivial_mask1(i16 %load) {
define i1 @or_nontrivial_mask2(i16 %load) {
; CHECK-LABEL: @or_nontrivial_mask2(
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[LOAD:%.*]], -3841
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 20607
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i16 [[TMP1]], 20607
+; CHECK-NEXT: ret i1 [[OR]]
;
%trunc = trunc i16 %load to i8
%cmp1 = icmp ne i8 %trunc, 127
@@ -205,8 +205,8 @@ define i1 @or_extra_use3(i16 %load) {
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i16 [[LOAD:%.*]] to i8
; CHECK-NEXT: call void @use.i8(i8 [[TRUNC]])
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[LOAD]], -3841
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 20607
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i16 [[TMP1]], 20607
+; CHECK-NEXT: ret i1 [[OR]]
;
%trunc = trunc i16 %load to i8
call void @use.i8(i8 %trunc)
@@ -222,8 +222,8 @@ define i1 @or_extra_use4(i16 %load) {
; CHECK-NEXT: [[AND:%.*]] = and i16 [[LOAD:%.*]], -4096
; CHECK-NEXT: call void @use.i16(i16 [[AND]])
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[LOAD]], -3841
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 20607
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i16 [[TMP1]], 20607
+; CHECK-NEXT: ret i1 [[OR]]
;
%trunc = trunc i16 %load to i8
%cmp1 = icmp ne i8 %trunc, 127
diff --git a/llvm/test/Transforms/InstCombine/min-positive.ll b/llvm/test/Transforms/InstCombine/min-positive.ll
index db8394fa90a67..1fb212b738725 100644
--- a/llvm/test/Transforms/InstCombine/min-positive.ll
+++ b/llvm/test/Transforms/InstCombine/min-positive.ll
@@ -84,8 +84,8 @@ define <2 x i1> @smin_commute_vec_undef_elts(<2 x i32> %x, <2 x i32> %other) {
define i1 @maybe_not_positive(i32 %other) {
; CHECK-LABEL: @maybe_not_positive(
; CHECK-NEXT: [[POSITIVE:%.*]] = load i32, ptr @g, align 4, !range [[RNG0:![0-9]+]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[POSITIVE]], i32 [[OTHER:%.*]])
-; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 [[TMP1]], 0
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.smin.i32(i32 [[POSITIVE]], i32 [[OTHER:%.*]])
+; CHECK-NEXT: [[TEST:%.*]] = icmp sgt i32 [[SEL]], 0
; CHECK-NEXT: ret i1 [[TEST]]
;
%positive = load i32, ptr @g, !range !{i32 0, i32 2048}
@@ -98,8 +98,8 @@ define i1 @maybe_not_positive(i32 %other) {
define <2 x i1> @maybe_not_positive_vec(<2 x i32> %x, <2 x i32> %other) {
; CHECK-LABEL: @maybe_not_positive_vec(
; CHECK-NEXT: [[NOTNEG:%.*]] = and <2 x i32> [[X:%.*]], <i32 7, i32 7>
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[NOTNEG]], <2 x i32> [[OTHER:%.*]])
-; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[SEL:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[NOTNEG]], <2 x i32> [[OTHER:%.*]])
+; CHECK-NEXT: [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[TEST]]
;
%notneg = and <2 x i32> %x, <i32 7, i32 7>
diff --git a/llvm/test/Transforms/InstCombine/minimum.ll b/llvm/test/Transforms/InstCombine/minimum.ll
index 8abd6815de275..71e6fec245c6b 100644
--- a/llvm/test/Transforms/InstCombine/minimum.ll
+++ b/llvm/test/Transforms/InstCombine/minimum.ll
@@ -149,8 +149,8 @@ define float @minimum_f32_val_nan(float %x) {
define float @minimum_f32_1_minimum_val_p0(float %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_val_p0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minimum.f32(float %x, float 0.0)
%z = call float @llvm.minimum.f32(float %y, float 1.0)
@@ -159,8 +159,8 @@ define float @minimum_f32_1_minimum_val_p0(float %x) {
define float @minimum_f32_1_minimum_p0_val_fast(float %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fast(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minimum.f32(float 0.0, float %x)
%z = call fast float @llvm.minimum.f32(float %y, float 1.0)
@@ -169,8 +169,8 @@ define float @minimum_f32_1_minimum_p0_val_fast(float %x) {
define float @minimum_f32_1_minimum_p0_val_fmf1(float %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fmf1(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minimum.f32(float 0.0, float %x)
%z = call nnan ninf float @llvm.minimum.f32(float %y, float 1.0)
@@ -179,8 +179,8 @@ define float @minimum_f32_1_minimum_p0_val_fmf1(float %x) {
define float @minimum_f32_1_minimum_p0_val_fmf2(float %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fmf2(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nnan ninf float @llvm.minimum.f32(float 0.0, float %x)
%z = call float @llvm.minimum.f32(float %y, float 1.0)
@@ -189,8 +189,8 @@ define float @minimum_f32_1_minimum_p0_val_fmf2(float %x) {
define float @minimum_f32_1_minimum_p0_val_fmf3(float %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fmf3(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan ninf float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nnan ninf float @llvm.minimum.f32(float 0.0, float %x)
%z = call nnan ninf float @llvm.minimum.f32(float %y, float 1.0)
@@ -199,8 +199,8 @@ define float @minimum_f32_1_minimum_p0_val_fmf3(float %x) {
define float @minimum_f32_p0_minimum_val_n0(float %x) {
; CHECK-LABEL: @minimum_f32_p0_minimum_val_n0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float -0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float -0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minimum.f32(float %x, float -0.0)
%z = call float @llvm.minimum.f32(float %y, float 0.0)
@@ -209,8 +209,8 @@ define float @minimum_f32_p0_minimum_val_n0(float %x) {
define float @minimum_f32_1_minimum_p0_val(float %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_p0_val(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minimum.f32(float 0.0, float %x)
%z = call float @llvm.minimum.f32(float %y, float 1.0)
@@ -219,8 +219,8 @@ define float @minimum_f32_1_minimum_p0_val(float %x) {
define <2 x float> @minimum_f32_1_minimum_val_p0_val_v2f32(<2 x float> %x) {
; CHECK-LABEL: @minimum_f32_1_minimum_val_p0_val_v2f32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.minimum.v2f32(<2 x float> [[X:%.*]], <2 x float> zeroinitializer)
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call <2 x float> @llvm.minimum.v2f32(<2 x float> [[X:%.*]], <2 x float> zeroinitializer)
+; CHECK-NEXT: ret <2 x float> [[Z]]
;
%y = call <2 x float> @llvm.minimum.v2f32(<2 x float> %x, <2 x float> zeroinitializer)
%z = call <2 x float> @llvm.minimum.v2f32(<2 x float> %y, <2 x float><float 1.0, float 1.0>)
@@ -415,8 +415,8 @@ define double @unary_neg_neg_extra_use_x_and_y(double %x, double %y) {
define float @reduce_precision(float %x, float %y) {
; CHECK-LABEL: @reduce_precision(
-; CHECK-NEXT: [[MINIMUM:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MINIMUM]]
+; CHECK-NEXT: [[MINIMUM1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MINIMUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -427,8 +427,8 @@ define float @reduce_precision(float %x, float %y) {
define float @reduce_precision_fmf(float %x, float %y) {
; CHECK-LABEL: @reduce_precision_fmf(
-; CHECK-NEXT: [[MINIMUM:%.*]] = call nnan float @llvm.minimum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MINIMUM]]
+; CHECK-NEXT: [[MINIMUM1:%.*]] = call nnan float @llvm.minimum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MINIMUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -440,8 +440,8 @@ define float @reduce_precision_fmf(float %x, float %y) {
define float @negated_op(float %x) {
; CHECK-LABEL: @negated_op(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = fneg float [[TMP1]]
+; CHECK-NEXT: ret float [[R]]
;
%negx = fneg float %x
%r = call float @llvm.minimum.f32(float %x, float %negx)
@@ -451,8 +451,8 @@ define float @negated_op(float %x) {
define <2 x double> @negated_op_fmf_commute_vec(<2 x double> %x) {
; CHECK-LABEL: @negated_op_fmf_commute_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> [[X:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fneg nnan ninf nsz <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = fneg nnan ninf nsz <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[R]]
;
%negx = fneg <2 x double> %x
%r = call nsz nnan ninf <2 x double> @llvm.minimum.v2f64(<2 x double> %negx, <2 x double> %x)
diff --git a/llvm/test/Transforms/InstCombine/minmax-demandbits.ll b/llvm/test/Transforms/InstCombine/minmax-demandbits.ll
index 20919ef584d14..99ac4a247e83c 100644
--- a/llvm/test/Transforms/InstCombine/minmax-demandbits.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-demandbits.ll
@@ -26,8 +26,8 @@ define i32 @and_umax_muchless(i32 %A) {
define i32 @and_umax_more(i32 %A) {
; CHECK-LABEL: @and_umax_more(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 32)
-; CHECK-NEXT: [[X:%.*]] = and i32 [[TMP1]], -32
+; CHECK-NEXT: [[L1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 32)
+; CHECK-NEXT: [[X:%.*]] = and i32 [[L1]], -32
; CHECK-NEXT: ret i32 [[X]]
;
%l0 = icmp ugt i32 32, %A
@@ -117,8 +117,8 @@ define i8 @t_2_63_or(i8 %A) {
define i8 @f_1_1(i8 %A) {
; CHECK-LABEL: @f_1_1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 1)
-; CHECK-NEXT: [[X:%.*]] = and i8 [[TMP1]], 1
+; CHECK-NEXT: [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 1)
+; CHECK-NEXT: [[X:%.*]] = and i8 [[L1]], 1
; CHECK-NEXT: ret i8 [[X]]
;
%l2 = icmp ugt i8 %A, 1
@@ -129,8 +129,8 @@ define i8 @f_1_1(i8 %A) {
define i8 @f_32_32(i8 %A) {
; CHECK-LABEL: @f_32_32(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 32)
-; CHECK-NEXT: [[X:%.*]] = and i8 [[TMP1]], -32
+; CHECK-NEXT: [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 32)
+; CHECK-NEXT: [[X:%.*]] = and i8 [[L1]], -32
; CHECK-NEXT: ret i8 [[X]]
;
%l2 = icmp ugt i8 %A, 32
@@ -141,8 +141,8 @@ define i8 @f_32_32(i8 %A) {
define i8 @f_191_192(i8 %A) {
; CHECK-LABEL: @f_191_192(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 -65)
-; CHECK-NEXT: [[X:%.*]] = and i8 [[TMP1]], -64
+; CHECK-NEXT: [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 -65)
+; CHECK-NEXT: [[X:%.*]] = and i8 [[L1]], -64
; CHECK-NEXT: ret i8 [[X]]
;
%l2 = icmp ugt i8 %A, 191
@@ -153,8 +153,8 @@ define i8 @f_191_192(i8 %A) {
define i8 @f_10_1(i8 %A) {
; CHECK-LABEL: @f_10_1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 10)
-; CHECK-NEXT: [[X:%.*]] = and i8 [[TMP1]], 1
+; CHECK-NEXT: [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 10)
+; CHECK-NEXT: [[X:%.*]] = and i8 [[L1]], 1
; CHECK-NEXT: ret i8 [[X]]
;
%l2 = icmp ugt i8 %A, 10
@@ -218,8 +218,8 @@ define i8 @and_min_7_8(i8 %A) {
define i8 @and_min_7_9(i8 %A) {
; CHECK-LABEL: @and_min_7_9(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[A:%.*]], i8 -9)
-; CHECK-NEXT: [[R:%.*]] = and i8 [[TMP1]], -8
+; CHECK-NEXT: [[MIN:%.*]] = call i8 @llvm.umin.i8(i8 [[A:%.*]], i8 -9)
+; CHECK-NEXT: [[R:%.*]] = and i8 [[MIN]], -8
; CHECK-NEXT: ret i8 [[R]]
;
%l2 = icmp ult i8 %A, -9
diff --git a/llvm/test/Transforms/InstCombine/minmax-fp.ll b/llvm/test/Transforms/InstCombine/minmax-fp.ll
index edb0f341c8152..d3c506d0dc2ad 100644
--- a/llvm/test/Transforms/InstCombine/minmax-fp.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-fp.ll
@@ -165,9 +165,9 @@ define i8 @t9(float %a) {
define i8 @t11(float %a, float %b) {
; CHECK-LABEL: @t11(
; CHECK-NEXT: [[DOTINV:%.*]] = fcmp fast oge float [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select fast i1 [[DOTINV]], float [[A]], float [[B]]
-; CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i8
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[DOTV:%.*]] = select fast i1 [[DOTINV]], float [[A]], float [[B]]
+; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[DOTV]] to i8
+; CHECK-NEXT: ret i8 [[TMP1]]
;
%1 = fcmp fast ult float %b, %a
%2 = fptosi float %a to i8
@@ -180,9 +180,9 @@ define i8 @t11(float %a, float %b) {
define i8 @t12(float %a, float %b) {
; CHECK-LABEL: @t12(
; CHECK-NEXT: [[DOTINV:%.*]] = fcmp nnan oge float [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select nnan i1 [[DOTINV]], float [[A]], float [[B]]
-; CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i8
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[DOTV:%.*]] = select nnan i1 [[DOTINV]], float [[A]], float [[B]]
+; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[DOTV]] to i8
+; CHECK-NEXT: ret i8 [[TMP1]]
;
%1 = fcmp nnan ult float %b, %a
%2 = fptosi float %a to i8
@@ -260,9 +260,9 @@ define double @t16(i32 %x) {
define double @t17(i32 %x) {
; CHECK-LABEL: @t17(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[TMP1]] to double
-; CHECK-NEXT: ret double [[TMP2]]
+; CHECK-NEXT: [[SEL1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 2)
+; CHECK-NEXT: [[SEL:%.*]] = sitofp i32 [[SEL1]] to double
+; CHECK-NEXT: ret double [[SEL]]
;
%cmp = icmp sgt i32 %x, 2
%cst = sitofp i32 %x to double
@@ -287,8 +287,8 @@ define float @fneg_fmax(float %x, float %y) {
define <2 x float> @fsub_fmax(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: @fsub_fmax(
; CHECK-NEXT: [[COND_INV:%.*]] = fcmp nnan nsz ogt <2 x float> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select nnan nsz <2 x i1> [[COND_INV]], <2 x float> [[Y]], <2 x float> [[X]]
-; CHECK-NEXT: [[MAX:%.*]] = fneg <2 x float> [[TMP1]]
+; CHECK-NEXT: [[MAX_V:%.*]] = select nnan nsz <2 x i1> [[COND_INV]], <2 x float> [[Y]], <2 x float> [[X]]
+; CHECK-NEXT: [[MAX:%.*]] = fneg <2 x float> [[MAX_V]]
; CHECK-NEXT: ret <2 x float> [[MAX]]
;
%n1 = fsub <2 x float> <float -0.0, float -0.0>, %x
@@ -315,8 +315,8 @@ define <2 x double> @fsub_fmin(<2 x double> %x, <2 x double> %y) {
define double @fneg_fmin(double %x, double %y) {
; CHECK-LABEL: @fneg_fmin(
; CHECK-NEXT: [[COND_INV:%.*]] = fcmp nnan nsz olt double [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select nnan nsz i1 [[COND_INV]], double [[Y]], double [[X]]
-; CHECK-NEXT: [[MAX:%.*]] = fneg double [[TMP1]]
+; CHECK-NEXT: [[MAX_V:%.*]] = select nnan nsz i1 [[COND_INV]], double [[Y]], double [[X]]
+; CHECK-NEXT: [[MAX:%.*]] = fneg double [[MAX_V]]
; CHECK-NEXT: ret double [[MAX]]
;
%n1 = fneg double %x
@@ -328,8 +328,8 @@ define double @fneg_fmin(double %x, double %y) {
define float @maxnum_ogt_fmf_on_select(float %a, float %b) {
; CHECK-LABEL: @maxnum_ogt_fmf_on_select(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[F:%.*]] = call nnan nsz float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[F]]
;
%cond = fcmp ogt float %a, %b
%f = select nnan nsz i1 %cond, float %a, float %b
@@ -338,8 +338,8 @@ define float @maxnum_ogt_fmf_on_select(float %a, float %b) {
define <2 x float> @maxnum_oge_fmf_on_select(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: @maxnum_oge_fmf_on_select(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz <2 x float> @llvm.maxnum.v2f32(<2 x float> [[A:%.*]], <2 x float> [[B:%.*]])
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[F:%.*]] = call nnan ninf nsz <2 x float> @llvm.maxnum.v2f32(<2 x float> [[A:%.*]], <2 x float> [[B:%.*]])
+; CHECK-NEXT: ret <2 x float> [[F]]
;
%cond = fcmp oge <2 x float> %a, %b
%f = select ninf nnan nsz <2 x i1> %cond, <2 x float> %a, <2 x float> %b
@@ -392,8 +392,8 @@ define float @maxnum_no_nnan(float %a, float %b) {
define float @minnum_olt_fmf_on_select(float %a, float %b) {
; CHECK-LABEL: @minnum_olt_fmf_on_select(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan nsz float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[F:%.*]] = call nnan nsz float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[F]]
;
%cond = fcmp olt float %a, %b
%f = select nnan nsz i1 %cond, float %a, float %b
@@ -402,8 +402,8 @@ define float @minnum_olt_fmf_on_select(float %a, float %b) {
define <2 x float> @minnum_ole_fmf_on_select(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: @minnum_ole_fmf_on_select(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz <2 x float> @llvm.minnum.v2f32(<2 x float> [[A:%.*]], <2 x float> [[B:%.*]])
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[F:%.*]] = call nnan ninf nsz <2 x float> @llvm.minnum.v2f32(<2 x float> [[A:%.*]], <2 x float> [[B:%.*]])
+; CHECK-NEXT: ret <2 x float> [[F]]
;
%cond = fcmp ole <2 x float> %a, %b
%f = select ninf nnan nsz <2 x i1> %cond, <2 x float> %a, <2 x float> %b
diff --git a/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll b/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
index e4d852a3d62d3..b2a559ea63f64 100644
--- a/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
@@ -584,8 +584,8 @@ define i8 @not_smax_of_nots(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use(i8 [[NOTX]])
; CHECK-NEXT: [[NOTY:%.*]] = xor i8 [[Y:%.*]], -1
; CHECK-NEXT: call void @use(i8 [[NOTY]])
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smin.i8(i8 [[X]], i8 [[Y]])
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[NOTM:%.*]] = call i8 @llvm.smin.i8(i8 [[X]], i8 [[Y]])
+; CHECK-NEXT: ret i8 [[NOTM]]
;
%notx = xor i8 %x, -1
call void @use(i8 %notx)
@@ -622,8 +622,8 @@ define i8 @not_umax_of_not(i8 %x, i8 %y) {
; CHECK-NEXT: [[NOTX:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: call void @use(i8 [[NOTX]])
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[TMP1]])
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[NOTM:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[TMP1]])
+; CHECK-NEXT: ret i8 [[NOTM]]
;
%notx = xor i8 %x, -1
call void @use(i8 %notx)
@@ -655,8 +655,8 @@ define i8 @not_umin_of_not_constant_op(i8 %x) {
; CHECK-LABEL: @not_umin_of_not_constant_op(
; CHECK-NEXT: [[NOTX:%.*]] = xor i8 [[X:%.*]], -1
; CHECK-NEXT: call void @use(i8 [[NOTX]])
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[X]], i8 -43)
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[NOTM:%.*]] = call i8 @llvm.umax.i8(i8 [[X]], i8 -43)
+; CHECK-NEXT: ret i8 [[NOTM]]
;
%notx = xor i8 %x, -1
call void @use(i8 %notx)
@@ -668,8 +668,8 @@ define i8 @not_umin_of_not_constant_op(i8 %x) {
define i8 @smax_negation(i8 %x, i8 %y) {
; CHECK-LABEL: @smax_negation(
; CHECK-NEXT: [[S1:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
+; CHECK-NEXT: ret i8 [[R]]
;
%s1 = sub i8 %x, %y
%s2 = sub i8 %y, %x
@@ -680,8 +680,8 @@ define i8 @smax_negation(i8 %x, i8 %y) {
define i8 @smax_negation_nsw(i8 %x, i8 %y) {
; CHECK-LABEL: @smax_negation_nsw(
; CHECK-NEXT: [[S1:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 true)
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 true)
+; CHECK-NEXT: ret i8 [[R]]
;
%s1 = sub nsw i8 %x, %y
%s2 = sub nsw i8 %y, %x
@@ -692,8 +692,8 @@ define i8 @smax_negation_nsw(i8 %x, i8 %y) {
define i8 @smax_negation_not_nsw(i8 %x, i8 %y) {
; CHECK-LABEL: @smax_negation_not_nsw(
; CHECK-NEXT: [[S1:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S1]], i1 false)
+; CHECK-NEXT: ret i8 [[R]]
;
%s1 = sub nsw i8 %x, %y
%s2 = sub nuw i8 %y, %x
@@ -703,8 +703,8 @@ define i8 @smax_negation_not_nsw(i8 %x, i8 %y) {
define <3 x i8> @smax_negation_vec(<3 x i8> %x) {
; CHECK-LABEL: @smax_negation_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i8> @llvm.abs.v3i8(<3 x i8> [[X:%.*]], i1 false)
-; CHECK-NEXT: ret <3 x i8> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.abs.v3i8(<3 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT: ret <3 x i8> [[R]]
;
%s = sub <3 x i8> <i8 0, i8 undef, i8 0>, %x
%r = call <3 x i8> @llvm.smax.v3i8(<3 x i8> %x, <3 x i8> %s)
@@ -739,8 +739,8 @@ define i8 @umax_negation(i8 %x, i8 %y) {
define i8 @umin_negation(i8 %x) {
; CHECK-LABEL: @umin_negation(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
+; CHECK-NEXT: ret i8 [[R]]
;
%s = sub nsw i8 0, %x
%r = call i8 @llvm.umin.i8(i8 %s, i8 %x)
@@ -751,8 +751,8 @@ define i8 @smax_negation_uses(i8 %x, i8 %y) {
; CHECK-LABEL: @smax_negation_uses(
; CHECK-NEXT: [[S2:%.*]] = sub i8 [[Y:%.*]], [[X:%.*]]
; CHECK-NEXT: call void @use(i8 [[S2]])
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[S2]], i1 false)
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.abs.i8(i8 [[S2]], i1 false)
+; CHECK-NEXT: ret i8 [[R]]
;
%s1 = sub i8 %x, %y
%s2 = sub i8 %y, %x
@@ -1263,8 +1263,8 @@ define i8 @freeToInvert(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: call void @use(i8 [[NY]])
; CHECK-NEXT: call void @use(i8 [[NZ]])
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[Y]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[Z]])
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[Z]])
+; CHECK-NEXT: ret i8 [[NOT]]
;
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
@@ -1289,8 +1289,8 @@ define i8 @freeToInvert_use1(i8 %x, i8 %y, i8 %z) {
; CHECK-NEXT: [[M1:%.*]] = call i8 @llvm.umax.i8(i8 [[NX]], i8 [[NY]])
; CHECK-NEXT: call void @use(i8 [[M1]])
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[M1]], -1
-; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smax.i8(i8 [[Z]], i8 [[TMP1]])
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[Z]], i8 [[TMP1]])
+; CHECK-NEXT: ret i8 [[NOT]]
;
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
@@ -1373,8 +1373,8 @@ define i8 @freeToInvert_two_minmax_ops(i8 %x, i8 %y, i8 %z, i8 %w) {
; CHECK-NEXT: call void @use(i8 [[NW]])
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X]], i8 [[Y]])
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.smin.i8(i8 [[W]], i8 [[Z]])
-; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[TMP2]])
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[NOT:%.*]] = call i8 @llvm.smax.i8(i8 [[TMP1]], i8 [[TMP2]])
+; CHECK-NEXT: ret i8 [[NOT]]
;
%nx = xor i8 %x, -1
%ny = xor i8 %y, -1
diff --git a/llvm/test/Transforms/InstCombine/minmax-of-minmax.ll b/llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
index f401a50b2289e..097bb365a416a 100644
--- a/llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
@@ -3,8 +3,8 @@
define i32 @smax_of_smax_smin_commute0(i32 %x, i32 %y) {
; CHECK-LABEL: @smax_of_smax_smin_commute0(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.smax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MAX]]
;
%cmp1 = icmp slt i32 %x, %y
%min = select i1 %cmp1, i32 %x, i32 %y
@@ -17,8 +17,8 @@ define i32 @smax_of_smax_smin_commute0(i32 %x, i32 %y) {
define i32 @smax_of_smax_smin_commute1(i32 %x, i32 %y) {
; CHECK-LABEL: @smax_of_smax_smin_commute1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[MAX]]
;
%cmp1 = icmp sgt i32 %x, %y
%min = select i1 %cmp1, i32 %y, i32 %x
@@ -31,8 +31,8 @@ define i32 @smax_of_smax_smin_commute1(i32 %x, i32 %y) {
define i32 @smax_of_smax_smin_commute2(i32 %x, i32 %y) {
; CHECK-LABEL: @smax_of_smax_smin_commute2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.smax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MAX]]
;
%cmp1 = icmp slt i32 %x, %y
%min = select i1 %cmp1, i32 %x, i32 %y
@@ -45,8 +45,8 @@ define i32 @smax_of_smax_smin_commute2(i32 %x, i32 %y) {
define <2 x i32> @smax_of_smax_smin_commute3(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @smax_of_smax_smin_commute3(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[MAX]]
;
%cmp1 = icmp sgt <2 x i32> %x, %y
%min = select <2 x i1> %cmp1, <2 x i32> %y, <2 x i32> %x
@@ -59,8 +59,8 @@ define <2 x i32> @smax_of_smax_smin_commute3(<2 x i32> %x, <2 x i32> %y) {
define i32 @smin_of_smin_smax_commute0(i32 %x, i32 %y) {
; CHECK-LABEL: @smin_of_smin_smax_commute0(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp sgt i32 %x, %y
%max = select i1 %cmp1, i32 %x, i32 %y
@@ -73,8 +73,8 @@ define i32 @smin_of_smin_smax_commute0(i32 %x, i32 %y) {
define i32 @smin_of_smin_smax_commute1(i32 %x, i32 %y) {
; CHECK-LABEL: @smin_of_smin_smax_commute1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp slt i32 %x, %y
%max = select i1 %cmp1, i32 %y, i32 %x
@@ -87,8 +87,8 @@ define i32 @smin_of_smin_smax_commute1(i32 %x, i32 %y) {
define <2 x i32> @smin_of_smin_smax_commute2(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @smin_of_smin_smax_commute2(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[MIN]]
;
%cmp1 = icmp sgt <2 x i32> %x, %y
%max = select <2 x i1> %cmp1, <2 x i32> %x, <2 x i32> %y
@@ -101,8 +101,8 @@ define <2 x i32> @smin_of_smin_smax_commute2(<2 x i32> %x, <2 x i32> %y) {
define i32 @smin_of_smin_smax_commute3(i32 %x, i32 %y) {
; CHECK-LABEL: @smin_of_smin_smax_commute3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp slt i32 %x, %y
%max = select i1 %cmp1, i32 %y, i32 %x
@@ -115,8 +115,8 @@ define i32 @smin_of_smin_smax_commute3(i32 %x, i32 %y) {
define i32 @umax_of_umax_umin_commute0(i32 %x, i32 %y) {
; CHECK-LABEL: @umax_of_umax_umin_commute0(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.umax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MAX]]
;
%cmp1 = icmp ult i32 %x, %y
%min = select i1 %cmp1, i32 %x, i32 %y
@@ -129,8 +129,8 @@ define i32 @umax_of_umax_umin_commute0(i32 %x, i32 %y) {
define i32 @umax_of_umax_umin_commute1(i32 %x, i32 %y) {
; CHECK-LABEL: @umax_of_umax_umin_commute1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[MAX]]
;
%cmp1 = icmp ugt i32 %x, %y
%min = select i1 %cmp1, i32 %y, i32 %x
@@ -143,8 +143,8 @@ define i32 @umax_of_umax_umin_commute1(i32 %x, i32 %y) {
define i32 @umax_of_umax_umin_commute2(i32 %x, i32 %y) {
; CHECK-LABEL: @umax_of_umax_umin_commute2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.umax.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MAX]]
;
%cmp1 = icmp ult i32 %x, %y
%min = select i1 %cmp1, i32 %x, i32 %y
@@ -157,8 +157,8 @@ define i32 @umax_of_umax_umin_commute2(i32 %x, i32 %y) {
define <2 x i32> @umax_of_umax_umin_commute3(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @umax_of_umax_umin_commute3(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[MAX:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[MAX]]
;
%cmp1 = icmp ugt <2 x i32> %x, %y
%min = select <2 x i1> %cmp1, <2 x i32> %y, <2 x i32> %x
@@ -171,8 +171,8 @@ define <2 x i32> @umax_of_umax_umin_commute3(<2 x i32> %x, <2 x i32> %y) {
define i32 @umin_of_umin_umax_commute0(i32 %x, i32 %y) {
; CHECK-LABEL: @umin_of_umin_umax_commute0(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp ugt i32 %x, %y
%max = select i1 %cmp1, i32 %x, i32 %y
@@ -185,8 +185,8 @@ define i32 @umin_of_umin_umax_commute0(i32 %x, i32 %y) {
define i32 @umin_of_umin_umax_commute1(i32 %x, i32 %y) {
; CHECK-LABEL: @umin_of_umin_umax_commute1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp ult i32 %x, %y
%max = select i1 %cmp1, i32 %y, i32 %x
@@ -199,8 +199,8 @@ define i32 @umin_of_umin_umax_commute1(i32 %x, i32 %y) {
define <2 x i32> @umin_of_umin_umax_commute2(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @umin_of_umin_umax_commute2(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[MIN]]
;
%cmp1 = icmp ugt <2 x i32> %x, %y
%max = select <2 x i1> %cmp1, <2 x i32> %x, <2 x i32> %y
@@ -213,8 +213,8 @@ define <2 x i32> @umin_of_umin_umax_commute2(<2 x i32> %x, <2 x i32> %y) {
define i32 @umin_of_umin_umax_commute3(i32 %x, i32 %y) {
; CHECK-LABEL: @umin_of_umin_umax_commute3(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp ult i32 %x, %y
%max = select i1 %cmp1, i32 %y, i32 %x
@@ -229,8 +229,8 @@ define i32 @umin_of_umin_umax_commute3(i32 %x, i32 %y) {
define i32 @umin_of_smin_umax_wrong_pattern(i32 %x, i32 %y) {
; CHECK-LABEL: @umin_of_smin_umax_wrong_pattern(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp ugt i32 %x, %y
%max = select i1 %cmp1, i32 %x, i32 %y
@@ -245,10 +245,10 @@ define i32 @umin_of_smin_umax_wrong_pattern(i32 %x, i32 %y) {
define i32 @smin_of_umin_umax_wrong_pattern2(i32 %x, i32 %y) {
; CHECK-LABEL: @smin_of_umin_umax_wrong_pattern2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umin.i32(i32 [[X]], i32 [[Y]])
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[TMP2]])
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[MAX:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[X]], i32 [[Y]])
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[MAX]], i32 [[MIN]])
+; CHECK-NEXT: ret i32 [[R]]
;
%cmp1 = icmp ult i32 %x, %y
%max = select i1 %cmp1, i32 %y, i32 %x
@@ -263,8 +263,8 @@ define i32 @smin_of_umin_umax_wrong_pattern2(i32 %x, i32 %y) {
define <2 x i32> @umin_of_umin_umax_wrong_operand(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; CHECK-LABEL: @umin_of_umin_umax_wrong_operand(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Z:%.*]])
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Z:%.*]])
+; CHECK-NEXT: ret <2 x i32> [[MIN]]
;
%cmp1 = icmp ugt <2 x i32> %x, %y
%max = select <2 x i1> %cmp1, <2 x i32> %x, <2 x i32> %y
@@ -279,8 +279,8 @@ define <2 x i32> @umin_of_umin_umax_wrong_operand(<2 x i32> %x, <2 x i32> %y, <2
define i32 @umin_of_umin_umax_wrong_operand2(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @umin_of_umin_umax_wrong_operand2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[Y:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT: ret i32 [[MIN]]
;
%cmp1 = icmp ult i32 %x, %z
%max = select i1 %cmp1, i32 %z, i32 %x
diff --git a/llvm/test/Transforms/InstCombine/minnum.ll b/llvm/test/Transforms/InstCombine/minnum.ll
index 6bb5b7a815a7b..3fb267d6b9961 100644
--- a/llvm/test/Transforms/InstCombine/minnum.ll
+++ b/llvm/test/Transforms/InstCombine/minnum.ll
@@ -149,8 +149,8 @@ define float @minnum_f32_val_nan(float %x) {
define float @minnum_f32_1_minnum_val_p0(float %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_val_p0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minnum.f32(float %x, float 0.0)
%z = call float @llvm.minnum.f32(float %y, float 1.0)
@@ -159,8 +159,8 @@ define float @minnum_f32_1_minnum_val_p0(float %x) {
define float @minnum_f32_1_minnum_p0_val_fast(float %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fast(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minnum.f32(float 0.0, float %x)
%z = call fast float @llvm.minnum.f32(float %y, float 1.0)
@@ -169,8 +169,8 @@ define float @minnum_f32_1_minnum_p0_val_fast(float %x) {
define float @minnum_f32_1_minnum_p0_val_fmf1(float %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fmf1(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nsz nnan float @llvm.minnum.f32(float 0.0, float %x)
%z = call nnan ninf float @llvm.minnum.f32(float %y, float 1.0)
@@ -179,8 +179,8 @@ define float @minnum_f32_1_minnum_p0_val_fmf1(float %x) {
define float @minnum_f32_1_minnum_p0_val_fmf2(float %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fmf2(
-; CHECK-NEXT: [[TMP1:%.*]] = call ninf float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call ninf float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nnan ninf float @llvm.minnum.f32(float 0.0, float %x)
%z = call nsz ninf float @llvm.minnum.f32(float %y, float 1.0)
@@ -189,8 +189,8 @@ define float @minnum_f32_1_minnum_p0_val_fmf2(float %x) {
define float @minnum_f32_1_minnum_p0_val_fmf3(float %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fmf3(
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call nnan ninf nsz float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call nsz ninf nnan float @llvm.minnum.f32(float 0.0, float %x)
%z = call nsz ninf nnan float @llvm.minnum.f32(float %y, float 1.0)
@@ -199,8 +199,8 @@ define float @minnum_f32_1_minnum_p0_val_fmf3(float %x) {
define float @minnum_f32_p0_minnum_val_n0(float %x) {
; CHECK-LABEL: @minnum_f32_p0_minnum_val_n0(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minnum.f32(float %x, float -0.0)
%z = call float @llvm.minnum.f32(float %y, float 0.0)
@@ -209,8 +209,8 @@ define float @minnum_f32_p0_minnum_val_n0(float %x) {
define float @minnum_f32_1_minnum_p0_val(float %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_p0_val(
-; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00)
+; CHECK-NEXT: ret float [[Z]]
;
%y = call float @llvm.minnum.f32(float 0.0, float %x)
%z = call float @llvm.minnum.f32(float %y, float 1.0)
@@ -219,8 +219,8 @@ define float @minnum_f32_1_minnum_p0_val(float %x) {
define <2 x float> @minnum_f32_1_minnum_val_p0_val_v2f32(<2 x float> %x) {
; CHECK-LABEL: @minnum_f32_1_minnum_val_p0_val_v2f32(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.minnum.v2f32(<2 x float> [[X:%.*]], <2 x float> zeroinitializer)
-; CHECK-NEXT: ret <2 x float> [[TMP1]]
+; CHECK-NEXT: [[Z:%.*]] = call <2 x float> @llvm.minnum.v2f32(<2 x float> [[X:%.*]], <2 x float> zeroinitializer)
+; CHECK-NEXT: ret <2 x float> [[Z]]
;
%y = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> zeroinitializer)
%z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %y, <2 x float><float 1.0, float 1.0>)
@@ -415,8 +415,8 @@ define double @unary_neg_neg_extra_use_x_and_y(double %x, double %y) {
define float @reduce_precision(float %x, float %y) {
; CHECK-LABEL: @reduce_precision(
-; CHECK-NEXT: [[MINNUM:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MINNUM]]
+; CHECK-NEXT: [[MINNUM1:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MINNUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -427,8 +427,8 @@ define float @reduce_precision(float %x, float %y) {
define float @reduce_precision_fmf(float %x, float %y) {
; CHECK-LABEL: @reduce_precision_fmf(
-; CHECK-NEXT: [[MINNUM:%.*]] = call nnan float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
-; CHECK-NEXT: ret float [[MINNUM]]
+; CHECK-NEXT: [[MINNUM1:%.*]] = call nnan float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
+; CHECK-NEXT: ret float [[MINNUM1]]
;
%x.ext = fpext float %x to double
%y.ext = fpext float %y to double
@@ -474,8 +474,8 @@ define float @reduce_precision_multi_use_1(float %x, float %y) {
define float @negated_op(float %x) {
; CHECK-LABEL: @negated_op(
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]]
-; CHECK-NEXT: ret float [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = fneg float [[TMP1]]
+; CHECK-NEXT: ret float [[R]]
;
%negx = fneg float %x
%r = call float @llvm.minnum.f32(float %x, float %negx)
@@ -485,8 +485,8 @@ define float @negated_op(float %x) {
define <2 x double> @negated_op_fmf_commute_vec(<2 x double> %x) {
; CHECK-LABEL: @negated_op_fmf_commute_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> [[X:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = fneg nnan ninf nsz <2 x double> [[TMP1]]
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = fneg nnan ninf nsz <2 x double> [[TMP1]]
+; CHECK-NEXT: ret <2 x double> [[R]]
;
%negx = fneg <2 x double> %x
%r = call nsz nnan ninf <2 x double> @llvm.minnum.v2f64(<2 x double> %negx, <2 x double> %x)
diff --git a/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll b/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
index fe6282fc444bc..f0c97c1707cde 100644
--- a/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
@@ -699,8 +699,8 @@ define i64 @test_mul_canonicalize_neg_is_not_undone(i64 %L1) {
define i32 @negate_if_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_true(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 -1, i32 1
%r = mul i32 %sel, %x
@@ -710,8 +710,8 @@ define i32 @negate_if_true(i32 %x, i1 %cond) {
define i32 @negate_if_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_false(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 1, i32 -1
%r = mul i32 %sel, %x
@@ -721,8 +721,8 @@ define i32 @negate_if_false(i32 %x, i1 %cond) {
define i32 @negate_if_true_nsw(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_true_nsw(
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 -1, i32 1
%r = mul nsw i32 %sel, %x
@@ -732,8 +732,8 @@ define i32 @negate_if_true_nsw(i32 %x, i1 %cond) {
define i32 @negate_if_true_nuw(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_true_nuw(
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 -1, i32 1
%r = mul nuw i32 %sel, %x
@@ -743,8 +743,8 @@ define i32 @negate_if_true_nuw(i32 %x, i1 %cond) {
define i32 @negate_if_false_nsw(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_false_nsw(
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 1, i32 -1
%r = mul nsw i32 %sel, %x
@@ -754,8 +754,8 @@ define i32 @negate_if_false_nsw(i32 %x, i1 %cond) {
define i32 @negate_if_false_nuw(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_false_nuw(
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 1, i32 -1
%r = mul nuw i32 %sel, %x
@@ -766,8 +766,8 @@ define <2 x i8> @negate_if_true_commute(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @negate_if_true_commute(
; CHECK-NEXT: [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 42>, [[PX:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
-; CHECK-NEXT: ret <2 x i8> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
;
%x = sdiv <2 x i8> <i8 42, i8 42>, %px ; thwart complexity-based canonicalization
%sel = select i1 %cond, <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 1, i8 1>
@@ -779,8 +779,8 @@ define <2 x i8> @negate_if_false_commute(<2 x i8> %px, <2 x i1> %cond) {
; CHECK-LABEL: @negate_if_false_commute(
; CHECK-NEXT: [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 5>, [[PX:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
-; CHECK-NEXT: ret <2 x i8> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
;
%x = sdiv <2 x i8> <i8 42, i8 5>, %px ; thwart complexity-based canonicalization
%sel = select <2 x i1> %cond, <2 x i8> <i8 1, i8 undef>, <2 x i8> <i8 -1, i8 -1>
diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll
index aefeb99c4810f..81f634a879c9c 100644
--- a/llvm/test/Transforms/InstCombine/mul.ll
+++ b/llvm/test/Transforms/InstCombine/mul.ll
@@ -1260,8 +1260,8 @@ define i64 @test_mul_canonicalize_neg_is_not_undone(i64 %L1) {
define i32 @negate_if_true(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_true(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 -1, i32 1
%r = mul i32 %sel, %x
@@ -1271,8 +1271,8 @@ define i32 @negate_if_true(i32 %x, i1 %cond) {
define i32 @negate_if_false(i32 %x, i1 %cond) {
; CHECK-LABEL: @negate_if_false(
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[X]], i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 1, i32 -1
%r = mul i32 %sel, %x
@@ -1283,8 +1283,8 @@ define <2 x i8> @negate_if_true_commute(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @negate_if_true_commute(
; CHECK-NEXT: [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 42>, [[PX:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
-; CHECK-NEXT: ret <2 x i8> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], <2 x i8> [[TMP1]], <2 x i8> [[X]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
;
%x = sdiv <2 x i8> <i8 42, i8 42>, %px ; thwart complexity-based canonicalization
%sel = select i1 %cond, <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 1, i8 1>
@@ -1296,8 +1296,8 @@ define <2 x i8> @negate_if_false_commute(<2 x i8> %px, <2 x i1> %cond) {
; CHECK-LABEL: @negate_if_false_commute(
; CHECK-NEXT: [[X:%.*]] = sdiv <2 x i8> <i8 42, i8 5>, [[PX:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
-; CHECK-NEXT: ret <2 x i8> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i8> [[X]], <2 x i8> [[TMP1]]
+; CHECK-NEXT: ret <2 x i8> [[R]]
;
%x = sdiv <2 x i8> <i8 42, i8 5>, %px ; thwart complexity-based canonicalization
%sel = select <2 x i1> %cond, <2 x i8> <i8 1, i8 undef>, <2 x i8> <i8 -1, i8 -1>
diff --git a/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll b/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
index c2dfb302f4217..a75a6496961b4 100644
--- a/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
+++ b/llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
@@ -8,9 +8,9 @@ define void @PR35618(ptr %st1, ptr %st2) {
; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1]], align 8
; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = fcmp olt double [[LD1]], [[LD2]]
-; CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP10]], double [[LD1]], double [[LD2]]
-; CHECK-NEXT: store double [[TMP121]], ptr [[ST1:%.*]], align 8
-; CHECK-NEXT: store double [[TMP121]], ptr [[ST2:%.*]], align 8
+; CHECK-NEXT: [[TMP12_V:%.*]] = select i1 [[TMP10]], double [[LD1]], double [[LD2]]
+; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST1:%.*]], align 8
+; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST2:%.*]], align 8
; CHECK-NEXT: ret void
;
%y1 = alloca double
diff --git a/llvm/test/Transforms/InstCombine/narrow-math.ll b/llvm/test/Transforms/InstCombine/narrow-math.ll
index 6355ea1734c2a..bfff00f62deac 100644
--- a/llvm/test/Transforms/InstCombine/narrow-math.ll
+++ b/llvm/test/Transforms/InstCombine/narrow-math.ll
@@ -122,8 +122,8 @@ define i64 @sext_sext_add_extra_use3(i32 %A) {
define i64 @test1(i32 %V) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0:!range !.*]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0:![0-9]+]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[NARROW:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64
; CHECK-NEXT: ret i64 [[ADD]]
@@ -138,8 +138,8 @@ define i64 @test1(i32 %V) {
define i64 @test2(i32 %V) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
; CHECK-NEXT: ret i64 [[ZEXT]]
@@ -153,8 +153,8 @@ define i64 @test2(i32 %V) {
define i64 @test3(i32 %V) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[NARROW:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64
; CHECK-NEXT: ret i64 [[ADD]]
@@ -169,8 +169,8 @@ define i64 @test3(i32 %V) {
define i64 @test4(i32 %V) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[ADD:%.*]] = mul nuw nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
; CHECK-NEXT: ret i64 [[ZEXT]]
@@ -461,8 +461,8 @@ define <2 x i64> @test10_vec(<2 x i32> %V) {
define i64 @test11(i32 %V) {
; CHECK-LABEL: @test11(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG1:!range !.*]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG1]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1:![0-9]+]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]]
; CHECK-NEXT: [[NARROW:%.*]] = add nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[ADD:%.*]] = sext i32 [[NARROW]] to i64
; CHECK-NEXT: ret i64 [[ADD]]
@@ -477,8 +477,8 @@ define i64 @test11(i32 %V) {
define i64 @test12(i32 %V) {
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG1]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG1]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG1]]
; CHECK-NEXT: [[NARROW:%.*]] = mul nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[NARROW]] to i64
; CHECK-NEXT: ret i64 [[ADD]]
@@ -493,8 +493,8 @@ define i64 @test12(i32 %V) {
define i64 @test13(i32 %V) {
; CHECK-LABEL: @test13(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG2:!range !.*]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG3:!range !.*]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG2:![0-9]+]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG3:![0-9]+]]
; CHECK-NEXT: [[NARROW:%.*]] = sub nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[SUB:%.*]] = sext i32 [[NARROW]] to i64
; CHECK-NEXT: ret i64 [[SUB]]
@@ -509,8 +509,8 @@ define i64 @test13(i32 %V) {
define i64 @test14(i32 %V) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG2]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG2]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[NARROW:%.*]] = sub nuw nsw i32 [[CALL1]], [[CALL2]]
; CHECK-NEXT: [[SUB:%.*]] = zext i32 [[NARROW]] to i64
; CHECK-NEXT: ret i64 [[SUB]]
@@ -579,8 +579,8 @@ define <2 x i64> @test16vec(<2 x i32> %V) {
; won't wrap.
define i64 @test17(i32 %V) {
; CHECK-LABEL: @test17(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
-; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
+; CHECK-NEXT: [[CALL2:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64
; CHECK-NEXT: [[SEXT2:%.*]] = zext i32 [[CALL2]] to i64
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[SEXT1]], [[SEXT2]]
@@ -598,7 +598,7 @@ define i64 @test17(i32 %V) {
; cause overflow.
define i64 @test18(i32 %V) {
; CHECK-LABEL: @test18(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG1]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG1]]
; CHECK-NEXT: [[SEXT1:%.*]] = sext i32 [[CALL1]] to i64
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 2147481648, [[SEXT1]]
; CHECK-NEXT: ret i64 [[SUB]]
@@ -613,7 +613,7 @@ define i64 @test18(i32 %V) {
; cause overflow.
define i64 @test19(i32 %V) {
; CHECK-LABEL: @test19(
-; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), [[RNG0]]
+; CHECK-NEXT: [[CALL1:%.*]] = call i32 @callee(), !range [[RNG0]]
; CHECK-NEXT: [[SEXT1:%.*]] = zext i32 [[CALL1]] to i64
; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i64 -2147481648, [[SEXT1]]
; CHECK-NEXT: ret i64 [[SUB]]
diff --git a/llvm/test/Transforms/InstCombine/nested-select.ll b/llvm/test/Transforms/InstCombine/nested-select.ll
index 2eb481570cee0..42a0f81e7b85a 100644
--- a/llvm/test/Transforms/InstCombine/nested-select.ll
+++ b/llvm/test/Transforms/InstCombine/nested-select.ll
@@ -7,7 +7,7 @@ declare void @use.i8(i8)
; Basic test
define i8 @andcond(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond(
+; CHECK-LABEL: @andcond(
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i8 [[OUTER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i8 [[INNER_SEL]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: ret i8 [[OUTER_SEL]]
@@ -18,7 +18,7 @@ define i8 @andcond(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inne
ret i8 %outer.sel
}
define i8 @orcond(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond(
+; CHECK-LABEL: @orcond(
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]], i8 [[OUTER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL]]
; CHECK-NEXT: ret i8 [[OUTER_SEL]]
@@ -32,7 +32,7 @@ define i8 @orcond(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner
; Extra use tests (basic test, no inversions)
define i8 @andcond.extrause0(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.extrause0(
+; CHECK-LABEL: @andcond.extrause0(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: call void @use.i1(i1 [[OUTER_COND]])
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND]], i8 [[OUTER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]]
@@ -46,7 +46,7 @@ define i8 @andcond.extrause0(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval
ret i8 %outer.sel
}
define i8 @orcond.extrause0(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.extrause0(
+; CHECK-LABEL: @orcond.extrause0(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND:%.*]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: call void @use.i1(i1 [[OUTER_COND]])
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND]], i8 [[INNER_SEL_FALSEVAL:%.*]], i8 [[OUTER_SEL_FALSEVAL:%.*]]
@@ -61,7 +61,7 @@ define i8 @orcond.extrause0(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval,
}
define i8 @andcond.extrause1(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.extrause1(
+; CHECK-LABEL: @andcond.extrause1(
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[INNER_COND:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: call void @use.i8(i8 [[TMP1]])
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i8 [[OUTER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_TRUEVAL]]
@@ -75,7 +75,7 @@ define i8 @andcond.extrause1(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval
ret i8 %outer.sel
}
define i8 @orcond.extrause1(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.extrause1(
+; CHECK-LABEL: @orcond.extrause1(
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[INNER_COND:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: call void @use.i8(i8 [[TMP1]])
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i8 [[INNER_SEL_FALSEVAL]], i8 [[OUTER_SEL_FALSEVAL:%.*]]
@@ -90,7 +90,7 @@ define i8 @orcond.extrause1(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval,
}
define i8 @andcond.extrause2(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.extrause2(
+; CHECK-LABEL: @andcond.extrause2(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: call void @use.i1(i1 [[OUTER_COND]])
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[INNER_COND]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
@@ -106,7 +106,7 @@ define i8 @andcond.extrause2(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval
ret i8 %outer.sel
}
define i8 @orcond.extrause2(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.extrause2(
+; CHECK-LABEL: @orcond.extrause2(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND:%.*]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: call void @use.i1(i1 [[OUTER_COND]])
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[INNER_COND]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
@@ -125,7 +125,7 @@ define i8 @orcond.extrause2(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval,
; Mismatched 'common' cond
define i8 @andcond.
diff erent.inner.cond(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.
diff erent.inner.cond(
+; CHECK-LABEL: @andcond.
diff erent.inner.cond(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND_V0:%.*]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[INNER_COND_V1:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[OUTER_COND]], i8 [[OUTER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL]]
@@ -138,7 +138,7 @@ define i8 @andcond.
diff erent.inner.cond(i1 %inner.cond.v0, i1 %inner.cond.v1, i1
ret i8 %outer.sel
}
define i8 @orcond.
diff erent.inner.cond(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.
diff erent.inner.cond(
+; CHECK-LABEL: @orcond.
diff erent.inner.cond(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND_V0:%.*]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[INNER_COND_V1:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[OUTER_COND]], i8 [[INNER_SEL]], i8 [[OUTER_SEL_FALSEVAL:%.*]]
@@ -151,7 +151,7 @@ define i8 @orcond.
diff erent.inner.cond(i1 %inner.cond.v0, i1 %inner.cond.v1, i1
}
define i1 @andcond.
diff erent.inner.cond.both.inverted(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.
diff erent.inner.cond.both.inverted(
+; CHECK-LABEL: @andcond.
diff erent.inner.cond.both.inverted(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND_V0:%.*]], true
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: [[NOT_INNER_COND_1:%.*]] = xor i1 [[INNER_COND_V1:%.*]], true
@@ -167,7 +167,7 @@ define i1 @andcond.
diff erent.inner.cond.both.inverted(i1 %inner.cond.v0, i1 %inn
ret i1 %outer.sel
}
define i1 @orcond.
diff erent.inner.cond.both.inverted(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.
diff erent.inner.cond.both.inverted(
+; CHECK-LABEL: @orcond.
diff erent.inner.cond.both.inverted(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND_V0:%.*]], true
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: [[NOT_INNER_COND_1:%.*]] = xor i1 [[INNER_COND_V1:%.*]], true
@@ -184,7 +184,7 @@ define i1 @orcond.
diff erent.inner.cond.both.inverted(i1 %inner.cond.v0, i1 %inne
}
define i1 @andcond.
diff erent.inner.cond.inverted.in.outer.cond(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.
diff erent.inner.cond.inverted.in.outer.cond(
+; CHECK-LABEL: @andcond.
diff erent.inner.cond.inverted.in.outer.cond(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND_V0:%.*]], true
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[INNER_COND_V1:%.*]], i1 [[INNER_SEL_FALSEVAL:%.*]], i1 false
@@ -198,7 +198,7 @@ define i1 @andcond.
diff erent.inner.cond.inverted.in.outer.cond(i1 %inner.cond.v0
ret i1 %outer.sel
}
define i1 @orcond.
diff erent.inner.cond.inverted.in.outer.cond(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.
diff erent.inner.cond.inverted.in.outer.cond(
+; CHECK-LABEL: @orcond.
diff erent.inner.cond.inverted.in.outer.cond(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND_V0:%.*]], true
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[INNER_COND_V1:%.*]], i1 true, i1 [[INNER_SEL_TRUEVAL:%.*]]
@@ -213,7 +213,7 @@ define i1 @orcond.
diff erent.inner.cond.inverted.in.outer.cond(i1 %inner.cond.v0,
}
define i1 @andcond.
diff erent.inner.cond.inverted.in.inner.sel(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.
diff erent.inner.cond.inverted.in.inner.sel(
+; CHECK-LABEL: @andcond.
diff erent.inner.cond.inverted.in.inner.sel(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND_V0:%.*]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: [[NOT_INNER_COND_1:%.*]] = xor i1 [[INNER_COND_V1:%.*]], true
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[NOT_INNER_COND_1]], i1 [[INNER_SEL_FALSEVAL:%.*]], i1 false
@@ -227,7 +227,7 @@ define i1 @andcond.
diff erent.inner.cond.inverted.in.inner.sel(i1 %inner.cond.v0,
ret i1 %outer.sel
}
define i1 @orcond.
diff erent.inner.cond.inverted.in.inner.sel(i1 %inner.cond.v0, i1 %inner.cond.v1, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.
diff erent.inner.cond.inverted.in.inner.sel(
+; CHECK-LABEL: @orcond.
diff erent.inner.cond.inverted.in.inner.sel(
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[INNER_COND_V0:%.*]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: [[NOT_INNER_COND_1:%.*]] = xor i1 [[INNER_COND_V1:%.*]], true
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[NOT_INNER_COND_1]], i1 true, i1 [[INNER_SEL_TRUEVAL:%.*]]
@@ -262,7 +262,7 @@ define i8 @D139275_c4001580(i1 %c0, i1 %c1, i1 %c2, i8 %inner.sel.trueval, i8 %i
; In %outer.sel, %outer.cond is inverted
define i1 @andcond.001.inv.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.001.inv.outer.cond(
+; CHECK-LABEL: @andcond.001.inv.outer.cond(
; CHECK-NEXT: [[NOT_ALT_COND:%.*]] = xor i1 [[ALT_COND:%.*]], true
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[NOT_ALT_COND]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 false
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[INNER_SEL]], i1 [[INNER_SEL_FALSEVAL:%.*]]
@@ -275,7 +275,7 @@ define i1 @andcond.001.inv.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.se
ret i1 %outer.sel
}
define i1 @orcond.001.inv.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.001.inv.outer.cond(
+; CHECK-LABEL: @orcond.001.inv.outer.cond(
; CHECK-NEXT: [[NOT_ALT_COND:%.*]] = xor i1 [[ALT_COND:%.*]], true
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[NOT_ALT_COND]], i1 true, i1 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 [[INNER_SEL]]
@@ -290,7 +290,7 @@ define i1 @orcond.001.inv.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel
; In %inner.sel, %inner.cond is inverted
define i1 @andcond.010.inv.inner.cond.in.inner.sel(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.010.inv.inner.cond.in.inner.sel(
+; CHECK-LABEL: @andcond.010.inv.inner.cond.in.inner.sel(
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i1 [[OUTER_SEL_TRUEVAL:%.*]], i1 false
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[INNER_SEL]], i1 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: ret i1 [[OUTER_SEL]]
@@ -302,7 +302,7 @@ define i1 @andcond.010.inv.inner.cond.in.inner.sel(i1 %inner.cond, i1 %alt.cond,
ret i1 %outer.sel
}
define i1 @orcond.010.inv.inner.cond.in.inner.sel(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.010.inv.inner.cond.in.inner.sel(
+; CHECK-LABEL: @orcond.010.inv.inner.cond.in.inner.sel(
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i1 true, i1 [[OUTER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 [[INNER_SEL]]
; CHECK-NEXT: ret i1 [[OUTER_SEL]]
@@ -316,7 +316,7 @@ define i1 @orcond.010.inv.inner.cond.in.inner.sel(i1 %inner.cond, i1 %alt.cond,
; In %outer.cond, %inner.cond is inverted
define i8 @andcond.100.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.100.inv.inner.cond.in.outer.cond(
+; CHECK-LABEL: @andcond.100.inv.inner.cond.in.outer.cond(
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i8 [[OUTER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[INNER_SEL]]
; CHECK-NEXT: ret i8 [[OUTER_SEL]]
@@ -328,7 +328,7 @@ define i8 @andcond.100.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond
ret i8 %outer.sel
}
define i8 @orcond.100.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond, i8 %inner.sel.trueval, i8 %inner.sel.falseval, i8 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.100.inv.inner.cond.in.outer.cond(
+; CHECK-LABEL: @orcond.100.inv.inner.cond.in.outer.cond(
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i8 [[INNER_SEL_TRUEVAL:%.*]], i8 [[OUTER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[INNER_COND:%.*]], i8 [[INNER_SEL]], i8 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: ret i8 [[OUTER_SEL]]
@@ -343,7 +343,7 @@ define i8 @orcond.100.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond,
; In %outer.sel, %outer.cond is inverted
; In %inner.sel, %inner.cond is inverted
define i1 @andcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(
+; CHECK-LABEL: @andcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(
; CHECK-NEXT: [[NOT_INNER_COND:%.*]] = xor i1 [[INNER_COND:%.*]], true
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[NOT_INNER_COND]], i1 true, i1 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: call void @use.i1(i1 [[TMP1]])
@@ -362,7 +362,7 @@ define i1 @andcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(i1 %inner.cond
ret i1 %outer.sel
}
define i1 @orcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(
+; CHECK-LABEL: @orcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(
; CHECK-NEXT: [[NOT_INNER_COND:%.*]] = xor i1 [[INNER_COND:%.*]], true
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[NOT_INNER_COND]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 false
; CHECK-NEXT: call void @use.i1(i1 [[TMP1]])
@@ -384,7 +384,7 @@ define i1 @orcond.011.inv.outer.cond.inv.inner.cond.in.inner.sel(i1 %inner.cond,
; In %outer.sel, %outer.cond is inverted
; In %outer.cond, %inner.cond is inverted
define i1 @andcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(
+; CHECK-LABEL: @andcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: call void @use.i1(i1 [[TMP1]])
; CHECK-NEXT: [[ALT_COND_NOT:%.*]] = xor i1 [[ALT_COND:%.*]], true
@@ -401,7 +401,7 @@ define i1 @andcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(i1 %inner.con
ret i1 %outer.sel
}
define i1 @orcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(
+; CHECK-LABEL: @orcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[INNER_COND:%.*]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: call void @use.i1(i1 [[TMP1]])
; CHECK-NEXT: [[ALT_COND_NOT:%.*]] = xor i1 [[ALT_COND:%.*]], true
@@ -421,7 +421,7 @@ define i1 @orcond.101.inv.outer.cond.inv.inner.cond.in.outer.cond(i1 %inner.cond
; In %inner.sel, %inner.cond is inverted
; In %outer.cond, %inner.cond is inverted
define i1 @andcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(
+; CHECK-LABEL: @andcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND:%.*]], true
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i1 [[OUTER_SEL_TRUEVAL:%.*]], i1 [[INNER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 [[INNER_SEL]], i1 false
@@ -435,7 +435,7 @@ define i1 @andcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(
ret i1 %outer.sel
}
define i1 @orcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(
+; CHECK-LABEL: @orcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND:%.*]], true
; CHECK-NEXT: [[INNER_SEL:%.*]] = select i1 [[ALT_COND:%.*]], i1 [[INNER_SEL_TRUEVAL:%.*]], i1 [[OUTER_SEL_FALSEVAL:%.*]]
; CHECK-NEXT: [[OUTER_SEL:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 true, i1 [[INNER_SEL]]
@@ -453,7 +453,7 @@ define i1 @orcond.110.inv.inner.cond.in.inner.sel.inv.inner.cond.in.outer.cond(i
; In %inner.sel, %inner.cond is inverted
; In %outer.cond, %inner.cond is inverted
define i1 @andcond.111.inv.all.conds(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.trueval) {
-; CHECK-LABEL: define {{[^@]+}}@andcond.111.inv.all.conds(
+; CHECK-LABEL: @andcond.111.inv.all.conds(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND:%.*]], true
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 [[ALT_COND:%.*]], i1 false
; CHECK-NEXT: call void @use.i1(i1 [[OUTER_COND]])
@@ -476,7 +476,7 @@ define i1 @andcond.111.inv.all.conds(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel
ret i1 %outer.sel
}
define i1 @orcond.111.inv.all.conds(i1 %inner.cond, i1 %alt.cond, i1 %inner.sel.trueval, i1 %inner.sel.falseval, i1 %outer.sel.falseval) {
-; CHECK-LABEL: define {{[^@]+}}@orcond.111.inv.all.conds(
+; CHECK-LABEL: @orcond.111.inv.all.conds(
; CHECK-NEXT: [[NOT_INNER_COND_0:%.*]] = xor i1 [[INNER_COND:%.*]], true
; CHECK-NEXT: [[OUTER_COND:%.*]] = select i1 [[NOT_INNER_COND_0]], i1 true, i1 [[ALT_COND:%.*]]
; CHECK-NEXT: call void @use.i1(i1 [[OUTER_COND]])
diff --git a/llvm/test/Transforms/InstCombine/onehot_merge.ll b/llvm/test/Transforms/InstCombine/onehot_merge.ll
index 73d4600a59e10..3622db419ff47 100644
--- a/llvm/test/Transforms/InstCombine/onehot_merge.ll
+++ b/llvm/test/Transforms/InstCombine/onehot_merge.ll
@@ -4,8 +4,8 @@
define i1 @and_consts(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @and_consts(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 12
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP1]], 12
+; CHECK-NEXT: ret i1 [[OR]]
;
%t1 = and i32 4, %k
%t2 = icmp eq i32 %t1, 0
@@ -18,8 +18,8 @@ define i1 @and_consts(i32 %k, i32 %c1, i32 %c2) {
define i1 @and_consts_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @and_consts_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 12
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP1]], 12
+; CHECK-NEXT: ret i1 [[OR]]
;
%t1 = and i32 4, %k
%t2 = icmp eq i32 %t1, 0
@@ -32,8 +32,8 @@ define i1 @and_consts_logical(i32 %k, i32 %c1, i32 %c2) {
define <2 x i1> @and_consts_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {
; CHECK-LABEL: @and_consts_vector(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[K:%.*]], <i32 12, i32 12>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], <i32 12, i32 12>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP1]], <i32 12, i32 12>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t1 = and <2 x i32> <i32 4, i32 4>, %k
%t2 = icmp eq <2 x i32> %t1, zeroinitializer
@@ -49,8 +49,8 @@ define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = shl i32 1, %c2
@@ -69,8 +69,8 @@ define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = shl i32 1, %c2
@@ -88,8 +88,8 @@ define <2 x i1> @foo1_and_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {
; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t = shl <2 x i32> <i32 1, i32 1>, %c1
%t4 = shl <2 x i32> <i32 1, i32 1>, %c2
@@ -109,8 +109,8 @@ define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%k2 = mul i32 %k, %k ; to trick the complexity sorting
%t = shl i32 1, %c1
@@ -131,8 +131,8 @@ define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%k2 = mul i32 %k, %k ; to trick the complexity sorting
%t = shl i32 1, %c1
@@ -152,8 +152,8 @@ define <2 x i1> @foo1_and_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32>
; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K2]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%k2 = mul <2 x i32> %k, %k ; to trick the complexity sorting
%t = shl <2 x i32> <i32 1, i32 1>, %c1
@@ -169,8 +169,8 @@ define <2 x i1> @foo1_and_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32>
define i1 @or_consts(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @or_consts(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 12
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 12
+; CHECK-NEXT: ret i1 [[OR]]
;
%t1 = and i32 4, %k
%t2 = icmp ne i32 %t1, 0
@@ -183,8 +183,8 @@ define i1 @or_consts(i32 %k, i32 %c1, i32 %c2) {
define i1 @or_consts_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @or_consts_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 12
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 12
+; CHECK-NEXT: ret i1 [[OR]]
;
%t1 = and i32 4, %k
%t2 = icmp ne i32 %t1, 0
@@ -197,8 +197,8 @@ define i1 @or_consts_logical(i32 %k, i32 %c1, i32 %c2) {
define <2 x i1> @or_consts_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {
; CHECK-LABEL: @or_consts_vector(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[K:%.*]], <i32 12, i32 12>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 12, i32 12>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 12, i32 12>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t1 = and <2 x i32> <i32 4, i32 4>, %k
%t2 = icmp ne <2 x i32> %t1, zeroinitializer
@@ -214,8 +214,8 @@ define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = shl i32 1, %c2
@@ -234,8 +234,8 @@ define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = shl i32 1, %c2
@@ -253,8 +253,8 @@ define <2 x i1> @foo1_or_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {
; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t = shl <2 x i32> <i32 1, i32 1>, %c1
%t4 = shl <2 x i32> <i32 1, i32 1>, %c2
@@ -274,8 +274,8 @@ define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%k2 = mul i32 %k, %k ; to trick the complexity sorting
%t = shl i32 1, %c1
@@ -296,8 +296,8 @@ define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%k2 = mul i32 %k, %k ; to trick the complexity sorting
%t = shl i32 1, %c1
@@ -317,8 +317,8 @@ define <2 x i1> @foo1_or_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32>
; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K2]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%k2 = mul <2 x i32> %k, %k ; to trick the complexity sorting
%t = shl <2 x i32> <i32 1, i32 1>, %c1
@@ -337,8 +337,8 @@ define i1 @foo1_and_signbit_lshr(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2
@@ -357,8 +357,8 @@ define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2
@@ -376,8 +376,8 @@ define <2 x i1> @foo1_and_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x
; CHECK-NEXT: [[T4:%.*]] = lshr <2 x i32> <i32 -2147483648, i32 -2147483648>, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t = shl <2 x i32> <i32 1, i32 1>, %c1
%t4 = lshr <2 x i32> <i32 -2147483648, i32 -2147483648>, %c2
@@ -395,8 +395,8 @@ define i1 @foo1_or_signbit_lshr(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2
@@ -415,8 +415,8 @@ define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t = shl i32 1, %c1
%t4 = lshr i32 -2147483648, %c2
@@ -434,8 +434,8 @@ define <2 x i1> @foo1_or_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i
; CHECK-NEXT: [[T4:%.*]] = lshr <2 x i32> <i32 -2147483648, i32 -2147483648>, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t = shl <2 x i32> <i32 1, i32 1>, %c1
%t4 = lshr <2 x i32> <i32 -2147483648, i32 -2147483648>, %c2
@@ -530,8 +530,8 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 %k, %c1
%t1 = icmp sgt i32 %t0, -1
@@ -564,8 +564,8 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 %k, %c1
%t1 = icmp slt i32 %t0, 0
@@ -580,8 +580,8 @@ define <2 x i1> @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_splat(
; CHECK-NEXT: [[T0:%.*]] = shl <2 x i32> [[K:%.*]], [[C1:%.*]]
; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[K]], [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[T0]], [[T2]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%t0 = shl <2 x i32> %k, %c1
%t1 = icmp slt <2 x i32> %t0, zeroinitializer
@@ -619,8 +619,8 @@ define i1 @foo1_and_extra_use_shl(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
store i32 %t0, ptr %p ; extra use of shl
@@ -641,8 +641,8 @@ define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
store i32 %t0, ptr %p ; extra use of shl
@@ -664,8 +664,8 @@ define i1 @foo1_and_extra_use_and(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i32 [[T2]], ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -687,8 +687,8 @@ define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -711,8 +711,8 @@ define i1 @foo1_and_extra_use_cmp(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i1 [[T3]], ptr [[P:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -735,8 +735,8 @@ define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -757,8 +757,8 @@ define i1 @foo1_and_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -779,8 +779,8 @@ define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i32 [[TMP1]], ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -802,8 +802,8 @@ define i1 @foo1_and_extra_use_and2(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i32 [[T4]], ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -825,8 +825,8 @@ define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i32 [[T4]], ptr [[P:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -849,8 +849,8 @@ define i1 @foo1_and_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i1 [[T5]], ptr [[P:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
@@ -873,8 +873,8 @@ define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {
; CHECK-NEXT: store i1 [[T5]], ptr [[P:%.*]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%t0 = shl i32 1, %c1
%t1 = shl i32 1, %c2
diff --git a/llvm/test/Transforms/InstCombine/or-fcmp.ll b/llvm/test/Transforms/InstCombine/or-fcmp.ll
index 45524a14cc74e..ffd927672b413 100644
--- a/llvm/test/Transforms/InstCombine/or-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/or-fcmp.ll
@@ -3,8 +3,8 @@
define i1 @PR1738(double %x, double %y) {
; CHECK-LABEL: @PR1738(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = fcmp uno double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = fcmp uno double %x, 0.0
%cmp2 = fcmp uno double %y, 0.0
@@ -28,8 +28,8 @@ define i1 @PR1738_logical(double %x, double %y) {
define <2 x i1> @PR1738_vec_undef(<2 x double> %x, <2 x double> %y) {
; CHECK-LABEL: @PR1738_vec_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <2 x double> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = fcmp uno <2 x double> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%cmp1 = fcmp uno <2 x double> %x, <double 0.0, double undef>
%cmp2 = fcmp uno <2 x double> %y, <double undef, double 0.0>
@@ -131,8 +131,8 @@ define <2 x i1> @PR41069_vec_commute(<2 x i1> %z, <2 x float> %c, <2 x float> %d
define i1 @fcmp_uno_nonzero(float %x, float %y) {
; CHECK-LABEL: @fcmp_uno_nonzero(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = fcmp uno float %x, 1.0
%cmp2 = fcmp uno float %y, 2.0
@@ -156,8 +156,8 @@ define i1 @fcmp_uno_nonzero_logical(float %x, float %y) {
define <3 x i1> @fcmp_uno_nonzero_vec(<3 x float> %x, <3 x float> %y) {
; CHECK-LABEL: @fcmp_uno_nonzero_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <3 x float> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = fcmp uno <3 x float> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%cmp1 = fcmp uno <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%cmp2 = fcmp uno <3 x float> %y, <float 3.0, float 2.0, float 1.0>
@@ -230,8 +230,8 @@ define i1 @auto_gen_1_logical_fmf(double %a, double %b) {
define i1 @auto_gen_2(double %a, double %b) {
; CHECK-LABEL: @auto_gen_2(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oeq double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -241,8 +241,8 @@ define i1 @auto_gen_2(double %a, double %b) {
define i1 @auto_gen_2_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_2_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oeq double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -252,8 +252,8 @@ define i1 @auto_gen_2_logical(double %a, double %b) {
define i1 @auto_gen_2_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_2_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oeq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oeq double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -296,8 +296,8 @@ define i1 @auto_gen_3_logical_fmf(double %a, double %b) {
define i1 @auto_gen_4(double %a, double %b) {
; CHECK-LABEL: @auto_gen_4(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ogt double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -307,8 +307,8 @@ define i1 @auto_gen_4(double %a, double %b) {
define i1 @auto_gen_4_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_4_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ogt double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -318,8 +318,8 @@ define i1 @auto_gen_4_logical(double %a, double %b) {
define i1 @auto_gen_4_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_4_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ogt double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -329,8 +329,8 @@ define i1 @auto_gen_4_logical_fmf(double %a, double %b) {
define i1 @auto_gen_5(double %a, double %b) {
; CHECK-LABEL: @auto_gen_5(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ogt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -340,8 +340,8 @@ define i1 @auto_gen_5(double %a, double %b) {
define i1 @auto_gen_5_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_5_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ogt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ogt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -351,8 +351,8 @@ define i1 @auto_gen_5_logical(double %a, double %b) {
define i1 @auto_gen_5_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_5_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ogt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ogt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ogt double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -395,8 +395,8 @@ define i1 @auto_gen_6_logical_fmf(double %a, double %b) {
define i1 @auto_gen_7(double %a, double %b) {
; CHECK-LABEL: @auto_gen_7(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -406,8 +406,8 @@ define i1 @auto_gen_7(double %a, double %b) {
define i1 @auto_gen_7_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_7_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -417,8 +417,8 @@ define i1 @auto_gen_7_logical(double %a, double %b) {
define i1 @auto_gen_7_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_7_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast oge double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -428,8 +428,8 @@ define i1 @auto_gen_7_logical_fmf(double %a, double %b) {
define i1 @auto_gen_8(double %a, double %b) {
; CHECK-LABEL: @auto_gen_8(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -439,8 +439,8 @@ define i1 @auto_gen_8(double %a, double %b) {
define i1 @auto_gen_8_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_8_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -450,8 +450,8 @@ define i1 @auto_gen_8_logical(double %a, double %b) {
define i1 @auto_gen_8_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_8_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -461,8 +461,8 @@ define i1 @auto_gen_8_logical_fmf(double %a, double %b) {
define i1 @auto_gen_9(double %a, double %b) {
; CHECK-LABEL: @auto_gen_9(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -472,8 +472,8 @@ define i1 @auto_gen_9(double %a, double %b) {
define i1 @auto_gen_9_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_9_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp oge double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -483,8 +483,8 @@ define i1 @auto_gen_9_logical(double %a, double %b) {
define i1 @auto_gen_9_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_9_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast oge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast oge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast oge double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -527,8 +527,8 @@ define i1 @auto_gen_10_logical_fmf(double %a, double %b) {
define i1 @auto_gen_11(double %a, double %b) {
; CHECK-LABEL: @auto_gen_11(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -538,8 +538,8 @@ define i1 @auto_gen_11(double %a, double %b) {
define i1 @auto_gen_11_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_11_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -549,8 +549,8 @@ define i1 @auto_gen_11_logical(double %a, double %b) {
define i1 @auto_gen_11_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_11_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast olt double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -560,8 +560,8 @@ define i1 @auto_gen_11_logical_fmf(double %a, double %b) {
define i1 @auto_gen_12(double %a, double %b) {
; CHECK-LABEL: @auto_gen_12(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -571,8 +571,8 @@ define i1 @auto_gen_12(double %a, double %b) {
define i1 @auto_gen_12_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_12_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -582,8 +582,8 @@ define i1 @auto_gen_12_logical(double %a, double %b) {
define i1 @auto_gen_12_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_12_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -593,8 +593,8 @@ define i1 @auto_gen_12_logical_fmf(double %a, double %b) {
define i1 @auto_gen_13(double %a, double %b) {
; CHECK-LABEL: @auto_gen_13(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -604,8 +604,8 @@ define i1 @auto_gen_13(double %a, double %b) {
define i1 @auto_gen_13_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_13_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -625,8 +625,8 @@ define i1 @auto_gen_13_logical_fmf(double %a, double %b) {
define i1 @auto_gen_14(double %a, double %b) {
; CHECK-LABEL: @auto_gen_14(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -636,8 +636,8 @@ define i1 @auto_gen_14(double %a, double %b) {
define i1 @auto_gen_14_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_14_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -647,8 +647,8 @@ define i1 @auto_gen_14_logical(double %a, double %b) {
define i1 @auto_gen_14_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_14_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -691,8 +691,8 @@ define i1 @auto_gen_15_logical_fmf(double %a, double %b) {
define i1 @auto_gen_16(double %a, double %b) {
; CHECK-LABEL: @auto_gen_16(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -702,8 +702,8 @@ define i1 @auto_gen_16(double %a, double %b) {
define i1 @auto_gen_16_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_16_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -713,8 +713,8 @@ define i1 @auto_gen_16_logical(double %a, double %b) {
define i1 @auto_gen_16_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_16_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -724,8 +724,8 @@ define i1 @auto_gen_16_logical_fmf(double %a, double %b) {
define i1 @auto_gen_17(double %a, double %b) {
; CHECK-LABEL: @auto_gen_17(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -735,8 +735,8 @@ define i1 @auto_gen_17(double %a, double %b) {
define i1 @auto_gen_17_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_17_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -756,8 +756,8 @@ define i1 @auto_gen_17_logical_fmf(double %a, double %b) {
define i1 @auto_gen_18(double %a, double %b) {
; CHECK-LABEL: @auto_gen_18(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -767,8 +767,8 @@ define i1 @auto_gen_18(double %a, double %b) {
define i1 @auto_gen_18_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_18_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -778,8 +778,8 @@ define i1 @auto_gen_18_logical(double %a, double %b) {
define i1 @auto_gen_18_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_18_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -789,8 +789,8 @@ define i1 @auto_gen_18_logical_fmf(double %a, double %b) {
define i1 @auto_gen_19(double %a, double %b) {
; CHECK-LABEL: @auto_gen_19(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -800,8 +800,8 @@ define i1 @auto_gen_19(double %a, double %b) {
define i1 @auto_gen_19_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_19_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -811,8 +811,8 @@ define i1 @auto_gen_19_logical(double %a, double %b) {
define i1 @auto_gen_19_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_19_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ole double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -822,8 +822,8 @@ define i1 @auto_gen_19_logical_fmf(double %a, double %b) {
define i1 @auto_gen_20(double %a, double %b) {
; CHECK-LABEL: @auto_gen_20(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -833,8 +833,8 @@ define i1 @auto_gen_20(double %a, double %b) {
define i1 @auto_gen_20_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_20_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -844,8 +844,8 @@ define i1 @auto_gen_20_logical(double %a, double %b) {
define i1 @auto_gen_20_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_20_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ole double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ole double %a, %b
%cmp1 = fcmp fast ole double %a, %b
@@ -888,8 +888,8 @@ define i1 @auto_gen_21_logical_fmf(double %a, double %b) {
define i1 @auto_gen_22(double %a, double %b) {
; CHECK-LABEL: @auto_gen_22(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -899,8 +899,8 @@ define i1 @auto_gen_22(double %a, double %b) {
define i1 @auto_gen_22_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_22_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -910,8 +910,8 @@ define i1 @auto_gen_22_logical(double %a, double %b) {
define i1 @auto_gen_22_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_22_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -921,8 +921,8 @@ define i1 @auto_gen_22_logical_fmf(double %a, double %b) {
define i1 @auto_gen_23(double %a, double %b) {
; CHECK-LABEL: @auto_gen_23(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -932,8 +932,8 @@ define i1 @auto_gen_23(double %a, double %b) {
define i1 @auto_gen_23_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_23_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -943,8 +943,8 @@ define i1 @auto_gen_23_logical(double %a, double %b) {
define i1 @auto_gen_23_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_23_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast one double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -954,8 +954,8 @@ define i1 @auto_gen_23_logical_fmf(double %a, double %b) {
define i1 @auto_gen_24(double %a, double %b) {
; CHECK-LABEL: @auto_gen_24(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -965,8 +965,8 @@ define i1 @auto_gen_24(double %a, double %b) {
define i1 @auto_gen_24_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_24_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -976,8 +976,8 @@ define i1 @auto_gen_24_logical(double %a, double %b) {
define i1 @auto_gen_24_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_24_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -987,8 +987,8 @@ define i1 @auto_gen_24_logical_fmf(double %a, double %b) {
define i1 @auto_gen_25(double %a, double %b) {
; CHECK-LABEL: @auto_gen_25(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -998,8 +998,8 @@ define i1 @auto_gen_25(double %a, double %b) {
define i1 @auto_gen_25_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_25_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1009,8 +1009,8 @@ define i1 @auto_gen_25_logical(double %a, double %b) {
define i1 @auto_gen_25_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_25_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast one double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -1020,8 +1020,8 @@ define i1 @auto_gen_25_logical_fmf(double %a, double %b) {
define i1 @auto_gen_26(double %a, double %b) {
; CHECK-LABEL: @auto_gen_26(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -1031,8 +1031,8 @@ define i1 @auto_gen_26(double %a, double %b) {
define i1 @auto_gen_26_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_26_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -1042,8 +1042,8 @@ define i1 @auto_gen_26_logical(double %a, double %b) {
define i1 @auto_gen_26_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_26_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp fast ole double %a, %b
@@ -1053,8 +1053,8 @@ define i1 @auto_gen_26_logical_fmf(double %a, double %b) {
define i1 @auto_gen_27(double %a, double %b) {
; CHECK-LABEL: @auto_gen_27(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -1064,8 +1064,8 @@ define i1 @auto_gen_27(double %a, double %b) {
define i1 @auto_gen_27_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_27_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp one double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -1075,8 +1075,8 @@ define i1 @auto_gen_27_logical(double %a, double %b) {
define i1 @auto_gen_27_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_27_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast one double %a, %b
%cmp1 = fcmp fast one double %a, %b
@@ -1119,8 +1119,8 @@ define i1 @auto_gen_28_logical_fmf(double %a, double %b) {
define i1 @auto_gen_29(double %a, double %b) {
; CHECK-LABEL: @auto_gen_29(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -1130,8 +1130,8 @@ define i1 @auto_gen_29(double %a, double %b) {
define i1 @auto_gen_29_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_29_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -1151,8 +1151,8 @@ define i1 @auto_gen_29_logical_fmf(double %a, double %b) {
define i1 @auto_gen_30(double %a, double %b) {
; CHECK-LABEL: @auto_gen_30(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -1162,8 +1162,8 @@ define i1 @auto_gen_30(double %a, double %b) {
define i1 @auto_gen_30_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_30_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -1173,8 +1173,8 @@ define i1 @auto_gen_30_logical(double %a, double %b) {
define i1 @auto_gen_30_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_30_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -1184,8 +1184,8 @@ define i1 @auto_gen_30_logical_fmf(double %a, double %b) {
define i1 @auto_gen_31(double %a, double %b) {
; CHECK-LABEL: @auto_gen_31(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -1195,8 +1195,8 @@ define i1 @auto_gen_31(double %a, double %b) {
define i1 @auto_gen_31_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_31_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -1216,8 +1216,8 @@ define i1 @auto_gen_31_logical_fmf(double %a, double %b) {
define i1 @auto_gen_32(double %a, double %b) {
; CHECK-LABEL: @auto_gen_32(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1227,8 +1227,8 @@ define i1 @auto_gen_32(double %a, double %b) {
define i1 @auto_gen_32_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_32_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1238,8 +1238,8 @@ define i1 @auto_gen_32_logical(double %a, double %b) {
define i1 @auto_gen_32_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_32_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -1249,8 +1249,8 @@ define i1 @auto_gen_32_logical_fmf(double %a, double %b) {
define i1 @auto_gen_33(double %a, double %b) {
; CHECK-LABEL: @auto_gen_33(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -1260,8 +1260,8 @@ define i1 @auto_gen_33(double %a, double %b) {
define i1 @auto_gen_33_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_33_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -1281,8 +1281,8 @@ define i1 @auto_gen_33_logical_fmf(double %a, double %b) {
define i1 @auto_gen_34(double %a, double %b) {
; CHECK-LABEL: @auto_gen_34(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -1292,8 +1292,8 @@ define i1 @auto_gen_34(double %a, double %b) {
define i1 @auto_gen_34_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_34_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -1303,8 +1303,8 @@ define i1 @auto_gen_34_logical(double %a, double %b) {
define i1 @auto_gen_34_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_34_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp fast one double %a, %b
@@ -1314,8 +1314,8 @@ define i1 @auto_gen_34_logical_fmf(double %a, double %b) {
define i1 @auto_gen_35(double %a, double %b) {
; CHECK-LABEL: @auto_gen_35(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp ord double %a, %b
@@ -1325,8 +1325,8 @@ define i1 @auto_gen_35(double %a, double %b) {
define i1 @auto_gen_35_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_35_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ord double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ord double %a, %b
%cmp1 = fcmp ord double %a, %b
@@ -1379,8 +1379,8 @@ define i1 @auto_gen_36_logical_fmf(double %a, double %b) {
define i1 @auto_gen_37(double %a, double %b) {
; CHECK-LABEL: @auto_gen_37(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -1390,8 +1390,8 @@ define i1 @auto_gen_37(double %a, double %b) {
define i1 @auto_gen_37_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_37_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -1401,8 +1401,8 @@ define i1 @auto_gen_37_logical(double %a, double %b) {
define i1 @auto_gen_37_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_37_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ueq double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -1412,8 +1412,8 @@ define i1 @auto_gen_37_logical_fmf(double %a, double %b) {
define i1 @auto_gen_38(double %a, double %b) {
; CHECK-LABEL: @auto_gen_38(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -1423,8 +1423,8 @@ define i1 @auto_gen_38(double %a, double %b) {
define i1 @auto_gen_38_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_38_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -1434,8 +1434,8 @@ define i1 @auto_gen_38_logical(double %a, double %b) {
define i1 @auto_gen_38_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_38_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -1445,8 +1445,8 @@ define i1 @auto_gen_38_logical_fmf(double %a, double %b) {
define i1 @auto_gen_39(double %a, double %b) {
; CHECK-LABEL: @auto_gen_39(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -1456,8 +1456,8 @@ define i1 @auto_gen_39(double %a, double %b) {
define i1 @auto_gen_39_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_39_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -1467,8 +1467,8 @@ define i1 @auto_gen_39_logical(double %a, double %b) {
define i1 @auto_gen_39_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_39_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ueq double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -1478,8 +1478,8 @@ define i1 @auto_gen_39_logical_fmf(double %a, double %b) {
define i1 @auto_gen_40(double %a, double %b) {
; CHECK-LABEL: @auto_gen_40(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1489,8 +1489,8 @@ define i1 @auto_gen_40(double %a, double %b) {
define i1 @auto_gen_40_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_40_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1500,8 +1500,8 @@ define i1 @auto_gen_40_logical(double %a, double %b) {
define i1 @auto_gen_40_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_40_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -1511,8 +1511,8 @@ define i1 @auto_gen_40_logical_fmf(double %a, double %b) {
define i1 @auto_gen_41(double %a, double %b) {
; CHECK-LABEL: @auto_gen_41(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -1522,8 +1522,8 @@ define i1 @auto_gen_41(double %a, double %b) {
define i1 @auto_gen_41_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_41_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -1533,8 +1533,8 @@ define i1 @auto_gen_41_logical(double %a, double %b) {
define i1 @auto_gen_41_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_41_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ueq double %a, %b
%cmp1 = fcmp fast ole double %a, %b
@@ -1604,8 +1604,8 @@ define i1 @auto_gen_43_logical_fmf(double %a, double %b) {
define i1 @auto_gen_44(double %a, double %b) {
; CHECK-LABEL: @auto_gen_44(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -1615,8 +1615,8 @@ define i1 @auto_gen_44(double %a, double %b) {
define i1 @auto_gen_44_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_44_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -1626,8 +1626,8 @@ define i1 @auto_gen_44_logical(double %a, double %b) {
define i1 @auto_gen_44_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_44_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ueq double %a, %b
%cmp1 = fcmp fast ueq double %a, %b
@@ -1670,8 +1670,8 @@ define i1 @auto_gen_45_logical_fmf(double %a, double %b) {
define i1 @auto_gen_46(double %a, double %b) {
; CHECK-LABEL: @auto_gen_46(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -1681,8 +1681,8 @@ define i1 @auto_gen_46(double %a, double %b) {
define i1 @auto_gen_46_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_46_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -1692,8 +1692,8 @@ define i1 @auto_gen_46_logical(double %a, double %b) {
define i1 @auto_gen_46_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_46_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -1703,8 +1703,8 @@ define i1 @auto_gen_46_logical_fmf(double %a, double %b) {
define i1 @auto_gen_47(double %a, double %b) {
; CHECK-LABEL: @auto_gen_47(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -1714,8 +1714,8 @@ define i1 @auto_gen_47(double %a, double %b) {
define i1 @auto_gen_47_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_47_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -1725,8 +1725,8 @@ define i1 @auto_gen_47_logical(double %a, double %b) {
define i1 @auto_gen_47_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_47_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ugt double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -1736,8 +1736,8 @@ define i1 @auto_gen_47_logical_fmf(double %a, double %b) {
define i1 @auto_gen_48(double %a, double %b) {
; CHECK-LABEL: @auto_gen_48(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -1747,8 +1747,8 @@ define i1 @auto_gen_48(double %a, double %b) {
define i1 @auto_gen_48_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_48_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -1758,8 +1758,8 @@ define i1 @auto_gen_48_logical(double %a, double %b) {
define i1 @auto_gen_48_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_48_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -1769,8 +1769,8 @@ define i1 @auto_gen_48_logical_fmf(double %a, double %b) {
define i1 @auto_gen_49(double %a, double %b) {
; CHECK-LABEL: @auto_gen_49(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1780,8 +1780,8 @@ define i1 @auto_gen_49(double %a, double %b) {
define i1 @auto_gen_49_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_49_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -1791,8 +1791,8 @@ define i1 @auto_gen_49_logical(double %a, double %b) {
define i1 @auto_gen_49_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_49_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ugt double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -1832,8 +1832,8 @@ define i1 @auto_gen_50_logical_fmf(double %a, double %b) {
define i1 @auto_gen_51(double %a, double %b) {
; CHECK-LABEL: @auto_gen_51(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -1843,8 +1843,8 @@ define i1 @auto_gen_51(double %a, double %b) {
define i1 @auto_gen_51_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_51_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -1854,8 +1854,8 @@ define i1 @auto_gen_51_logical(double %a, double %b) {
define i1 @auto_gen_51_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_51_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ugt double %a, %b
%cmp1 = fcmp fast one double %a, %b
@@ -1895,8 +1895,8 @@ define i1 @auto_gen_52_logical_fmf(double %a, double %b) {
define i1 @auto_gen_53(double %a, double %b) {
; CHECK-LABEL: @auto_gen_53(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -1906,8 +1906,8 @@ define i1 @auto_gen_53(double %a, double %b) {
define i1 @auto_gen_53_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_53_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -1917,8 +1917,8 @@ define i1 @auto_gen_53_logical(double %a, double %b) {
define i1 @auto_gen_53_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_53_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ugt double %a, %b
%cmp1 = fcmp fast ueq double %a, %b
@@ -1928,8 +1928,8 @@ define i1 @auto_gen_53_logical_fmf(double %a, double %b) {
define i1 @auto_gen_54(double %a, double %b) {
; CHECK-LABEL: @auto_gen_54(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -1939,8 +1939,8 @@ define i1 @auto_gen_54(double %a, double %b) {
define i1 @auto_gen_54_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_54_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -1950,8 +1950,8 @@ define i1 @auto_gen_54_logical(double %a, double %b) {
define i1 @auto_gen_54_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_54_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ugt double %a, %b
%cmp1 = fcmp fast ugt double %a, %b
@@ -1994,8 +1994,8 @@ define i1 @auto_gen_55_logical_fmf(double %a, double %b) {
define i1 @auto_gen_56(double %a, double %b) {
; CHECK-LABEL: @auto_gen_56(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -2005,8 +2005,8 @@ define i1 @auto_gen_56(double %a, double %b) {
define i1 @auto_gen_56_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_56_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -2016,8 +2016,8 @@ define i1 @auto_gen_56_logical(double %a, double %b) {
define i1 @auto_gen_56_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_56_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -2027,8 +2027,8 @@ define i1 @auto_gen_56_logical_fmf(double %a, double %b) {
define i1 @auto_gen_57(double %a, double %b) {
; CHECK-LABEL: @auto_gen_57(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -2038,8 +2038,8 @@ define i1 @auto_gen_57(double %a, double %b) {
define i1 @auto_gen_57_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_57_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -2049,8 +2049,8 @@ define i1 @auto_gen_57_logical(double %a, double %b) {
define i1 @auto_gen_57_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_57_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast uge double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -2060,8 +2060,8 @@ define i1 @auto_gen_57_logical_fmf(double %a, double %b) {
define i1 @auto_gen_58(double %a, double %b) {
; CHECK-LABEL: @auto_gen_58(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -2071,8 +2071,8 @@ define i1 @auto_gen_58(double %a, double %b) {
define i1 @auto_gen_58_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_58_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -2082,8 +2082,8 @@ define i1 @auto_gen_58_logical(double %a, double %b) {
define i1 @auto_gen_58_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_58_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -2213,8 +2213,8 @@ define i1 @auto_gen_62_logical_fmf(double %a, double %b) {
define i1 @auto_gen_63(double %a, double %b) {
; CHECK-LABEL: @auto_gen_63(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -2224,8 +2224,8 @@ define i1 @auto_gen_63(double %a, double %b) {
define i1 @auto_gen_63_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_63_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -2235,8 +2235,8 @@ define i1 @auto_gen_63_logical(double %a, double %b) {
define i1 @auto_gen_63_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_63_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast uge double %a, %b
%cmp1 = fcmp fast ueq double %a, %b
@@ -2246,8 +2246,8 @@ define i1 @auto_gen_63_logical_fmf(double %a, double %b) {
define i1 @auto_gen_64(double %a, double %b) {
; CHECK-LABEL: @auto_gen_64(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -2257,8 +2257,8 @@ define i1 @auto_gen_64(double %a, double %b) {
define i1 @auto_gen_64_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_64_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -2268,8 +2268,8 @@ define i1 @auto_gen_64_logical(double %a, double %b) {
define i1 @auto_gen_64_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_64_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp fast ugt double %a, %b
@@ -2279,8 +2279,8 @@ define i1 @auto_gen_64_logical_fmf(double %a, double %b) {
define i1 @auto_gen_65(double %a, double %b) {
; CHECK-LABEL: @auto_gen_65(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp uge double %a, %b
@@ -2290,8 +2290,8 @@ define i1 @auto_gen_65(double %a, double %b) {
define i1 @auto_gen_65_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_65_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uge double %a, %b
%cmp1 = fcmp uge double %a, %b
@@ -2301,8 +2301,8 @@ define i1 @auto_gen_65_logical(double %a, double %b) {
define i1 @auto_gen_65_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_65_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast uge double %a, %b
%cmp1 = fcmp fast uge double %a, %b
@@ -2345,8 +2345,8 @@ define i1 @auto_gen_66_logical_fmf(double %a, double %b) {
define i1 @auto_gen_67(double %a, double %b) {
; CHECK-LABEL: @auto_gen_67(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -2356,8 +2356,8 @@ define i1 @auto_gen_67(double %a, double %b) {
define i1 @auto_gen_67_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_67_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -2367,8 +2367,8 @@ define i1 @auto_gen_67_logical(double %a, double %b) {
define i1 @auto_gen_67_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_67_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ult double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -2378,8 +2378,8 @@ define i1 @auto_gen_67_logical_fmf(double %a, double %b) {
define i1 @auto_gen_68(double %a, double %b) {
; CHECK-LABEL: @auto_gen_68(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -2389,8 +2389,8 @@ define i1 @auto_gen_68(double %a, double %b) {
define i1 @auto_gen_68_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_68_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -2400,8 +2400,8 @@ define i1 @auto_gen_68_logical(double %a, double %b) {
define i1 @auto_gen_68_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_68_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -2441,8 +2441,8 @@ define i1 @auto_gen_69_logical_fmf(double %a, double %b) {
define i1 @auto_gen_70(double %a, double %b) {
; CHECK-LABEL: @auto_gen_70(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -2452,8 +2452,8 @@ define i1 @auto_gen_70(double %a, double %b) {
define i1 @auto_gen_70_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_70_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -2463,8 +2463,8 @@ define i1 @auto_gen_70_logical(double %a, double %b) {
define i1 @auto_gen_70_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_70_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -2474,8 +2474,8 @@ define i1 @auto_gen_70_logical_fmf(double %a, double %b) {
define i1 @auto_gen_71(double %a, double %b) {
; CHECK-LABEL: @auto_gen_71(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -2485,8 +2485,8 @@ define i1 @auto_gen_71(double %a, double %b) {
define i1 @auto_gen_71_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_71_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -2496,8 +2496,8 @@ define i1 @auto_gen_71_logical(double %a, double %b) {
define i1 @auto_gen_71_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_71_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ult double %a, %b
%cmp1 = fcmp fast ole double %a, %b
@@ -2507,8 +2507,8 @@ define i1 @auto_gen_71_logical_fmf(double %a, double %b) {
define i1 @auto_gen_72(double %a, double %b) {
; CHECK-LABEL: @auto_gen_72(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -2518,8 +2518,8 @@ define i1 @auto_gen_72(double %a, double %b) {
define i1 @auto_gen_72_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_72_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -2529,8 +2529,8 @@ define i1 @auto_gen_72_logical(double %a, double %b) {
define i1 @auto_gen_72_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_72_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp fast one double %a, %b
@@ -2570,8 +2570,8 @@ define i1 @auto_gen_73_logical_fmf(double %a, double %b) {
define i1 @auto_gen_74(double %a, double %b) {
; CHECK-LABEL: @auto_gen_74(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -2581,8 +2581,8 @@ define i1 @auto_gen_74(double %a, double %b) {
define i1 @auto_gen_74_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_74_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -2592,8 +2592,8 @@ define i1 @auto_gen_74_logical(double %a, double %b) {
define i1 @auto_gen_74_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_74_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp fast ueq double %a, %b
@@ -2603,8 +2603,8 @@ define i1 @auto_gen_74_logical_fmf(double %a, double %b) {
define i1 @auto_gen_75(double %a, double %b) {
; CHECK-LABEL: @auto_gen_75(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -2614,8 +2614,8 @@ define i1 @auto_gen_75(double %a, double %b) {
define i1 @auto_gen_75_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_75_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -2625,8 +2625,8 @@ define i1 @auto_gen_75_logical(double %a, double %b) {
define i1 @auto_gen_75_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_75_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ult double %a, %b
%cmp1 = fcmp fast ugt double %a, %b
@@ -2666,8 +2666,8 @@ define i1 @auto_gen_76_logical_fmf(double %a, double %b) {
define i1 @auto_gen_77(double %a, double %b) {
; CHECK-LABEL: @auto_gen_77(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -2677,8 +2677,8 @@ define i1 @auto_gen_77(double %a, double %b) {
define i1 @auto_gen_77_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_77_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ult double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -2688,8 +2688,8 @@ define i1 @auto_gen_77_logical(double %a, double %b) {
define i1 @auto_gen_77_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_77_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ult double %a, %b
%cmp1 = fcmp fast ult double %a, %b
@@ -2732,8 +2732,8 @@ define i1 @auto_gen_78_logical_fmf(double %a, double %b) {
define i1 @auto_gen_79(double %a, double %b) {
; CHECK-LABEL: @auto_gen_79(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -2743,8 +2743,8 @@ define i1 @auto_gen_79(double %a, double %b) {
define i1 @auto_gen_79_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_79_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -2754,8 +2754,8 @@ define i1 @auto_gen_79_logical(double %a, double %b) {
define i1 @auto_gen_79_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_79_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ule double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -2825,8 +2825,8 @@ define i1 @auto_gen_81_logical_fmf(double %a, double %b) {
define i1 @auto_gen_82(double %a, double %b) {
; CHECK-LABEL: @auto_gen_82(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -2836,8 +2836,8 @@ define i1 @auto_gen_82(double %a, double %b) {
define i1 @auto_gen_82_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_82_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -2847,8 +2847,8 @@ define i1 @auto_gen_82_logical(double %a, double %b) {
define i1 @auto_gen_82_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_82_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -2858,8 +2858,8 @@ define i1 @auto_gen_82_logical_fmf(double %a, double %b) {
define i1 @auto_gen_83(double %a, double %b) {
; CHECK-LABEL: @auto_gen_83(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -2869,8 +2869,8 @@ define i1 @auto_gen_83(double %a, double %b) {
define i1 @auto_gen_83_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_83_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -2880,8 +2880,8 @@ define i1 @auto_gen_83_logical(double %a, double %b) {
define i1 @auto_gen_83_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_83_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ule double %a, %b
%cmp1 = fcmp fast ole double %a, %b
@@ -2951,8 +2951,8 @@ define i1 @auto_gen_85_logical_fmf(double %a, double %b) {
define i1 @auto_gen_86(double %a, double %b) {
; CHECK-LABEL: @auto_gen_86(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -2962,8 +2962,8 @@ define i1 @auto_gen_86(double %a, double %b) {
define i1 @auto_gen_86_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_86_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -2973,8 +2973,8 @@ define i1 @auto_gen_86_logical(double %a, double %b) {
define i1 @auto_gen_86_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_86_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp fast ueq double %a, %b
@@ -3044,8 +3044,8 @@ define i1 @auto_gen_88_logical_fmf(double %a, double %b) {
define i1 @auto_gen_89(double %a, double %b) {
; CHECK-LABEL: @auto_gen_89(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -3055,8 +3055,8 @@ define i1 @auto_gen_89(double %a, double %b) {
define i1 @auto_gen_89_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_89_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -3066,8 +3066,8 @@ define i1 @auto_gen_89_logical(double %a, double %b) {
define i1 @auto_gen_89_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_89_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast ule double %a, %b
%cmp1 = fcmp fast ult double %a, %b
@@ -3077,8 +3077,8 @@ define i1 @auto_gen_89_logical_fmf(double %a, double %b) {
define i1 @auto_gen_90(double %a, double %b) {
; CHECK-LABEL: @auto_gen_90(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ule double %a, %b
@@ -3088,8 +3088,8 @@ define i1 @auto_gen_90(double %a, double %b) {
define i1 @auto_gen_90_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_90_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp ule double %a, %b
@@ -3099,8 +3099,8 @@ define i1 @auto_gen_90_logical(double %a, double %b) {
define i1 @auto_gen_90_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_90_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ule double %a, %b
%cmp1 = fcmp fast ule double %a, %b
@@ -3173,8 +3173,8 @@ define i1 @auto_gen_92_logical_fmf(double %a, double %b) {
define i1 @auto_gen_93(double %a, double %b) {
; CHECK-LABEL: @auto_gen_93(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -3184,8 +3184,8 @@ define i1 @auto_gen_93(double %a, double %b) {
define i1 @auto_gen_93_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_93_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -3195,8 +3195,8 @@ define i1 @auto_gen_93_logical(double %a, double %b) {
define i1 @auto_gen_93_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_93_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast une double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -3236,8 +3236,8 @@ define i1 @auto_gen_94_logical_fmf(double %a, double %b) {
define i1 @auto_gen_95(double %a, double %b) {
; CHECK-LABEL: @auto_gen_95(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -3247,8 +3247,8 @@ define i1 @auto_gen_95(double %a, double %b) {
define i1 @auto_gen_95_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_95_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -3258,8 +3258,8 @@ define i1 @auto_gen_95_logical(double %a, double %b) {
define i1 @auto_gen_95_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_95_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast une double %a, %b
%cmp1 = fcmp fast olt double %a, %b
@@ -3299,8 +3299,8 @@ define i1 @auto_gen_96_logical_fmf(double %a, double %b) {
define i1 @auto_gen_97(double %a, double %b) {
; CHECK-LABEL: @auto_gen_97(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -3310,8 +3310,8 @@ define i1 @auto_gen_97(double %a, double %b) {
define i1 @auto_gen_97_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_97_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -3321,8 +3321,8 @@ define i1 @auto_gen_97_logical(double %a, double %b) {
define i1 @auto_gen_97_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_97_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast une double %a, %b
%cmp1 = fcmp fast one double %a, %b
@@ -3392,8 +3392,8 @@ define i1 @auto_gen_99_logical_fmf(double %a, double %b) {
define i1 @auto_gen_100(double %a, double %b) {
; CHECK-LABEL: @auto_gen_100(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -3403,8 +3403,8 @@ define i1 @auto_gen_100(double %a, double %b) {
define i1 @auto_gen_100_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_100_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -3414,8 +3414,8 @@ define i1 @auto_gen_100_logical(double %a, double %b) {
define i1 @auto_gen_100_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_100_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp fast ugt double %a, %b
@@ -3455,8 +3455,8 @@ define i1 @auto_gen_101_logical_fmf(double %a, double %b) {
define i1 @auto_gen_102(double %a, double %b) {
; CHECK-LABEL: @auto_gen_102(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -3466,8 +3466,8 @@ define i1 @auto_gen_102(double %a, double %b) {
define i1 @auto_gen_102_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_102_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -3477,8 +3477,8 @@ define i1 @auto_gen_102_logical(double %a, double %b) {
define i1 @auto_gen_102_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_102_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp fast ult double %a, %b
@@ -3518,8 +3518,8 @@ define i1 @auto_gen_103_logical_fmf(double %a, double %b) {
define i1 @auto_gen_104(double %a, double %b) {
; CHECK-LABEL: @auto_gen_104(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp une double %a, %b
@@ -3529,8 +3529,8 @@ define i1 @auto_gen_104(double %a, double %b) {
define i1 @auto_gen_104_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_104_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp une double %a, %b
@@ -3540,8 +3540,8 @@ define i1 @auto_gen_104_logical(double %a, double %b) {
define i1 @auto_gen_104_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_104_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp une double %a, %b
%cmp1 = fcmp fast une double %a, %b
@@ -3583,8 +3583,8 @@ define i1 @auto_gen_105_logical_fmf(double %a, double %b) {
define i1 @auto_gen_106(double %a, double %b) {
; CHECK-LABEL: @auto_gen_106(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -3594,8 +3594,8 @@ define i1 @auto_gen_106(double %a, double %b) {
define i1 @auto_gen_106_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_106_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp oeq double %a, %b
@@ -3605,8 +3605,8 @@ define i1 @auto_gen_106_logical(double %a, double %b) {
define i1 @auto_gen_106_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_106_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp fast oeq double %a, %b
@@ -3616,8 +3616,8 @@ define i1 @auto_gen_106_logical_fmf(double %a, double %b) {
define i1 @auto_gen_107(double %a, double %b) {
; CHECK-LABEL: @auto_gen_107(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -3627,8 +3627,8 @@ define i1 @auto_gen_107(double %a, double %b) {
define i1 @auto_gen_107_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_107_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -3649,8 +3649,8 @@ define i1 @auto_gen_107_logical_fmf(double %a, double %b) {
define i1 @auto_gen_108(double %a, double %b) {
; CHECK-LABEL: @auto_gen_108(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -3660,8 +3660,8 @@ define i1 @auto_gen_108(double %a, double %b) {
define i1 @auto_gen_108_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_108_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp oge double %a, %b
@@ -3671,8 +3671,8 @@ define i1 @auto_gen_108_logical(double %a, double %b) {
define i1 @auto_gen_108_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_108_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp fast oge double %a, %b
@@ -3682,8 +3682,8 @@ define i1 @auto_gen_108_logical_fmf(double %a, double %b) {
define i1 @auto_gen_109(double %a, double %b) {
; CHECK-LABEL: @auto_gen_109(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -3693,8 +3693,8 @@ define i1 @auto_gen_109(double %a, double %b) {
define i1 @auto_gen_109_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_109_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp olt double %a, %b
@@ -3715,8 +3715,8 @@ define i1 @auto_gen_109_logical_fmf(double %a, double %b) {
define i1 @auto_gen_110(double %a, double %b) {
; CHECK-LABEL: @auto_gen_110(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -3726,8 +3726,8 @@ define i1 @auto_gen_110(double %a, double %b) {
define i1 @auto_gen_110_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_110_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ole double %a, %b
@@ -3737,8 +3737,8 @@ define i1 @auto_gen_110_logical(double %a, double %b) {
define i1 @auto_gen_110_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_110_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp fast ole double %a, %b
@@ -3748,8 +3748,8 @@ define i1 @auto_gen_110_logical_fmf(double %a, double %b) {
define i1 @auto_gen_111(double %a, double %b) {
; CHECK-LABEL: @auto_gen_111(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -3759,8 +3759,8 @@ define i1 @auto_gen_111(double %a, double %b) {
define i1 @auto_gen_111_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_111_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp one double %a, %b
@@ -3811,8 +3811,8 @@ define i1 @auto_gen_112_logical_fmf(double %a, double %b) {
define i1 @auto_gen_113(double %a, double %b) {
; CHECK-LABEL: @auto_gen_113(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -3822,8 +3822,8 @@ define i1 @auto_gen_113(double %a, double %b) {
define i1 @auto_gen_113_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_113_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ueq double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ueq double %a, %b
@@ -3844,8 +3844,8 @@ define i1 @auto_gen_113_logical_fmf(double %a, double %b) {
define i1 @auto_gen_114(double %a, double %b) {
; CHECK-LABEL: @auto_gen_114(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -3855,8 +3855,8 @@ define i1 @auto_gen_114(double %a, double %b) {
define i1 @auto_gen_114_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_114_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ugt double %a, %b
@@ -3866,8 +3866,8 @@ define i1 @auto_gen_114_logical(double %a, double %b) {
define i1 @auto_gen_114_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_114_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ugt double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp fast ugt double %a, %b
@@ -3877,8 +3877,8 @@ define i1 @auto_gen_114_logical_fmf(double %a, double %b) {
define i1 @auto_gen_115(double %a, double %b) {
; CHECK-LABEL: @auto_gen_115(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp uge double %a, %b
@@ -3888,8 +3888,8 @@ define i1 @auto_gen_115(double %a, double %b) {
define i1 @auto_gen_115_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_115_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uge double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp uge double %a, %b
@@ -3910,8 +3910,8 @@ define i1 @auto_gen_115_logical_fmf(double %a, double %b) {
define i1 @auto_gen_116(double %a, double %b) {
; CHECK-LABEL: @auto_gen_116(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -3921,8 +3921,8 @@ define i1 @auto_gen_116(double %a, double %b) {
define i1 @auto_gen_116_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_116_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ult double %a, %b
@@ -3932,8 +3932,8 @@ define i1 @auto_gen_116_logical(double %a, double %b) {
define i1 @auto_gen_116_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_116_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ult double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp fast ult double %a, %b
@@ -3943,8 +3943,8 @@ define i1 @auto_gen_116_logical_fmf(double %a, double %b) {
define i1 @auto_gen_117(double %a, double %b) {
; CHECK-LABEL: @auto_gen_117(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ule double %a, %b
@@ -3954,8 +3954,8 @@ define i1 @auto_gen_117(double %a, double %b) {
define i1 @auto_gen_117_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_117_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp ule double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp ule double %a, %b
@@ -3976,8 +3976,8 @@ define i1 @auto_gen_117_logical_fmf(double %a, double %b) {
define i1 @auto_gen_118(double %a, double %b) {
; CHECK-LABEL: @auto_gen_118(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp une double %a, %b
@@ -3987,8 +3987,8 @@ define i1 @auto_gen_118(double %a, double %b) {
define i1 @auto_gen_118_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_118_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp une double %a, %b
@@ -3998,8 +3998,8 @@ define i1 @auto_gen_118_logical(double %a, double %b) {
define i1 @auto_gen_118_logical_fmf(double %a, double %b) {
; CHECK-LABEL: @auto_gen_118_logical_fmf(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp une double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp fast une double %a, %b
@@ -4009,8 +4009,8 @@ define i1 @auto_gen_118_logical_fmf(double %a, double %b) {
define i1 @auto_gen_119(double %a, double %b) {
; CHECK-LABEL: @auto_gen_119(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp uno double %a, %b
@@ -4020,8 +4020,8 @@ define i1 @auto_gen_119(double %a, double %b) {
define i1 @auto_gen_119_logical(double %a, double %b) {
; CHECK-LABEL: @auto_gen_119_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp uno double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp uno double %a, %b
%cmp1 = fcmp uno double %a, %b
@@ -4521,8 +4521,8 @@ define i1 @auto_gen_135_logical_fmf(double %a, double %b) {
define i1 @intersect_fmf_1(double %a, double %b) {
; CHECK-LABEL: @intersect_fmf_1(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp fast one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast olt double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -4532,8 +4532,8 @@ define i1 @intersect_fmf_1(double %a, double %b) {
define i1 @intersect_fmf_2(double %a, double %b) {
; CHECK-LABEL: @intersect_fmf_2(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp fast olt double %a, %b
%cmp1 = fcmp ogt double %a, %b
@@ -4543,8 +4543,8 @@ define i1 @intersect_fmf_2(double %a, double %b) {
define i1 @intersect_fmf_3(double %a, double %b) {
; CHECK-LABEL: @intersect_fmf_3(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp olt double %a, %b
%cmp1 = fcmp fast ogt double %a, %b
@@ -4554,8 +4554,8 @@ define i1 @intersect_fmf_3(double %a, double %b) {
define i1 @intersect_fmf_4(double %a, double %b) {
; CHECK-LABEL: @intersect_fmf_4(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = fcmp one double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[RETVAL]]
;
%cmp = fcmp ninf olt double %a, %b
%cmp1 = fcmp nnan ogt double %a, %b
diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index 25cf241f44c07..fd53783a06f9d 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -27,8 +27,8 @@ define i32 @test13(i32 %A) {
define i1 @test14(i32 %A, i32 %B) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp ult i32 %A, %B
%C2 = icmp ugt i32 %A, %B
@@ -39,8 +39,8 @@ define i1 @test14(i32 %A, i32 %B) {
define i1 @test14_commuted(i32 %A, i32 %B) {
; CHECK-LABEL: @test14_commuted(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp ult i32 %A, %B
%C2 = icmp ult i32 %B, %A
@@ -51,8 +51,8 @@ define i1 @test14_commuted(i32 %A, i32 %B) {
define i1 @test14_logical(i32 %A, i32 %B) {
; CHECK-LABEL: @test14_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp ult i32 %A, %B
%C2 = icmp ugt i32 %A, %B
@@ -63,8 +63,8 @@ define i1 @test14_logical(i32 %A, i32 %B) {
define i1 @test15(i32 %A, i32 %B) {
; CHECK-LABEL: @test15(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp ult i32 %A, %B
%C2 = icmp eq i32 %A, %B
@@ -75,8 +75,8 @@ define i1 @test15(i32 %A, i32 %B) {
define i1 @test15_logical(i32 %A, i32 %B) {
; CHECK-LABEL: @test15_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp ult i32 %A, %B
%C2 = icmp eq i32 %A, %B
@@ -112,8 +112,8 @@ define i32 @test17(i32 %A) {
define i1 @test18(i32 %A) {
; CHECK-LABEL: @test18(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], -100
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -50
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ult i32 [[TMP1]], -50
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sge i32 %A, 100
%C = icmp slt i32 %A, 50
@@ -124,8 +124,8 @@ define i1 @test18(i32 %A) {
define i1 @test18_logical(i32 %A) {
; CHECK-LABEL: @test18_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[A:%.*]], -100
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -50
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ult i32 [[TMP1]], -50
+; CHECK-NEXT: ret i1 [[D]]
;
%B = icmp sge i32 %A, 100
%C = icmp slt i32 %A, 50
@@ -136,8 +136,8 @@ define i1 @test18_logical(i32 %A) {
define <2 x i1> @test18vec(<2 x i32> %A) {
; CHECK-LABEL: @test18vec(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[A:%.*]], <i32 -100, i32 -100>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -50, i32 -50>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -50, i32 -50>
+; CHECK-NEXT: ret <2 x i1> [[D]]
;
%B = icmp sge <2 x i32> %A, <i32 100, i32 100>
%C = icmp slt <2 x i32> %A, <i32 50, i32 50>
@@ -212,8 +212,8 @@ define i1 @test25(i32 %A, i32 %B) {
; CHECK-LABEL: @test25(
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[B:%.*]], 57
-; CHECK-NEXT: [[F:%.*]] = and i1 [[C]], [[D]]
-; CHECK-NEXT: ret i1 [[F]]
+; CHECK-NEXT: [[E_NOT:%.*]] = and i1 [[C]], [[D]]
+; CHECK-NEXT: ret i1 [[E_NOT]]
;
%C = icmp eq i32 %A, 0
%D = icmp eq i32 %B, 57
@@ -226,8 +226,8 @@ define i1 @test25_logical(i32 %A, i32 %B) {
; CHECK-LABEL: @test25_logical(
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[B:%.*]], 57
-; CHECK-NEXT: [[E:%.*]] = select i1 [[C]], i1 [[D]], i1 false
-; CHECK-NEXT: ret i1 [[E]]
+; CHECK-NEXT: [[E_NOT:%.*]] = select i1 [[C]], i1 [[D]], i1 false
+; CHECK-NEXT: ret i1 [[E_NOT]]
;
%C = icmp eq i32 %A, 0
%D = icmp eq i32 %B, 57
@@ -240,8 +240,8 @@ define i1 @test25_logical(i32 %A, i32 %B) {
define i1 @and_icmp_eq_0(i32 %A, i32 %B) {
; CHECK-LABEL: @and_icmp_eq_0(
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp eq i32 %A, 0
%C2 = icmp eq i32 %B, 0
@@ -253,8 +253,8 @@ define i1 @and_icmp_eq_0(i32 %A, i32 %B) {
define <2 x i1> @and_icmp_eq_0_vector(<2 x i32> %A, <2 x i32> %B) {
; CHECK-LABEL: @and_icmp_eq_0_vector(
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[D]]
;
%C1 = icmp eq <2 x i32> %A, zeroinitializer
%C2 = icmp eq <2 x i32> %B, zeroinitializer
@@ -265,8 +265,8 @@ define <2 x i1> @and_icmp_eq_0_vector(<2 x i32> %A, <2 x i32> %B) {
define <2 x i1> @and_icmp_eq_0_vector_undef1(<2 x i32> %A, <2 x i32> %B) {
; CHECK-LABEL: @and_icmp_eq_0_vector_undef1(
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[D]]
;
%C1 = icmp eq <2 x i32> %A, <i32 0, i32 undef>
%C2 = icmp eq <2 x i32> %B, <i32 0, i32 undef>
@@ -277,8 +277,8 @@ define <2 x i1> @and_icmp_eq_0_vector_undef1(<2 x i32> %A, <2 x i32> %B) {
define <2 x i1> @and_icmp_eq_0_vector_undef2(<2 x i32> %A, <2 x i32> %B) {
; CHECK-LABEL: @and_icmp_eq_0_vector_undef2(
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[D]]
;
%C1 = icmp eq <2 x i32> %A, <i32 0, i32 undef>
%C2 = icmp eq <2 x i32> %B, <i32 undef, i32 0>
@@ -332,8 +332,8 @@ define <2 x i1> @test27vec(<2 x ptr> %A, <2 x ptr> %B) {
define i1 @test28(i32 %A, i32 %B) {
; CHECK-LABEL: @test28(
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[D]]
;
%C1 = icmp ne i32 %A, 0
%C2 = icmp ne i32 %B, 0
@@ -447,8 +447,8 @@ define <2 x i64> @test31vec(<2 x i64> %A) {
; codegen is mature enough to handle vector selects.
define <4 x i32> @test32(<4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191) {
; CHECK-LABEL: @test32(
-; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[AND_I1352:%.*]], <4 x i32> [[VECINIT6_I176:%.*]], <4 x i32> [[VECINIT6_I191:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[OR_I:%.*]] = select <4 x i1> [[AND_I1352:%.*]], <4 x i32> [[VECINIT6_I176:%.*]], <4 x i32> [[VECINIT6_I191:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[OR_I]]
;
%and.i135 = sext <4 x i1> %and.i1352 to <4 x i32>
%and.i129 = and <4 x i32> %vecinit6.i176, %and.i135
@@ -502,8 +502,8 @@ define i32 @test35(i32 %a, i32 %b) {
define i1 @test36(i32 %x) {
; CHECK-LABEL: @test36(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -23
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RET2:%.*]] = icmp ult i32 [[TMP1]], 3
+; CHECK-NEXT: ret i1 [[RET2]]
;
%cmp1 = icmp eq i32 %x, 23
%cmp2 = icmp eq i32 %x, 24
@@ -516,8 +516,8 @@ define i1 @test36(i32 %x) {
define i1 @test36_logical(i32 %x) {
; CHECK-LABEL: @test36_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -23
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RET2:%.*]] = icmp ult i32 [[TMP1]], 3
+; CHECK-NEXT: ret i1 [[RET2]]
;
%cmp1 = icmp eq i32 %x, 23
%cmp2 = icmp eq i32 %x, 24
@@ -530,8 +530,8 @@ define i1 @test36_logical(i32 %x) {
define i1 @test37(i32 %x) {
; CHECK-LABEL: @test37(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 31
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RET1:%.*]] = icmp ult i32 [[TMP1]], 31
+; CHECK-NEXT: ret i1 [[RET1]]
;
%add1 = add i32 %x, 7
%cmp1 = icmp ult i32 %add1, 30
@@ -543,8 +543,8 @@ define i1 @test37(i32 %x) {
define i1 @test37_logical(i32 %x) {
; CHECK-LABEL: @test37_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 31
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RET1:%.*]] = icmp ult i32 [[TMP1]], 31
+; CHECK-NEXT: ret i1 [[RET1]]
;
%add1 = add i32 %x, 7
%cmp1 = icmp ult i32 %add1, 30
@@ -556,8 +556,8 @@ define i1 @test37_logical(i32 %x) {
define <2 x i1> @test37_uniform(<2 x i32> %x) {
; CHECK-LABEL: @test37_uniform(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 7, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 31, i32 31>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[RET1:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 31, i32 31>
+; CHECK-NEXT: ret <2 x i1> [[RET1]]
;
%add1 = add <2 x i32> %x, <i32 7, i32 7>
%cmp1 = icmp ult <2 x i32> %add1, <i32 30, i32 30>
@@ -584,8 +584,8 @@ define <2 x i1> @test37_undef(<2 x i32> %x) {
define i1 @test38(i32 %x) {
; CHECK-LABEL: @test38(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 31
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RET1:%.*]] = icmp ult i32 [[TMP1]], 31
+; CHECK-NEXT: ret i1 [[RET1]]
;
%add1 = add i32 %x, 7
%cmp1 = icmp eq i32 %x, 23
@@ -597,8 +597,8 @@ define i1 @test38(i32 %x) {
define i1 @test38_logical(i32 %x) {
; CHECK-LABEL: @test38_logical(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 7
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 31
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RET1:%.*]] = icmp ult i32 [[TMP1]], 31
+; CHECK-NEXT: ret i1 [[RET1]]
;
%add1 = add i32 %x, 7
%cmp1 = icmp eq i32 %x, 23
@@ -757,8 +757,8 @@ define i1 @test46(i8 signext %c) {
; CHECK-LABEL: @test46(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 26
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i8 [[TMP2]], 26
+; CHECK-NEXT: ret i1 [[OR]]
;
%c.off = add i8 %c, -97
%cmp1 = icmp ult i8 %c.off, 26
@@ -772,8 +772,8 @@ define i1 @test46_logical(i8 signext %c) {
; CHECK-LABEL: @test46_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 26
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i8 [[TMP2]], 26
+; CHECK-NEXT: ret i1 [[OR]]
;
%c.off = add i8 %c, -97
%cmp1 = icmp ult i8 %c.off, 26
@@ -787,8 +787,8 @@ define <2 x i1> @test46_uniform(<2 x i8> %c) {
; CHECK-LABEL: @test46_uniform(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[C:%.*]], <i8 -33, i8 -33>
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i8> [[TMP1]], <i8 -65, i8 -65>
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <2 x i8> [[TMP2]], <i8 26, i8 26>
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult <2 x i8> [[TMP2]], <i8 26, i8 26>
+; CHECK-NEXT: ret <2 x i1> [[OR]]
;
%c.off = add <2 x i8> %c, <i8 -97, i8 -97>
%cmp1 = icmp ult <2 x i8> %c.off, <i8 26, i8 26>
@@ -820,8 +820,8 @@ define <2 x i1> @test46_undef(<2 x i8> %c) {
define i1 @two_ranges_to_mask_and_range_degenerate(i16 %x) {
; CHECK-LABEL: @two_ranges_to_mask_and_range_degenerate(
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[X:%.*]], -20
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i16 [[TMP1]], 12
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i16 [[TMP1]], 12
+; CHECK-NEXT: ret i1 [[OR]]
;
%cmp1 = icmp ult i16 %x, 12
%cmp2 = icmp uge i16 %x, 16
@@ -835,8 +835,8 @@ define i1 @test47(i8 signext %c) {
; CHECK-LABEL: @test47(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 27
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i8 [[TMP2]], 27
+; CHECK-NEXT: ret i1 [[OR]]
;
%c.off = add i8 %c, -65
%cmp1 = icmp ule i8 %c.off, 26
@@ -850,8 +850,8 @@ define i1 @test47_logical(i8 signext %c) {
; CHECK-LABEL: @test47_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 27
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[OR:%.*]] = icmp ult i8 [[TMP2]], 27
+; CHECK-NEXT: ret i1 [[OR]]
;
%c.off = add i8 %c, -65
%cmp1 = icmp ule i8 %c.off, 26
@@ -1196,8 +1196,8 @@ define i1 @orn_and_cmp_4_logical(i32 %a, i32 %b, i32 %c) {
; The constant vectors are inverses. Make sure we can turn this into a select without crashing trying to truncate the constant to 16xi1.
define <16 x i1> @test51(<16 x i1> %arg, <16 x i1> %arg1) {
; CHECK-LABEL: @test51(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i1> [[ARG:%.*]], <16 x i1> [[ARG1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 24, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: ret <16 x i1> [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i1> [[ARG:%.*]], <16 x i1> [[ARG1:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 23, i32 24, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT: ret <16 x i1> [[TMP3]]
;
%tmp = and <16 x i1> %arg, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>
%tmp2 = and <16 x i1> %arg1, <i1 false, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true>
@@ -1450,8 +1450,8 @@ define i8 @lshr_bitwidth_mask(i8 %x, i8 %y) {
define i1 @cmp_overlap(i32 %x) {
; CHECK-LABEL: @cmp_overlap(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT: ret i1 [[R]]
;
%isneg = icmp slt i32 %x, 0
%negx = sub i32 0, %x
@@ -1462,8 +1462,8 @@ define i1 @cmp_overlap(i32 %x) {
define <2 x i1> @cmp_overlap_splat(<2 x i5> %x) {
; CHECK-LABEL: @cmp_overlap_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i5> [[X:%.*]], <i5 1, i5 1>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt <2 x i5> [[X:%.*]], <i5 1, i5 1>
+; CHECK-NEXT: ret <2 x i1> [[R]]
;
%isneg = icmp slt <2 x i5> %x, zeroinitializer
%negx = sub <2 x i5> zeroinitializer, %x
diff --git a/llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll b/llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
index 731a4c7897b59..ea75de4e99f88 100644
--- a/llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
+++ b/llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
@@ -19,9 +19,9 @@ define i32 @test_gep_and_bitcast(i1 %cond, i1 %cond2) {
; ALL: bb2:
; ALL-NEXT: br label [[EXIT]]
; ALL: exit:
-; ALL-NEXT: [[PTR_TYPED_IN:%.*]] = getelementptr inbounds i8, ptr [[OBJ]], i64 16
-; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED_IN]], align 4
-; ALL-NEXT: store i32 1, ptr [[PTR_TYPED_IN]], align 4
+; ALL-NEXT: [[PTR_TYPED:%.*]] = getelementptr inbounds i8, ptr [[OBJ]], i64 16
+; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED]], align 4
+; ALL-NEXT: store i32 1, ptr [[PTR_TYPED]], align 4
; ALL-NEXT: [[RES:%.*]] = select i1 [[COND2:%.*]], i32 [[RES_PHI]], i32 1
; ALL-NEXT: ret i32 [[RES]]
;
@@ -57,9 +57,9 @@ define i32 @test_gep_and_bitcast_arg(ptr %obj, i1 %cond, i1 %cond2) {
; ALL: bb2:
; ALL-NEXT: br label [[EXIT]]
; ALL: exit:
-; ALL-NEXT: [[PTR_TYPED_IN:%.*]] = getelementptr inbounds i8, ptr [[OBJ:%.*]], i64 16
-; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED_IN]], align 4
-; ALL-NEXT: store i32 1, ptr [[PTR_TYPED_IN]], align 4
+; ALL-NEXT: [[PTR_TYPED:%.*]] = getelementptr inbounds i8, ptr [[OBJ:%.*]], i64 16
+; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED]], align 4
+; ALL-NEXT: store i32 1, ptr [[PTR_TYPED]], align 4
; ALL-NEXT: [[RES:%.*]] = select i1 [[COND2:%.*]], i32 [[RES_PHI]], i32 1
; ALL-NEXT: ret i32 [[RES]]
;
@@ -105,9 +105,9 @@ define i32 @test_gep_and_bitcast_phi(i1 %cond, i1 %cond2, i1 %cond3) {
; ALL: bb4:
; ALL-NEXT: br label [[EXIT]]
; ALL: exit:
-; ALL-NEXT: [[PTR_TYPED_IN:%.*]] = getelementptr inbounds i8, ptr [[OBJ]], i64 16
-; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED_IN]], align 4
-; ALL-NEXT: store i32 1, ptr [[PTR_TYPED_IN]], align 4
+; ALL-NEXT: [[PTR_TYPED:%.*]] = getelementptr inbounds i8, ptr [[OBJ]], i64 16
+; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED]], align 4
+; ALL-NEXT: store i32 1, ptr [[PTR_TYPED]], align 4
; ALL-NEXT: [[RES:%.*]] = select i1 [[COND3:%.*]], i32 [[RES_PHI]], i32 1
; ALL-NEXT: ret i32 [[RES]]
;
@@ -196,9 +196,9 @@ define i32 @test_gep_and_bitcast_gep_base_ptr(i1 %cond, i1 %cond2) {
; ALL: bb2:
; ALL-NEXT: br label [[EXIT]]
; ALL: exit:
-; ALL-NEXT: [[PTR_TYPED_IN:%.*]] = getelementptr inbounds i8, ptr [[OBJ0]], i64 32
-; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED_IN]], align 4
-; ALL-NEXT: store i32 1, ptr [[PTR_TYPED_IN]], align 4
+; ALL-NEXT: [[PTR_TYPED:%.*]] = getelementptr inbounds i8, ptr [[OBJ0]], i64 32
+; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED]], align 4
+; ALL-NEXT: store i32 1, ptr [[PTR_TYPED]], align 4
; ALL-NEXT: [[RES:%.*]] = select i1 [[COND2:%.*]], i32 [[RES_PHI]], i32 1
; ALL-NEXT: ret i32 [[RES]]
;
@@ -234,9 +234,9 @@ define i32 @test_gep_and_bitcast_same_bb(i1 %cond, i1 %cond2) {
; ALL: bb2:
; ALL-NEXT: br label [[EXIT]]
; ALL: exit:
-; ALL-NEXT: [[PTR_TYPED_IN:%.*]] = getelementptr inbounds i8, ptr [[OBJ]], i64 16
-; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED_IN]], align 4
-; ALL-NEXT: store i32 1, ptr [[PTR_TYPED_IN]], align 4
+; ALL-NEXT: [[PTR_TYPED:%.*]] = getelementptr inbounds i8, ptr [[OBJ]], i64 16
+; ALL-NEXT: [[RES_PHI:%.*]] = load i32, ptr [[PTR_TYPED]], align 4
+; ALL-NEXT: store i32 1, ptr [[PTR_TYPED]], align 4
; ALL-NEXT: [[RES:%.*]] = select i1 [[COND2:%.*]], i32 [[RES_PHI]], i32 1
; ALL-NEXT: ret i32 [[RES]]
;
diff --git a/llvm/test/Transforms/InstCombine/phi-extractvalue.ll b/llvm/test/Transforms/InstCombine/phi-extractvalue.ll
index 06ae31cfebef8..75fd4718721cc 100644
--- a/llvm/test/Transforms/InstCombine/phi-extractvalue.ll
+++ b/llvm/test/Transforms/InstCombine/phi-extractvalue.ll
@@ -414,12 +414,12 @@ define i32 @extractvalue_of_one_constant_phi(i1 %c, { i32, i32 } %arg) {
; CHECK-LABEL: @extractvalue_of_one_constant_phi(
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
; CHECK: if:
-; CHECK-NEXT: [[PHI_EV:%.*]] = extractvalue { i32, i32 } [[ARG:%.*]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[ARG:%.*]], 0
; CHECK-NEXT: br label [[JOIN:%.*]]
; CHECK: else:
; CHECK-NEXT: br label [[JOIN]]
; CHECK: join:
-; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[PHI_EV]], [[IF]] ], [ 3, [[ELSE]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[TMP1]], [[IF]] ], [ 3, [[ELSE]] ]
; CHECK-NEXT: ret i32 [[PHI]]
;
br i1 %c, label %if, label %else
@@ -465,12 +465,12 @@ define i32 @extractvalue_of_one_constant_phi_multi_index(i1 %c, { i32, { i32, i3
; CHECK-LABEL: @extractvalue_of_one_constant_phi_multi_index(
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
; CHECK: if:
-; CHECK-NEXT: [[PHI_EV:%.*]] = extractvalue { i32, { i32, i32 } } [[ARG:%.*]], 1, 1
+; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, { i32, i32 } } [[ARG:%.*]], 1, 1
; CHECK-NEXT: br label [[JOIN:%.*]]
; CHECK: else:
; CHECK-NEXT: br label [[JOIN]]
; CHECK: join:
-; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[PHI_EV]], [[IF]] ], [ 6, [[ELSE]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[TMP1]], [[IF]] ], [ 6, [[ELSE]] ]
; CHECK-NEXT: ret i32 [[PHI]]
;
br i1 %c, label %if, label %else
diff --git a/llvm/test/Transforms/InstCombine/phi-int2ptr-fold.ll b/llvm/test/Transforms/InstCombine/phi-int2ptr-fold.ll
index b2cdc0dc7dad0..0cceecd0709dd 100644
--- a/llvm/test/Transforms/InstCombine/phi-int2ptr-fold.ll
+++ b/llvm/test/Transforms/InstCombine/phi-int2ptr-fold.ll
@@ -14,9 +14,9 @@ define i64 @func(ptr %X, ptr %Y, i1 %cond) {
; CHECK: bb2:
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[PHI_IN_IN:%.*]] = phi ptr [ [[X:%.*]], [[BB1]] ], [ [[Y:%.*]], [[BB2]] ]
-; CHECK-NEXT: [[PHI_IN:%.*]] = ptrtoint ptr [[PHI_IN_IN]] to i64
-; CHECK-NEXT: ret i64 [[PHI_IN]]
+; CHECK-NEXT: [[PHI_IN:%.*]] = phi ptr [ [[X:%.*]], [[BB1]] ], [ [[Y:%.*]], [[BB2]] ]
+; CHECK-NEXT: [[X_P_I:%.*]] = ptrtoint ptr [[PHI_IN]] to i64
+; CHECK-NEXT: ret i64 [[X_P_I]]
;
br i1 %cond, label %bb1, label %bb2
@@ -42,8 +42,8 @@ define i64 @func_single_operand(ptr %X, ptr %Y, i1 %cond) {
; CHECK: bb1:
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
-; CHECK-NEXT: [[PHI_IN:%.*]] = phi ptr [ [[X:%.*]], [[BB1]] ], [ [[Y:%.*]], [[TMP0:%.*]] ]
-; CHECK-NEXT: [[X_P_I:%.*]] = ptrtoint ptr [[PHI_IN]] to i64
+; CHECK-NEXT: [[PHI:%.*]] = phi ptr [ [[X:%.*]], [[BB1]] ], [ [[Y:%.*]], [[TMP0:%.*]] ]
+; CHECK-NEXT: [[X_P_I:%.*]] = ptrtoint ptr [[PHI]] to i64
; CHECK-NEXT: ret i64 [[X_P_I]]
;
br i1 %cond, label %bb1, label %exit
diff --git a/llvm/test/Transforms/InstCombine/phi-pointercasts.ll b/llvm/test/Transforms/InstCombine/phi-pointercasts.ll
index 75d5c6e462271..066b5332b8c94 100644
--- a/llvm/test/Transforms/InstCombine/phi-pointercasts.ll
+++ b/llvm/test/Transforms/InstCombine/phi-pointercasts.ll
@@ -96,14 +96,14 @@ define void @test_bitcast_loads_in_
diff erent_bbs(i1 %c, ptr %ptr.0, ptr %ptr.1)
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
; CHECK: b0:
-; CHECK-NEXT: [[LOAD_PTR_02:%.*]] = load ptr, ptr [[PTR_0:%.*]], align 8
-; CHECK-NEXT: call void @use(ptr [[LOAD_PTR_02]])
+; CHECK-NEXT: [[LOAD_PTR_0:%.*]] = load ptr, ptr [[PTR_0:%.*]], align 8
+; CHECK-NEXT: call void @use(ptr [[LOAD_PTR_0]])
; CHECK-NEXT: br label [[END:%.*]]
; CHECK: b1:
-; CHECK-NEXT: [[LOAD_PTR_11:%.*]] = load ptr, ptr [[PTR_1:%.*]], align 8
+; CHECK-NEXT: [[LOAD_PTR_1:%.*]] = load ptr, ptr [[PTR_1:%.*]], align 8
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[LOAD_PTR_02]], [[B0]] ], [ [[LOAD_PTR_11]], [[B1]] ]
+; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[LOAD_PTR_0]], [[B0]] ], [ [[LOAD_PTR_1]], [[B1]] ]
; CHECK-NEXT: store i8 0, ptr [[P]], align 1
; CHECK-NEXT: ret void
;
@@ -164,7 +164,7 @@ define void @test_bitcast_not_foldable(i1 %c, ptr %ptr.0, ptr %ptr.1) {
; CHECK-NEXT: call void @use(ptr [[PTR_1:%.*]])
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0:%.*]], [[B0]] ], [ [[PTR_1:%.*]], [[B1]] ]
+; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0:%.*]], [[B0]] ], [ [[PTR_1]], [[B1]] ]
; CHECK-NEXT: store i8 0, ptr [[P]], align 1
; CHECK-NEXT: ret void
;
@@ -223,7 +223,7 @@ define void @test_bitcast_
diff erent_bases(i1 %c, ptr %ptr.0, ptr %ptr.1) {
; CHECK: b1:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0:%.*]], [[B0]] ], [ [[PTR_1:%.*]], [[B1]] ]
+; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0]], [[B0]] ], [ [[PTR_1:%.*]], [[B1]] ]
; CHECK-NEXT: store i8 0, ptr [[P]], align 1
; CHECK-NEXT: ret void
;
@@ -293,7 +293,7 @@ define void @test_4_incoming_values_
diff erent_bases_1(i32 %c, ptr %ptr.0, ptr %p
; CHECK: b3:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0:%.*]], [[B0]] ], [ [[PTR_1:%.*]], [[B1]] ], [ [[PTR_0]], [[B2]] ], [ [[PTR_0]], [[B3]] ]
+; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0]], [[B0]] ], [ [[PTR_1:%.*]], [[B1]] ], [ [[PTR_0]], [[B2]] ], [ [[PTR_0]], [[B3]] ]
; CHECK-NEXT: store i8 0, ptr [[P]], align 1
; CHECK-NEXT: ret void
; CHECK: end.2:
@@ -346,8 +346,8 @@ define void @test_4_incoming_values_
diff erent_bases_2(i32 %c, ptr %ptr.0, ptr %p
; CHECK: b3:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P_IN:%.*]] = phi ptr [ [[PTR_1:%.*]], [[B0]] ], [ [[PTR_0]], [[B1]] ], [ [[PTR_0]], [[B2]] ], [ [[PTR_0]], [[B3]] ]
-; CHECK-NEXT: store i8 0, ptr [[P_IN]], align 1
+; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_1:%.*]], [[B0]] ], [ [[PTR_0]], [[B1]] ], [ [[PTR_0]], [[B2]] ], [ [[PTR_0]], [[B3]] ]
+; CHECK-NEXT: store i8 0, ptr [[P]], align 1
; CHECK-NEXT: ret void
; CHECK: end.2:
; CHECK-NEXT: ret void
@@ -394,12 +394,12 @@ define void @test_4_incoming_values_
diff erent_bases_3(i32 %c, ptr %ptr.0, ptr %p
; CHECK: b1:
; CHECK-NEXT: br label [[END]]
; CHECK: b2:
-; CHECK-NEXT: call void @use(ptr [[PTR_0]])
+; CHECK-NEXT: call void @use(ptr [[PTR_0:%.*]])
; CHECK-NEXT: br label [[END]]
; CHECK: b3:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0:%.*]], [[B0]] ], [ [[PTR_0]], [[B1]] ], [ [[PTR_0]], [[B2]] ], [ [[PTR_1:%.*]], [[B3]] ]
+; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[PTR_0]], [[B0]] ], [ [[PTR_0]], [[B1]] ], [ [[PTR_0]], [[B2]] ], [ [[PTR_1:%.*]], [[B3]] ]
; CHECK-NEXT: store i8 0, ptr [[P]], align 1
; CHECK-NEXT: ret void
; CHECK: end.2:
diff --git a/llvm/test/Transforms/InstCombine/pow-3.ll b/llvm/test/Transforms/InstCombine/pow-3.ll
index 778ab648b1fd9..20d8afbe755d7 100644
--- a/llvm/test/Transforms/InstCombine/pow-3.ll
+++ b/llvm/test/Transforms/InstCombine/pow-3.ll
@@ -18,8 +18,8 @@ define double @sqrt_intrinsic(double %x) {
; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[RETVAL]]
;
%retval = call double @llvm.pow.f64(double %x, double 0.5)
ret double %retval
diff --git a/llvm/test/Transforms/InstCombine/pow-exp.ll b/llvm/test/Transforms/InstCombine/pow-exp.ll
index 685b9434cb5b3..fb8d9170e90cb 100644
--- a/llvm/test/Transforms/InstCombine/pow-exp.ll
+++ b/llvm/test/Transforms/InstCombine/pow-exp.ll
@@ -137,7 +137,7 @@ define fp128 @powl_exp2l_not_fast(fp128 %x, fp128 %y) {
define float @powf_exp10f(float %x, float %y) {
; CHECK-LABEL: @powf_exp10f(
-; CHECK-NEXT: [[CALL:%.*]] = call fast float @exp10f(float [[X:%.*]]) #1
+; CHECK-NEXT: [[CALL:%.*]] = call fast float @exp10f(float [[X:%.*]]) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[CALL]], float [[Y:%.*]])
; CHECK-NEXT: ret float [[POW]]
;
@@ -148,7 +148,7 @@ define float @powf_exp10f(float %x, float %y) {
define double @pow_exp10(double %x, double %y) {
; CHECK-LABEL: @pow_exp10(
-; CHECK-NEXT: [[CALL:%.*]] = call fast double @exp10(double [[X:%.*]]) #1
+; CHECK-NEXT: [[CALL:%.*]] = call fast double @exp10(double [[X:%.*]]) #[[ATTR1]]
; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[CALL]], double [[Y:%.*]])
; CHECK-NEXT: ret double [[POW]]
;
@@ -159,7 +159,7 @@ define double @pow_exp10(double %x, double %y) {
define fp128 @pow_exp10l(fp128 %x, fp128 %y) {
; CHECK-LABEL: @pow_exp10l(
-; CHECK-NEXT: [[CALL:%.*]] = call fast fp128 @exp10l(fp128 [[X:%.*]]) #1
+; CHECK-NEXT: [[CALL:%.*]] = call fast fp128 @exp10l(fp128 [[X:%.*]]) #[[ATTR1]]
; CHECK-NEXT: [[POW:%.*]] = call fast fp128 @llvm.pow.f128(fp128 [[CALL]], fp128 [[Y:%.*]])
; CHECK-NEXT: ret fp128 [[POW]]
;
@@ -212,18 +212,18 @@ declare void @use_f(float)
define double @pow_ok_base(double %e) {
; CHECK-LABEL: @pow_ok_base(
-; Do not change 0xBFE0776{{.*}} to the exact constant, see PR42740
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0xBFE0776{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0xBFE0776228967D13
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
+; Do not change 0xBFE0776{{.*}} to the exact constant, see PR42740
%call = tail call afn nnan ninf double @pow(double 0x3FE6666666666666, double %e)
ret double %call
}
define double @pow_ok_base_fast(double %e) {
; CHECK-LABEL: @pow_ok_base_fast(
-; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[E:%.*]], 0xBFE0776{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[E:%.*]], 0xBFE0776228967D13
; CHECK-NEXT: [[EXP2:%.*]] = tail call fast double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -233,7 +233,7 @@ define double @pow_ok_base_fast(double %e) {
define double @pow_ok_base2(double %e) {
; CHECK-LABEL: @pow_ok_base2(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x4010952{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x4010952C788751AC
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -243,7 +243,7 @@ define double @pow_ok_base2(double %e) {
define double @pow_ok_base3(double %e) {
; CHECK-LABEL: @pow_ok_base3(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x400AB0B5{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x400AB0B5584886CD
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -253,7 +253,7 @@ define double @pow_ok_base3(double %e) {
define double @pow_ok_ten_base(double %e) {
; CHECK-LABEL: @pow_ok_ten_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x400A934F{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x400A934F0979A371
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -273,7 +273,7 @@ define double @pow_ok_denorm_base(double %e) {
define float @powf_ok_base(float %e) {
; CHECK-LABEL: @powf_ok_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0xBFE07762{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0xBFE0776240000000
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -283,7 +283,7 @@ define float @powf_ok_base(float %e) {
define float @powf_ok_base2(float %e) {
; CHECK-LABEL: @powf_ok_base2(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x4010952{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x4010952C80000000
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -293,7 +293,7 @@ define float @powf_ok_base2(float %e) {
define float @powf_ok_base3(float %e) {
; CHECK-LABEL: @powf_ok_base3(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x400AB0B5{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x400AB0B560000000
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -303,7 +303,7 @@ define float @powf_ok_base3(float %e) {
define float @powf_ok_ten_base(float %e) {
; CHECK-LABEL: @powf_ok_ten_base(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x400A934{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x400A934F00000000
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: ret float [[EXP2F]]
;
@@ -370,7 +370,7 @@ define double @pow_negative_base(double %e) {
define double @pow_multiuse(double %e) {
; CHECK-LABEL: @pow_multiuse(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x4002934{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn double [[E:%.*]], 0x4002934F0979A371
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan ninf afn double @exp2(double [[MUL]])
; CHECK-NEXT: tail call void @use_d(double [[EXP2]])
; CHECK-NEXT: ret double [[EXP2]]
@@ -400,7 +400,7 @@ define double @pow_ok_base_no_nnan(double %e) {
define double @pow_ok_base_no_ninf(double %e) {
; CHECK-LABEL: @pow_ok_base_no_ninf(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan afn double [[E:%.*]], 0xBFE0776{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan afn double [[E:%.*]], 0xBFE0776228967D13
; CHECK-NEXT: [[EXP2:%.*]] = tail call nnan afn double @exp2(double [[MUL]])
; CHECK-NEXT: ret double [[EXP2]]
;
@@ -455,7 +455,7 @@ define float @powf_negative_base(float %e) {
define float @powf_multiuse(float %e) {
; CHECK-LABEL: @powf_multiuse(
-; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x4002934{{.*}}
+; CHECK-NEXT: [[MUL:%.*]] = fmul nnan ninf afn float [[E:%.*]], 0x4002934F00000000
; CHECK-NEXT: [[EXP2F:%.*]] = tail call nnan ninf afn float @exp2f(float [[MUL]])
; CHECK-NEXT: tail call void @use_f(float [[EXP2F]])
; CHECK-NEXT: ret float [[EXP2F]]
diff --git a/llvm/test/Transforms/InstCombine/pow-sqrt.ll b/llvm/test/Transforms/InstCombine/pow-sqrt.ll
index b018850e29baf..9272c1c33a953 100644
--- a/llvm/test/Transforms/InstCombine/pow-sqrt.ll
+++ b/llvm/test/Transforms/InstCombine/pow-sqrt.ll
@@ -21,8 +21,8 @@ define double @pow_intrinsic_half_no_FMF(double %x) {
; CHECK-NEXT: [[SQRT:%.*]] = call double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call double @llvm.fabs.f64(double [[SQRT]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[POW:%.*]] = select i1 [[ISINF]], double 0x7FF0000000000000, double [[ABS]]
+; CHECK-NEXT: ret double [[POW]]
;
%pow = call double @llvm.pow.f64(double %x, double 5.0e-01)
ret double %pow
@@ -52,8 +52,8 @@ define <2 x double> @pow_intrinsic_half_approx(<2 x double> %x) {
; CHECK-NEXT: [[SQRT:%.*]] = call afn <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], <double 0xFFF0000000000000, double 0xFFF0000000000000>
-; CHECK-NEXT: [[TMP1:%.*]] = select afn <2 x i1> [[ISINF]], <2 x double> <double 0x7FF0000000000000, double 0x7FF0000000000000>, <2 x double> [[ABS]]
-; CHECK-NEXT: ret <2 x double> [[TMP1]]
+; CHECK-NEXT: [[POW:%.*]] = select afn <2 x i1> [[ISINF]], <2 x double> <double 0x7FF0000000000000, double 0x7FF0000000000000>, <2 x double> [[ABS]]
+; CHECK-NEXT: ret <2 x double> [[POW]]
;
%pow = call afn <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 5.0e-01, double 5.0e-01>)
ret <2 x double> %pow
@@ -117,8 +117,8 @@ define double @pow_intrinsic_half_nsz(double %x) {
; CHECK-LABEL: @pow_intrinsic_half_nsz(
; CHECK-NEXT: [[SQRT:%.*]] = call nsz double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[TMP1:%.*]] = select nsz i1 [[ISINF]], double 0x7FF0000000000000, double [[SQRT]]
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[POW:%.*]] = select nsz i1 [[ISINF]], double 0x7FF0000000000000, double [[SQRT]]
+; CHECK-NEXT: ret double [[POW]]
;
%pow = call nsz double @llvm.pow.f64(double %x, double 5.0e-01)
ret double %pow
@@ -222,8 +222,8 @@ define <2 x double> @pow_intrinsic_neghalf_reassoc(<2 x double> %x) {
; CHECK-NEXT: [[SQRT:%.*]] = call reassoc <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call reassoc <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp reassoc oeq <2 x double> [[X]], <double 0xFFF0000000000000, double 0xFFF0000000000000>
-; CHECK-NEXT: [[ABS_OP:%.*]] = fdiv reassoc <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[ABS]]
-; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[ABS_OP]]
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv reassoc <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[ABS]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[TMP1]]
; CHECK-NEXT: ret <2 x double> [[RECIPROCAL]]
;
%pow = call reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -5.0e-01, double -5.0e-01>)
@@ -239,8 +239,8 @@ define <2 x double> @pow_intrinsic_neghalf_afn(<2 x double> %x) {
; CHECK-NEXT: [[SQRT:%.*]] = call afn <2 x double> @llvm.sqrt.v2f64(<2 x double> [[X:%.*]])
; CHECK-NEXT: [[ABS:%.*]] = call afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[SQRT]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp afn oeq <2 x double> [[X]], <double 0xFFF0000000000000, double 0xFFF0000000000000>
-; CHECK-NEXT: [[ABS_OP:%.*]] = fdiv afn <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[ABS]]
-; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[ABS_OP]]
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv afn <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[ABS]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select <2 x i1> [[ISINF]], <2 x double> zeroinitializer, <2 x double> [[TMP1]]
; CHECK-NEXT: ret <2 x double> [[RECIPROCAL]]
;
%pow = call afn <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -5.0e-01, double -5.0e-01>)
@@ -286,8 +286,8 @@ define double @pow_intrinsic_neghalf_nsz(double %x) {
; CHECK-LABEL: @pow_intrinsic_neghalf_nsz(
; CHECK-NEXT: [[SQRT:%.*]] = call nsz afn double @llvm.sqrt.f64(double [[X:%.*]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp nsz afn oeq double [[X]], 0xFFF0000000000000
-; CHECK-NEXT: [[SQRT_OP:%.*]] = fdiv nsz afn double 1.000000e+00, [[SQRT]]
-; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], double 0.000000e+00, double [[SQRT_OP]]
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv nsz afn double 1.000000e+00, [[SQRT]]
+; CHECK-NEXT: [[RECIPROCAL:%.*]] = select i1 [[ISINF]], double 0.000000e+00, double [[TMP1]]
; CHECK-NEXT: ret double [[RECIPROCAL]]
;
%pow = call afn nsz double @llvm.pow.f64(double %x, double -5.0e-01)
diff --git a/llvm/test/Transforms/InstCombine/powi.ll b/llvm/test/Transforms/InstCombine/powi.ll
index 7e4ecc549ff00..20fe25c50a3ff 100644
--- a/llvm/test/Transforms/InstCombine/powi.ll
+++ b/llvm/test/Transforms/InstCombine/powi.ll
@@ -144,8 +144,8 @@ define double @powi_fmul_powi(double %x, i32 %y, i32 %z) {
; CHECK-LABEL: @powi_fmul_powi(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[Z:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[TMP0]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[TMP0]])
+; CHECK-NEXT: ret double [[MUL]]
;
entry:
%p1 = tail call double @llvm.powi.f64.i32(double %x, i32 %y)
@@ -158,8 +158,8 @@ define double @powi_fmul_powi_fast_on_fmul(double %x, i32 %y, i32 %z) {
; CHECK-LABEL: @powi_fmul_powi_fast_on_fmul(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[Z:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call fast double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[TMP0]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[MUL:%.*]] = call fast double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[TMP0]])
+; CHECK-NEXT: ret double [[MUL]]
;
entry:
%p1 = tail call double @llvm.powi.f64.i32(double %x, i32 %y)
@@ -187,8 +187,8 @@ define double @powi_fmul_powi_same_power(double %x, i32 %y, i32 %z) {
; CHECK-LABEL: @powi_fmul_powi_same_power(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = shl i32 [[Y:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[TMP0]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[TMP0]])
+; CHECK-NEXT: ret double [[MUL]]
;
entry:
%p1 = tail call double @llvm.powi.f64.i32(double %x, i32 %y)
@@ -203,8 +203,8 @@ define double @powi_fmul_powi_use_first(double %x, i32 %y, i32 %z) {
; CHECK-NEXT: [[P1:%.*]] = tail call double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
; CHECK-NEXT: tail call void @use(double [[P1]])
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[Y]], [[Z:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X]], i32 [[TMP0]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X]], i32 [[TMP0]])
+; CHECK-NEXT: ret double [[MUL]]
;
entry:
%p1 = tail call double @llvm.powi.f64.i32(double %x, i32 %y)
@@ -220,8 +220,8 @@ define double @powi_fmul_powi_use_second(double %x, i32 %y, i32 %z) {
; CHECK-NEXT: [[P1:%.*]] = tail call double @llvm.powi.f64.i32(double [[X:%.*]], i32 [[Z:%.*]])
; CHECK-NEXT: tail call void @use(double [[P1]])
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[Y:%.*]], [[Z]]
-; CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X]], i32 [[TMP0]])
-; CHECK-NEXT: ret double [[TMP1]]
+; CHECK-NEXT: [[MUL:%.*]] = call reassoc double @llvm.powi.f64.i32(double [[X]], i32 [[TMP0]])
+; CHECK-NEXT: ret double [[MUL]]
;
entry:
%p1 = tail call double @llvm.powi.f64.i32(double %x, i32 %z)
diff --git a/llvm/test/Transforms/InstCombine/pr17827.ll b/llvm/test/Transforms/InstCombine/pr17827.ll
index 94e1ef2ca6054..6c6110aa073a5 100644
--- a/llvm/test/Transforms/InstCombine/pr17827.ll
+++ b/llvm/test/Transforms/InstCombine/pr17827.ll
@@ -34,8 +34,8 @@ define i1 @test_shift_and_cmp_not_changed2(i8 %p) {
define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
; CHECK-LABEL: @test_shift_and_cmp_changed1(
; CHECK-NEXT: [[ANDP:%.*]] = shl i8 [[P:%.*]], 5
-; CHECK-NEXT: [[SHL:%.*]] = and i8 [[ANDP]], -64
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[SHL]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[ANDP]], -64
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 32
; CHECK-NEXT: ret i1 [[CMP]]
;
%andp = and i8 %p, 6
@@ -50,8 +50,8 @@ define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
; CHECK-LABEL: @test_shift_and_cmp_changed1_vec(
; CHECK-NEXT: [[ANDP:%.*]] = shl <2 x i8> [[P:%.*]], <i8 5, i8 5>
-; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[ANDP]], <i8 -64, i8 -64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], <i8 32, i8 32>
+; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[ANDP]], <i8 -64, i8 -64>
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[TMP1]], <i8 32, i8 32>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%andp = and <2 x i8> %p, <i8 6, i8 6>
diff --git a/llvm/test/Transforms/InstCombine/pr21199.ll b/llvm/test/Transforms/InstCombine/pr21199.ll
index 383f6c5182371..54389768f1f9b 100644
--- a/llvm/test/Transforms/InstCombine/pr21199.ll
+++ b/llvm/test/Transforms/InstCombine/pr21199.ll
@@ -9,14 +9,14 @@ declare void @f(i32)
define void @test(i32 %len) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.umin.i32(i32 [[LEN:%.*]], i32 8)
-; CHECK-NEXT: [[CMP11_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.umin.i32(i32 [[LEN:%.*]], i32 8)
+; CHECK-NEXT: [[CMP11_NOT:%.*]] = icmp eq i32 [[COND]], 0
; CHECK-NEXT: br i1 [[CMP11_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[I_02:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: tail call void @f(i32 [[TMP0]])
+; CHECK-NEXT: tail call void @f(i32 [[COND]])
; CHECK-NEXT: [[INC]] = add i32 [[I_02]], 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[INC]], [[TMP0]]
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[INC]], [[COND]]
; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_BODY]], label [[FOR_END]]
; CHECK: for.end:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/InstCombine/pr21651.ll b/llvm/test/Transforms/InstCombine/pr21651.ll
index 89e027f41e6b4..5095fceb9812b 100644
--- a/llvm/test/Transforms/InstCombine/pr21651.ll
+++ b/llvm/test/Transforms/InstCombine/pr21651.ll
@@ -6,9 +6,9 @@ target datalayout = "n8:16:32:64"
define void @PR21651() {
; CHECK-LABEL: @PR21651(
-; CHECK-NEXT: switch i1 false, label %out [
-; CHECK-NEXT: i1 false, label %out
-; CHECK-NEXT: i1 true, label %out
+; CHECK-NEXT: switch i1 false, label [[OUT:%.*]] [
+; CHECK-NEXT: i1 false, label [[OUT]]
+; CHECK-NEXT: i1 true, label [[OUT]]
; CHECK-NEXT: ]
; CHECK: out:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/InstCombine/pr25342.ll b/llvm/test/Transforms/InstCombine/pr25342.ll
index 013c739772799..e1a6822e79084 100644
--- a/llvm/test/Transforms/InstCombine/pr25342.ll
+++ b/llvm/test/Transforms/InstCombine/pr25342.ll
@@ -93,8 +93,8 @@ define void @multi_phi(i32 signext %n) {
; CHECK-NEXT: [[ADD_I:%.*]] = fadd float [[SUB_I]], [[TMP0]]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: [[BIT0:%.*]] = and i32 [[INC]], 1
-; CHECK-NEXT: [[EVEN:%.*]] = icmp eq i32 [[BIT0]], 0
-; CHECK-NEXT: br i1 [[EVEN]], label [[EVEN_BB:%.*]], label [[ODD_BB]]
+; CHECK-NEXT: [[EVEN_NOT_NOT:%.*]] = icmp eq i32 [[BIT0]], 0
+; CHECK-NEXT: br i1 [[EVEN_NOT_NOT]], label [[EVEN_BB:%.*]], label [[ODD_BB]]
; CHECK: even.bb:
; CHECK-NEXT: [[TMP5:%.*]] = fadd float [[SUB_I]], [[ADD_I]]
; CHECK-NEXT: br label [[ODD_BB]]
diff --git a/llvm/test/Transforms/InstCombine/pr32686.ll b/llvm/test/Transforms/InstCombine/pr32686.ll
index 4a57b54c0de0f..acce81a603d2d 100644
--- a/llvm/test/Transforms/InstCombine/pr32686.ll
+++ b/llvm/test/Transforms/InstCombine/pr32686.ll
@@ -7,8 +7,8 @@
define void @tinkywinky() {
; CHECK-LABEL: @tinkywinky(
; CHECK-NEXT: [[PATATINO:%.*]] = load i8, ptr @a, align 1
-; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i8 [[PATATINO]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[TOBOOL]] to i32
+; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i8 [[PATATINO]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[TOBOOL_NOT]] to i32
; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], or (i32 zext (i1 icmp ne (ptr @a, ptr @b) to i32), i32 2)
; CHECK-NEXT: store i32 [[OR1]], ptr @b, align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/InstCombine/pr38897.ll b/llvm/test/Transforms/InstCombine/pr38897.ll
index 09af97cb0550b..0d4aecac9a67b 100644
--- a/llvm/test/Transforms/InstCombine/pr38897.ll
+++ b/llvm/test/Transforms/InstCombine/pr38897.ll
@@ -7,9 +7,9 @@ define i32 @sharpening(i32 %b340, i1 %c, i1 %d, i32 %e, i32 %f, i32 %g, i32 %h)
; CHECK-NEXT: [[SMAX58:%.*]] = select i1 [[C:%.*]], i32 [[E:%.*]], i32 [[F:%.*]]
; CHECK-NEXT: [[SMAX59:%.*]] = select i1 [[D:%.*]], i32 [[G:%.*]], i32 [[H:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[SMAX59]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 -1)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX58]], i32 [[TMP1]])
-; CHECK-NEXT: [[TMP14:%.*]] = xor i32 [[TMP2]], -1
+; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 -1)
+; CHECK-NEXT: [[SMAX61:%.*]] = call i32 @llvm.smax.i32(i32 [[SMAX58]], i32 [[TMP12]])
+; CHECK-NEXT: [[TMP14:%.*]] = xor i32 [[SMAX61]], -1
; CHECK-NEXT: ret i32 [[TMP14]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/pr38915.ll b/llvm/test/Transforms/InstCombine/pr38915.ll
index 5c11f2499f036..0874fe6cc927d 100644
--- a/llvm/test/Transforms/InstCombine/pr38915.ll
+++ b/llvm/test/Transforms/InstCombine/pr38915.ll
@@ -5,9 +5,9 @@ define i32 @PR38915(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @PR38915(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -1
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[Y:%.*]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP3]], i32 [[Z:%.*]])
-; CHECK-NEXT: [[M2N:%.*]] = xor i32 [[TMP4]], -1
+; CHECK-NEXT: [[M1N:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 [[TMP2]])
+; CHECK-NEXT: [[M2:%.*]] = call i32 @llvm.smax.i32(i32 [[M1N]], i32 [[Z:%.*]])
+; CHECK-NEXT: [[M2N:%.*]] = xor i32 [[M2]], -1
; CHECK-NEXT: ret i32 [[M2N]]
;
%xn = sub i32 0, %x
diff --git a/llvm/test/Transforms/InstCombine/pr43376-getFlippedStrictnessPredicateAndConstant-assert.ll b/llvm/test/Transforms/InstCombine/pr43376-getFlippedStrictnessPredicateAndConstant-assert.ll
index ffb280ce3516a..1ae8b5600881a 100644
--- a/llvm/test/Transforms/InstCombine/pr43376-getFlippedStrictnessPredicateAndConstant-assert.ll
+++ b/llvm/test/Transforms/InstCombine/pr43376-getFlippedStrictnessPredicateAndConstant-assert.ll
@@ -10,8 +10,8 @@ define i16 @d(ptr %d.a, ptr %d.b) {
; CHECK-LABEL: @d(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T0:%.*]] = load i16, ptr [[D_A:%.*]], align 1
-; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[T0]], 0
-; CHECK-NEXT: br i1 [[TOBOOL]], label [[LAND_END:%.*]], label [[LAND_RHS:%.*]]
+; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i16 [[T0]], 0
+; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LAND_END:%.*]], label [[LAND_RHS:%.*]]
; CHECK: land.rhs:
; CHECK-NEXT: br label [[LAND_END]]
; CHECK: land.end:
diff --git a/llvm/test/Transforms/InstCombine/pr44541.ll b/llvm/test/Transforms/InstCombine/pr44541.ll
index 2401a4024cc25..bc1679b7698b6 100644
--- a/llvm/test/Transforms/InstCombine/pr44541.ll
+++ b/llvm/test/Transforms/InstCombine/pr44541.ll
@@ -13,8 +13,8 @@ define i16 @passthru(i16 returned %x) {
define i16 @test(i16 %arg) {
; CHECK-LABEL: @test(
; CHECK-NEXT: [[ZERO:%.*]] = call i16 @passthru(i16 0)
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ARG:%.*]], i16 0)
-; CHECK-NEXT: ret i16 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = call i16 @llvm.smax.i16(i16 [[ARG:%.*]], i16 0)
+; CHECK-NEXT: ret i16 [[RET]]
;
%zero = call i16 @passthru(i16 0)
%sub = sub nuw nsw i16 %arg, %zero
diff --git a/llvm/test/Transforms/InstCombine/preserve-sminmax.ll b/llvm/test/Transforms/InstCombine/preserve-sminmax.ll
index d71ed6eaf7d84..f45cbe054d441 100644
--- a/llvm/test/Transforms/InstCombine/preserve-sminmax.ll
+++ b/llvm/test/Transforms/InstCombine/preserve-sminmax.ll
@@ -10,8 +10,8 @@
define i32 @foo(i32 %h) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: [[SD:%.*]] = sdiv i32 [[H:%.*]], 2
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[SD]], i32 1)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[SD]], i32 1)
+; CHECK-NEXT: ret i32 [[R]]
;
%sd = sdiv i32 %h, 2
%t = icmp slt i32 %sd, 1
@@ -22,8 +22,8 @@ define i32 @foo(i32 %h) {
define i32 @bar(i32 %h) {
; CHECK-LABEL: @bar(
; CHECK-NEXT: [[SD:%.*]] = sdiv i32 [[H:%.*]], 2
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[SD]], i32 1)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smax.i32(i32 [[SD]], i32 1)
+; CHECK-NEXT: ret i32 [[R]]
;
%sd = sdiv i32 %h, 2
%t = icmp sgt i32 %sd, 1
diff --git a/llvm/test/Transforms/InstCombine/printf-1.ll b/llvm/test/Transforms/InstCombine/printf-1.ll
index f162b2d948feb..7bd2895c9b942 100644
--- a/llvm/test/Transforms/InstCombine/printf-1.ll
+++ b/llvm/test/Transforms/InstCombine/printf-1.ll
@@ -166,8 +166,8 @@ define i32 @test_no_simplify3() {
; CHECK-NEXT: ret i32 [[RET]]
;
; CHECK-IPRINTF-LABEL: @test_no_simplify3(
-; CHECK-IPRINTF-NEXT: [[TMP1:%.*]] = call i32 (ptr, ...) @iprintf(ptr noundef nonnull dereferenceable(1) @h)
-; CHECK-IPRINTF-NEXT: ret i32 [[TMP1]]
+; CHECK-IPRINTF-NEXT: [[RET:%.*]] = call i32 (ptr, ...) @iprintf(ptr noundef nonnull dereferenceable(1) @h)
+; CHECK-IPRINTF-NEXT: ret i32 [[RET]]
;
%ret = call i32 (ptr, ...) @printf(ptr @h)
ret i32 %ret
diff --git a/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll b/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
index de8fcbb3802ac..8f25c71e47823 100644
--- a/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
+++ b/llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
@@ -415,7 +415,6 @@ entry:
define i8 @select_
diff _addrspace_remove_alloca(i1 %cond, ptr %p) {
; CHECK-LABEL: @select_
diff _addrspace_remove_alloca(
; CHECK-NEXT: entry:
-; CHECK-NOT: [[ALLOCA:%.*]] = alloca [32 x i8]
; CHECK-NEXT: ret i8 0
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll b/llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll
index 328c2cdae6679..da0f724abfde4 100644
--- a/llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/ptrauth-intrinsics.ll
@@ -77,8 +77,8 @@ define i64 @test_ptrauth_resign_auth(ptr %p) {
define i64 @test_ptrauth_resign_auth_mismatch(ptr %p) {
; CHECK-LABEL: @test_ptrauth_resign_auth_mismatch(
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64
-; CHECK-NEXT: [[SIGNED:%.*]] = call i64 @llvm.ptrauth.resign(i64 %tmp0, i32 1, i64 1234, i32 0, i64 10)
-; CHECK-NEXT: [[AUTHED:%.*]] = call i64 @llvm.ptrauth.auth(i64 %signed, i32 0, i64 42)
+; CHECK-NEXT: [[SIGNED:%.*]] = call i64 @llvm.ptrauth.resign(i64 [[TMP0]], i32 1, i64 1234, i32 0, i64 10)
+; CHECK-NEXT: [[AUTHED:%.*]] = call i64 @llvm.ptrauth.auth(i64 [[SIGNED]], i32 0, i64 42)
; CHECK-NEXT: ret i64 [[AUTHED]]
;
%tmp0 = ptrtoint ptr %p to i64
@@ -89,4 +89,4 @@ define i64 @test_ptrauth_resign_auth_mismatch(ptr %p) {
declare i64 @llvm.ptrauth.auth(i64, i32, i64)
declare i64 @llvm.ptrauth.sign(i64, i32, i64)
-declare i64 @llvm.ptrauth.resign(i64, i32, i64, i32, i64)
\ No newline at end of file
+declare i64 @llvm.ptrauth.resign(i64, i32, i64, i32, i64)
diff --git a/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll b/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll
index d5b7cc1bc4cc4..26c170bed6704 100644
--- a/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll
+++ b/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll
@@ -188,8 +188,8 @@ define i32 @and_signbit_ashr(i32 %x) {
define i32 @and_nosignbit_ashr(i32 %x) {
; CHECK-LABEL: @and_nosignbit_ashr(
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], 8388352
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = and i32 [[T0]], 8388352
+; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 2147418112 ; 0x7FFF0000
%r = ashr i32 %t0, 8
diff --git a/llvm/test/Transforms/InstCombine/range-check.ll b/llvm/test/Transforms/InstCombine/range-check.ll
index 3617abc03d37b..0d138b6ba7e79 100644
--- a/llvm/test/Transforms/InstCombine/range-check.ll
+++ b/llvm/test/Transforms/InstCombine/range-check.ll
@@ -7,8 +7,8 @@
define i1 @test_and1(i32 %x, i32 %n) {
; CHECK-LABEL: @test_and1(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sge i32 %x, 0
@@ -35,8 +35,8 @@ define i1 @test_and1_logical(i32 %x, i32 %n) {
define i1 @test_and2(i32 %x, i32 %n) {
; CHECK-LABEL: @test_and2(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sgt i32 %x, -1
@@ -63,8 +63,8 @@ define i1 @test_and2_logical(i32 %x, i32 %n) {
define i1 @test_and3(i32 %x, i32 %n) {
; CHECK-LABEL: @test_and3(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sgt i32 %nn, %x
@@ -76,8 +76,8 @@ define i1 @test_and3(i32 %x, i32 %n) {
define i1 @test_and3_logical(i32 %x, i32 %n) {
; CHECK-LABEL: @test_and3_logical(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sgt i32 %nn, %x
@@ -89,8 +89,8 @@ define i1 @test_and3_logical(i32 %x, i32 %n) {
define i1 @test_and4(i32 %x, i32 %n) {
; CHECK-LABEL: @test_and4(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sge i32 %nn, %x
@@ -102,8 +102,8 @@ define i1 @test_and4(i32 %x, i32 %n) {
define i1 @test_and4_logical(i32 %x, i32 %n) {
; CHECK-LABEL: @test_and4_logical(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sge i32 %nn, %x
@@ -115,8 +115,8 @@ define i1 @test_and4_logical(i32 %x, i32 %n) {
define i1 @test_or1(i32 %x, i32 %n) {
; CHECK-LABEL: @test_or1(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp slt i32 %x, 0
@@ -143,8 +143,8 @@ define i1 @test_or1_logical(i32 %x, i32 %n) {
define i1 @test_or2(i32 %x, i32 %n) {
; CHECK-LABEL: @test_or2(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sle i32 %x, -1
@@ -171,8 +171,8 @@ define i1 @test_or2_logical(i32 %x, i32 %n) {
define i1 @test_or3(i32 %x, i32 %n) {
; CHECK-LABEL: @test_or3(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sle i32 %nn, %x
@@ -184,8 +184,8 @@ define i1 @test_or3(i32 %x, i32 %n) {
define i1 @test_or3_logical(i32 %x, i32 %n) {
; CHECK-LABEL: @test_or3_logical(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp sle i32 %nn, %x
@@ -197,8 +197,8 @@ define i1 @test_or3_logical(i32 %x, i32 %n) {
define i1 @test_or4(i32 %x, i32 %n) {
; CHECK-LABEL: @test_or4(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp slt i32 %nn, %x
@@ -210,8 +210,8 @@ define i1 @test_or4(i32 %x, i32 %n) {
define i1 @test_or4_logical(i32 %x, i32 %n) {
; CHECK-LABEL: @test_or4_logical(
; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[NN]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
;
%nn = and i32 %n, 2147483647
%a = icmp slt i32 %nn, %x
diff --git a/llvm/test/Transforms/InstCombine/recurrence.ll b/llvm/test/Transforms/InstCombine/recurrence.ll
index c00ecd5112db6..f75e0d439c572 100644
--- a/llvm/test/Transforms/InstCombine/recurrence.ll
+++ b/llvm/test/Transforms/InstCombine/recurrence.ll
@@ -26,8 +26,8 @@ define i64 @test_or2(i64 %a, i64 %b) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[TMP0:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: tail call void @use(i64 [[TMP0]])
+; CHECK-NEXT: [[IV_NEXT:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
; CHECK-NEXT: br label [[LOOP]]
;
entry:
@@ -45,8 +45,8 @@ define i64 @test_or3(i64 %a, i64 %b) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[TMP0:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: tail call void @use(i64 [[TMP0]])
+; CHECK-NEXT: [[IV_NEXT:%.*]] = or i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
; CHECK-NEXT: br label [[LOOP]]
;
entry:
@@ -106,8 +106,8 @@ define i64 @test_and2(i64 %a, i64 %b) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: tail call void @use(i64 [[TMP0]])
+; CHECK-NEXT: [[IV_NEXT:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
; CHECK-NEXT: br label [[LOOP]]
;
entry:
@@ -125,8 +125,8 @@ define i64 @test_and3(i64 %a, i64 %b) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: tail call void @use(i64 [[TMP0]])
+; CHECK-NEXT: [[IV_NEXT:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]])
; CHECK-NEXT: br label [[LOOP]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll
index cc450ecb1c1ef..dbff28487036f 100644
--- a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll
@@ -6,8 +6,8 @@ define i1 @reduce_add_self(<8 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP3]], 0
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.add.v8i32(<8 x i1> %x)
ret i1 %res
@@ -18,8 +18,8 @@ define i32 @reduce_add_sext(<4 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP1]]), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = zext i4 [[TMP2]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
-; CHECK-NEXT: ret i32 [[TMP4]]
+; CHECK-NEXT: [[RES:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %sext)
@@ -30,8 +30,8 @@ define i64 @reduce_add_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_add_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]]
-; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i8 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext)
@@ -42,8 +42,8 @@ define i16 @reduce_add_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_add_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.ctpop.i16(i16 [[TMP1]]), !range [[RNG2:![0-9]+]]
-; CHECK-NEXT: [[TMP3:%.*]] = sub nsw i16 0, [[TMP2]]
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sub nsw i16 0, [[TMP2]]
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sext)
@@ -55,8 +55,8 @@ define i8 @reduce_add_zext_long(<128 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = sub i8 0, [[TMP3]]
-; CHECK-NEXT: ret i8 [[TMP4]]
+; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext)
@@ -69,11 +69,11 @@ define i8 @reduce_add_zext_long_external_use(<128 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = sub i8 0, [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP5]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP4]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext)
@@ -87,11 +87,11 @@ define i64 @reduce_add_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_add_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]]
-; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i8 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
index 52a2a2cd42903..4af9177bbfaaa 100644
--- a/llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
@@ -6,8 +6,8 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define i1 @reduce_and_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_and_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp eq i8 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.and.v8i32(<8 x i1> %x)
ret i1 %res
@@ -17,8 +17,8 @@ define i32 @reduce_and_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_and_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %sext)
@@ -29,8 +29,8 @@ define i64 @reduce_and_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_and_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %zext)
@@ -41,8 +41,8 @@ define i16 @reduce_and_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_and_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %sext)
@@ -53,8 +53,8 @@ define i8 @reduce_and_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_and_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %sext)
@@ -66,11 +66,11 @@ define i8 @reduce_and_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_and_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %sext)
@@ -84,11 +84,11 @@ define i64 @reduce_and_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_and_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %zext)
@@ -102,8 +102,8 @@ define i1 @reduce_and_pointer_cast(ptr %arg, ptr %arg1) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[LHS1:%.*]] = load i64, ptr [[ARG1:%.*]], align 8
; CHECK-NEXT: [[RHS2:%.*]] = load i64, ptr [[ARG:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[LHS1]], [[RHS2]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[ALL_EQ:%.*]] = icmp eq i64 [[LHS1]], [[RHS2]]
+; CHECK-NEXT: ret i1 [[ALL_EQ]]
;
bb:
%lhs = load <8 x i8>, ptr %arg1
@@ -120,8 +120,8 @@ define i1 @reduce_and_pointer_cast_wide(ptr %arg, ptr %arg1) {
; CHECK-NEXT: [[RHS:%.*]] = load <8 x i16>, ptr [[ARG:%.*]], align 16
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i16> [[LHS]], [[RHS]]
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i1> [[CMP]] to i8
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[TMP0]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[ALL_EQ:%.*]] = icmp eq i8 [[TMP0]], 0
+; CHECK-NEXT: ret i1 [[ALL_EQ]]
;
bb:
%lhs = load <8 x i16>, ptr %arg1
@@ -136,8 +136,8 @@ define i1 @reduce_and_pointer_cast_ne(ptr %arg, ptr %arg1) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[LHS1:%.*]] = load i64, ptr [[ARG1:%.*]], align 8
; CHECK-NEXT: [[RHS2:%.*]] = load i64, ptr [[ARG:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[LHS1]], [[RHS2]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[ALL_EQ:%.*]] = icmp ne i64 [[LHS1]], [[RHS2]]
+; CHECK-NEXT: ret i1 [[ALL_EQ]]
;
bb:
%lhs = load <8 x i8>, ptr %arg1
@@ -155,8 +155,8 @@ define i1 @reduce_and_pointer_cast_ne_wide(ptr %arg, ptr %arg1) {
; CHECK-NEXT: [[RHS:%.*]] = load <8 x i16>, ptr [[ARG:%.*]], align 16
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i16> [[LHS]], [[RHS]]
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i1> [[CMP]] to i8
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[TMP0]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[ALL_EQ:%.*]] = icmp ne i8 [[TMP0]], 0
+; CHECK-NEXT: ret i1 [[ALL_EQ]]
;
bb:
%lhs = load <8 x i16>, ptr %arg1
diff --git a/llvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll
index 8214bad098af8..f70820801602c 100644
--- a/llvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll
@@ -4,8 +4,8 @@
define i1 @reduce_mul_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_mul_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp eq i8 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.mul.v8i32(<8 x i1> %x)
ret i1 %res
@@ -15,8 +15,8 @@ define i32 @reduce_mul_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_mul_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %sext)
@@ -27,8 +27,8 @@ define i64 @reduce_mul_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_mul_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %zext)
@@ -39,8 +39,8 @@ define i16 @reduce_mul_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_mul_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %sext)
@@ -51,8 +51,8 @@ define i8 @reduce_mul_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_mul_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %sext)
@@ -64,11 +64,11 @@ define i8 @reduce_mul_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_mul_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %sext)
@@ -82,11 +82,11 @@ define i64 @reduce_mul_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_mul_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
index 80c1d97d2ebe3..48c139663b62d 100644
--- a/llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
@@ -6,8 +6,8 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define i1 @reduce_or_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_or_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.or.v8i32(<8 x i1> %x)
ret i1 %res
@@ -17,8 +17,8 @@ define i32 @reduce_or_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_or_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %sext)
@@ -29,8 +29,8 @@ define i64 @reduce_or_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_or_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %zext)
@@ -41,8 +41,8 @@ define i16 @reduce_or_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_or_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %sext)
@@ -53,8 +53,8 @@ define i8 @reduce_or_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_or_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i128 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %sext)
@@ -66,11 +66,11 @@ define i8 @reduce_or_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_or_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i128 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %sext)
@@ -84,11 +84,11 @@ define i64 @reduce_or_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_or_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %zext)
@@ -102,8 +102,8 @@ define i1 @reduce_or_pointer_cast(ptr %arg, ptr %arg1) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[LHS1:%.*]] = load i64, ptr [[ARG1:%.*]], align 8
; CHECK-NEXT: [[RHS2:%.*]] = load i64, ptr [[ARG:%.*]], align 8
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i64 [[LHS1]], [[RHS2]]
-; CHECK-NEXT: ret i1 [[DOTNOT]]
+; CHECK-NEXT: [[ANY_NE_NOT:%.*]] = icmp eq i64 [[LHS1]], [[RHS2]]
+; CHECK-NEXT: ret i1 [[ANY_NE_NOT]]
;
bb:
%lhs = load <8 x i8>, ptr %arg1
@@ -121,8 +121,8 @@ define i1 @reduce_or_pointer_cast_wide(ptr %arg, ptr %arg1) {
; CHECK-NEXT: [[RHS:%.*]] = load <8 x i16>, ptr [[ARG:%.*]], align 16
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i16> [[LHS]], [[RHS]]
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i1> [[CMP]] to i8
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i8 [[TMP0]], 0
-; CHECK-NEXT: ret i1 [[DOTNOT]]
+; CHECK-NEXT: [[ANY_NE_NOT:%.*]] = icmp eq i8 [[TMP0]], 0
+; CHECK-NEXT: ret i1 [[ANY_NE_NOT]]
;
bb:
%lhs = load <8 x i16>, ptr %arg1
@@ -139,8 +139,8 @@ define i1 @reduce_or_pointer_cast_ne(ptr %arg, ptr %arg1) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[LHS1:%.*]] = load i64, ptr [[ARG1:%.*]], align 8
; CHECK-NEXT: [[RHS2:%.*]] = load i64, ptr [[ARG:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[LHS1]], [[RHS2]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[ANY_NE:%.*]] = icmp ne i64 [[LHS1]], [[RHS2]]
+; CHECK-NEXT: ret i1 [[ANY_NE]]
;
bb:
%lhs = load <8 x i8>, ptr %arg1
@@ -157,8 +157,8 @@ define i1 @reduce_or_pointer_cast_ne_wide(ptr %arg, ptr %arg1) {
; CHECK-NEXT: [[RHS:%.*]] = load <8 x i16>, ptr [[ARG:%.*]], align 16
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i16> [[LHS]], [[RHS]]
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i1> [[CMP]] to i8
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[TMP0]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[ANY_NE:%.*]] = icmp ne i8 [[TMP0]], 0
+; CHECK-NEXT: ret i1 [[ANY_NE]]
;
bb:
%lhs = load <8 x i16>, ptr %arg1
diff --git a/llvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
index a2ac7ac189c70..6ac5f7d7ff933 100644
--- a/llvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
@@ -4,8 +4,8 @@
define i1 @reduce_smax_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_smax_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp eq i8 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.smax.v8i32(<8 x i1> %x)
ret i1 %res
@@ -15,8 +15,8 @@ define i32 @reduce_smax_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_smax_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %sext)
@@ -27,8 +27,8 @@ define i64 @reduce_smax_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_smax_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %zext)
@@ -39,8 +39,8 @@ define i16 @reduce_smax_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_smax_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %sext)
@@ -51,8 +51,8 @@ define i8 @reduce_smax_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_smax_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %sext)
@@ -64,11 +64,11 @@ define i8 @reduce_smax_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_smax_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %sext)
@@ -82,11 +82,11 @@ define i64 @reduce_smax_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_smax_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
index 1050f617385b6..06ec36828d8e2 100644
--- a/llvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
@@ -4,8 +4,8 @@
define i1 @reduce_smin_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_smin_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.smin.v8i32(<8 x i1> %x)
ret i1 %res
@@ -15,8 +15,8 @@ define i32 @reduce_smin_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_smin_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %sext)
@@ -27,8 +27,8 @@ define i64 @reduce_smin_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_smin_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %zext)
@@ -39,8 +39,8 @@ define i16 @reduce_smin_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_smin_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %sext)
@@ -51,8 +51,8 @@ define i8 @reduce_smin_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_smin_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i128 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %sext)
@@ -64,11 +64,11 @@ define i8 @reduce_smin_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_smin_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i128 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %sext)
@@ -82,11 +82,11 @@ define i64 @reduce_smin_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_smin_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll
index 73ce5840c17a6..323dd59fa301e 100644
--- a/llvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-umax-sext-zext-i1.ll
@@ -4,8 +4,8 @@
define i1 @reduce_umax_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_umax_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.umax.v8i32(<8 x i1> %x)
ret i1 %res
@@ -15,8 +15,8 @@ define i32 @reduce_umax_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_umax_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %sext)
@@ -27,8 +27,8 @@ define i64 @reduce_umax_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_umax_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %zext)
@@ -39,8 +39,8 @@ define i16 @reduce_umax_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_umax_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %sext)
@@ -51,8 +51,8 @@ define i8 @reduce_umax_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_umax_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i128 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %sext)
@@ -64,11 +64,11 @@ define i8 @reduce_umax_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_umax_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i128 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %sext)
@@ -82,11 +82,11 @@ define i64 @reduce_umax_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_umax_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll
index 3e12a1311b148..e56ba613318af 100644
--- a/llvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-umin-sext-zext-i1.ll
@@ -4,8 +4,8 @@
define i1 @reduce_umin_self(<8 x i1> %x) {
; CHECK-LABEL: @reduce_umin_self(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp eq i8 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.umin.v8i32(<8 x i1> %x)
ret i1 %res
@@ -15,8 +15,8 @@ define i32 @reduce_umin_sext(<4 x i1> %x) {
; CHECK-LABEL: @reduce_umin_sext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %sext)
@@ -27,8 +27,8 @@ define i64 @reduce_umin_zext(<8 x i1> %x) {
; CHECK-LABEL: @reduce_umin_zext(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %zext)
@@ -39,8 +39,8 @@ define i16 @reduce_umin_sext_same(<16 x i1> %x) {
; CHECK-LABEL: @reduce_umin_sext_same(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[RES]]
;
%sext = sext <16 x i1> %x to <16 x i16>
%res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %sext)
@@ -51,8 +51,8 @@ define i8 @reduce_umin_zext_long(<128 x i1> %x) {
; CHECK-LABEL: @reduce_umin_zext_long(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %sext)
@@ -64,11 +64,11 @@ define i8 @reduce_umin_zext_long_external_use(<128 x i1> %x) {
; CHECK-LABEL: @reduce_umin_zext_long_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i8
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP2]] to i8
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP3]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %sext)
@@ -82,11 +82,11 @@ define i64 @reduce_umin_zext_external_use(<8 x i1> %x) {
; CHECK-LABEL: @reduce_umin_zext_external_use(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
index 68864d5d05884..40175cab33059 100644
--- a/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
+++ b/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
@@ -6,8 +6,8 @@ define i1 @reduce_xor_self(<8 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i8 [[TMP3]], 0
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[RES:%.*]] = icmp ne i8 [[TMP3]], 0
+; CHECK-NEXT: ret i1 [[RES]]
;
%res = call i1 @llvm.vector.reduce.xor.v8i32(<8 x i1> %x)
ret i1 %res
@@ -19,8 +19,8 @@ define i32 @reduce_xor_sext(<4 x i1> %x) {
; CHECK-NEXT: [[TMP2:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP1]]), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = and i4 [[TMP2]], 1
; CHECK-NEXT: [[SEXT:%.*]] = sub nsw i4 0, [[TMP3]]
-; CHECK-NEXT: [[TMP4:%.*]] = sext i4 [[SEXT]] to i32
-; CHECK-NEXT: ret i32 [[TMP4]]
+; CHECK-NEXT: [[RES:%.*]] = sext i4 [[SEXT]] to i32
+; CHECK-NEXT: ret i32 [[RES]]
;
%sext = sext <4 x i1> %x to <4 x i32>
%res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %sext)
@@ -32,8 +32,8 @@ define i64 @reduce_xor_zext(<8 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]]
; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1
-; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64
-; CHECK-NEXT: ret i64 [[TMP4]]
+; CHECK-NEXT: [[RES:%.*]] = zext i8 [[TMP3]] to i64
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %zext)
@@ -59,8 +59,8 @@ define i8 @reduce_xor_zext_long(<128 x i1> %x) {
; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = sub nsw i8 0, [[TMP4]]
-; CHECK-NEXT: ret i8 [[TMP5]]
+; CHECK-NEXT: [[RES:%.*]] = sub nsw i8 0, [[TMP4]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %sext)
@@ -74,11 +74,11 @@ define i8 @reduce_xor_zext_long_external_use(<128 x i1> %x) {
; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = sub nsw i8 0, [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <128 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP6]] to i8
+; CHECK-NEXT: [[RES:%.*]] = sub nsw i8 0, [[TMP4]]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <128 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP5]] to i8
; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
-; CHECK-NEXT: ret i8 [[TMP5]]
+; CHECK-NEXT: ret i8 [[RES]]
;
%sext = sext <128 x i1> %x to <128 x i8>
%res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %sext)
@@ -93,11 +93,11 @@ define i64 @reduce_xor_zext_external_use(<8 x i1> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]]
; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1
-; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i1> [[X]], i64 0
-; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP5]] to i64
+; CHECK-NEXT: [[RES:%.*]] = zext i8 [[TMP3]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0
+; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i64
; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
-; CHECK-NEXT: ret i64 [[TMP4]]
+; CHECK-NEXT: ret i64 [[RES]]
;
%zext = zext <8 x i1> %x to <8 x i64>
%res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %zext)
diff --git a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll
index 2e552a7e6e0f0..107ef291bf439 100644
--- a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll
+++ b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-is-non-zero-and-no-underflow.ll
@@ -49,8 +49,8 @@ define i1 @t1(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -70,8 +70,8 @@ define i1 @t1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -92,8 +92,8 @@ define i1 @t2(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %offset, 0
call void @llvm.assume(i1 %cmp)
@@ -113,8 +113,8 @@ define i1 @t2_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %offset, 0
call void @llvm.assume(i1 %cmp)
@@ -137,8 +137,8 @@ define i1 @t3_oneuse0(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -161,8 +161,8 @@ define i1 @t3_oneuse0_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -184,8 +184,8 @@ define i1 @t4_oneuse1(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -208,8 +208,8 @@ define i1 @t4_oneuse1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -281,8 +281,8 @@ define i1 @t6_commutativity0(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -302,8 +302,8 @@ define i1 @t6_commutativity0_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -322,8 +322,8 @@ define i1 @t7_commutativity1(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -343,8 +343,8 @@ define i1 @t7_commutativity1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -363,8 +363,8 @@ define i1 @t7_commutativity3(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -384,8 +384,8 @@ define i1 @t7_commutativity3_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -406,8 +406,8 @@ define i1 @t8(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -427,8 +427,8 @@ define i1 @t8_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -449,8 +449,8 @@ define i1 @t9(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
@@ -470,8 +470,8 @@ define i1 @t9_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%cmp = icmp slt i8 %base, 0
call void @llvm.assume(i1 %cmp)
diff --git a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll
index 049b61eb2d81b..0be4457ad3fc0 100644
--- a/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll
+++ b/llvm/test/Transforms/InstCombine/result-of-add-of-negative-or-zero-is-non-zero-and-no-underflow.ll
@@ -11,8 +11,8 @@ define i1 @t0(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -27,8 +27,8 @@ define i1 @t0_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -46,8 +46,8 @@ define i1 @t1_oneuse0(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -65,8 +65,8 @@ define i1 @t1_oneuse0_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[ADJUSTED]], 0
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -83,8 +83,8 @@ define i1 @t2_oneuse1(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -102,8 +102,8 @@ define i1 @t2_oneuse1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[NO_UNDERFLOW:%.*]] = icmp ule i8 [[ADJUSTED]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -160,8 +160,8 @@ define i1 @t4_commutativity0(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -176,8 +176,8 @@ define i1 @t4_commutativity0_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -191,8 +191,8 @@ define i1 @t5_commutativity1(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -207,8 +207,8 @@ define i1 @t5_commutativity1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -222,8 +222,8 @@ define i1 @t6_commutativity3(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -238,8 +238,8 @@ define i1 @t6_commutativity3_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -255,8 +255,8 @@ define i1 @t7(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -271,8 +271,8 @@ define i1 @t7_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[OFFSET]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i8 [[TMP1]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[TMP1]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -288,8 +288,8 @@ define i1 @t8(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -304,8 +304,8 @@ define i1 @t8_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: [[ADJUSTED:%.*]] = add i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[BASE]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = add i8 %base, %offset
call void @use8(i8 %adjusted)
diff --git a/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll b/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
index 582916827b61f..2f845f5a98cfc 100644
--- a/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
+++ b/llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and-no-overflow.ll
@@ -24,8 +24,8 @@ define i1 @t0_noncanonical_ignoreme(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -45,8 +45,8 @@ define i1 @t0_noncanonical_ignoreme_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -66,8 +66,8 @@ define i1 @t1(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -87,8 +87,8 @@ define i1 @t1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -203,8 +203,8 @@ define i1 @t3_commutability0(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -224,8 +224,8 @@ define i1 @t3_commutability0_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -244,8 +244,8 @@ define i1 @t4_commutability1(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -265,8 +265,8 @@ define i1 @t4_commutability1_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -285,8 +285,8 @@ define i1 @t5_commutability2(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -306,8 +306,8 @@ define i1 @t5_commutability2_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -384,8 +384,8 @@ define i1 @t7(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]])
; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -405,8 +405,8 @@ define i1 @t7_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]])
; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -513,8 +513,8 @@ define i1 @t9_commutative(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]])
; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -534,8 +534,8 @@ define i1 @t9_commutative_logical(i8 %base, i8 %offset) {
; CHECK-NEXT: call void @use1(i1 [[UNDERFLOW]])
; CHECK-NEXT: [[NULL:%.*]] = icmp eq i8 [[BASE]], [[OFFSET]]
; CHECK-NEXT: call void @use1(i1 [[NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -558,8 +558,8 @@ define i1 @t10(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -582,8 +582,8 @@ define i1 @t10_logical(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -605,8 +605,8 @@ define i1 @t11_commutative(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -629,8 +629,8 @@ define i1 @t11_commutative_logical(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp ne i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -653,8 +653,8 @@ define i1 @t12(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -677,8 +677,8 @@ define i1 @t12_logical(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -700,8 +700,8 @@ define i1 @t13(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -724,8 +724,8 @@ define i1 @t13_logical(i64 %base, ptr nonnull %offsetptr) {
; CHECK-NEXT: call void @use1(i1 [[NO_UNDERFLOW]])
; CHECK-NEXT: [[NOT_NULL:%.*]] = icmp eq i64 [[OFFSET]], [[BASE]]
; CHECK-NEXT: call void @use1(i1 [[NOT_NULL]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i64 [[OFFSET]], [[BASE]]
+; CHECK-NEXT: ret i1 [[R]]
;
%offset = ptrtoint ptr %offsetptr to i64
@@ -785,8 +785,8 @@ define i1 @base_ult_offset(i8 %base, i8 %offset) {
; CHECK-LABEL: @base_ult_offset(
; CHECK-NEXT: [[ADJUSTED:%.*]] = sub i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -800,8 +800,8 @@ define i1 @base_ult_offset_logical(i8 %base, i8 %offset) {
; CHECK-LABEL: @base_ult_offset_logical(
; CHECK-NEXT: [[ADJUSTED:%.*]] = sub i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -814,8 +814,8 @@ define i1 @base_uge_offset(i8 %base, i8 %offset) {
; CHECK-LABEL: @base_uge_offset(
; CHECK-NEXT: [[ADJUSTED:%.*]] = sub i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
@@ -829,8 +829,8 @@ define i1 @base_uge_offset_logical(i8 %base, i8 %offset) {
; CHECK-LABEL: @base_uge_offset_logical(
; CHECK-NEXT: [[ADJUSTED:%.*]] = sub i8 [[BASE:%.*]], [[OFFSET:%.*]]
; CHECK-NEXT: call void @use8(i8 [[ADJUSTED]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]]
+; CHECK-NEXT: ret i1 [[R]]
;
%adjusted = sub i8 %base, %offset
call void @use8(i8 %adjusted)
diff --git a/llvm/test/Transforms/InstCombine/sadd-with-overflow.ll b/llvm/test/Transforms/InstCombine/sadd-with-overflow.ll
index 9f1435a2cff55..4b37ccbe3370b 100644
--- a/llvm/test/Transforms/InstCombine/sadd-with-overflow.ll
+++ b/llvm/test/Transforms/InstCombine/sadd-with-overflow.ll
@@ -9,8 +9,8 @@ declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8)
define { i32, i1 } @simple_fold(i32 %x) {
; CHECK-LABEL: @simple_fold(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 20)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 20)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = add nsw i32 %x, 7
%b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 13)
@@ -30,8 +30,8 @@ define { i32, i1 } @fold_mixed_signs(i32 %x) {
define { i8, i1 } @fold_on_constant_add_no_overflow(i8 %x) {
; CHECK-LABEL: @fold_on_constant_add_no_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X:%.*]], i8 127)
-; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X:%.*]], i8 127)
+; CHECK-NEXT: ret { i8, i1 } [[B]]
;
%a = add nsw i8 %x, 100
%b = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %a, i8 27)
@@ -51,8 +51,8 @@ define { i8, i1 } @no_fold_on_constant_add_overflow(i8 %x) {
define { <2 x i32>, <2 x i1> } @fold_simple_splat_constant(<2 x i32> %x) {
; CHECK-LABEL: @fold_simple_splat_constant(
-; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 42, i32 42>)
-; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 42, i32 42>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
;
%a = add nsw <2 x i32> %x, <i32 12, i32 12>
%b = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
@@ -83,8 +83,8 @@ define { <2 x i32>, <2 x i1> } @no_fold_splat_not_constant(<2 x i32> %x, <2 x i3
define { i32, i1 } @fold_nuwnsw(i32 %x) {
; CHECK-LABEL: @fold_nuwnsw(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = add nuw nsw i32 %x, 12
%b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 30)
@@ -115,8 +115,8 @@ define { i32, i1 } @no_fold_wrapped_add(i32 %x) {
define { i32, i1 } @fold_sub_simple(i32 %x) {
; CHECK-LABEL: @fold_sub_simple(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = sub nsw i32 %x, -12
%b = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 30)
diff --git a/llvm/test/Transforms/InstCombine/sadd_sat.ll b/llvm/test/Transforms/InstCombine/sadd_sat.ll
index 44381b8d45113..5ccb6f92b6c72 100644
--- a/llvm/test/Transforms/InstCombine/sadd_sat.ll
+++ b/llvm/test/Transforms/InstCombine/sadd_sat.ll
@@ -77,9 +77,9 @@ define i32 @smul_sat32(i32 %a, i32 %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
; CHECK-NEXT: [[ADD:%.*]] = mul nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP0]], i64 -2147483648)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
; CHECK-NEXT: ret i32 [[CONV7]]
;
entry:
@@ -293,9 +293,9 @@ define signext i4 @sadd_sat4(i4 signext %a, i4 signext %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i4 [[A:%.*]] to i32
; CHECK-NEXT: [[CONV1:%.*]] = sext i4 [[B:%.*]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 7)
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 -8)
-; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[TMP1]] to i4
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 7)
+; CHECK-NEXT: [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -8)
+; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[SPEC_STORE_SELECT10]] to i4
; CHECK-NEXT: ret i4 [[CONV9]]
;
entry:
@@ -316,9 +316,9 @@ define signext i4 @ssub_sat4(i4 signext %a, i4 signext %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i4 [[A:%.*]] to i32
; CHECK-NEXT: [[CONV1:%.*]] = sext i4 [[B:%.*]] to i32
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV1]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smin.i32(i32 [[SUB]], i32 7)
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 -8)
-; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[TMP1]] to i4
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[SUB]], i32 7)
+; CHECK-NEXT: [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -8)
+; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[SPEC_STORE_SELECT10]] to i4
; CHECK-NEXT: ret i4 [[CONV9]]
;
entry:
@@ -405,9 +405,9 @@ define <4 x i32> @sadd_satv4i4(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @sadd_satv4i4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[ADD]], <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP0]], <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[ADD]], <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[SPEC_STORE_SELECT]], <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)
+; CHECK-NEXT: ret <4 x i32> [[SPEC_STORE_SELECT8]]
;
entry:
%add = add <4 x i32> %a, %b
@@ -422,9 +422,9 @@ define <4 x i32> @ssub_satv4i4(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @ssub_satv4i4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD:%.*]] = sub <4 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[ADD]], <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP0]], <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[ADD]], <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[SPEC_STORE_SELECT]], <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)
+; CHECK-NEXT: ret <4 x i32> [[SPEC_STORE_SELECT8]]
;
entry:
%add = sub <4 x i32> %a, %b
@@ -440,8 +440,8 @@ define i32 @sadd_sat32_extrause_1(i32 %a, i32 %b) {
; CHECK-LABEL: @sadd_sat32_extrause_1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[B:%.*]], i32 [[A:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[TMP0]] to i64
-; CHECK-NEXT: call void @use64(i64 [[TMP1]])
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = sext i32 [[TMP0]] to i64
+; CHECK-NEXT: call void @use64(i64 [[SPEC_STORE_SELECT8]])
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
@@ -463,10 +463,10 @@ define i32 @sadd_sat32_extrause_2(i32 %a, i32 %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP0]], i64 -2147483648)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT: call void @use64(i64 [[TMP0]])
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
+; CHECK-NEXT: call void @use64(i64 [[SPEC_STORE_SELECT]])
; CHECK-NEXT: ret i32 [[CONV7]]
;
entry:
@@ -511,9 +511,9 @@ define i32 @sadd_sat32_extrause_3(i32 %a, i32 %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP0]], i64 -2147483648)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
; CHECK-NEXT: call void @use64(i64 [[ADD]])
; CHECK-NEXT: ret i32 [[CONV7]]
;
@@ -559,9 +559,9 @@ define i32 @sadd_sat32_trunc(i32 %a, i32 %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 32767)
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP0]], i64 -32768)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 32767)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -32768)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
; CHECK-NEXT: ret i32 [[CONV7]]
;
entry:
@@ -601,9 +601,9 @@ define i8 @sadd_sat8_ext8(i8 %a, i16 %b) {
; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i32
; CHECK-NEXT: [[CONV1:%.*]] = sext i16 [[B:%.*]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 127)
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 -128)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[TMP1]] to i8
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 127)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -128)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[SPEC_STORE_SELECT8]] to i8
; CHECK-NEXT: ret i8 [[CONV7]]
;
entry:
@@ -624,8 +624,8 @@ define i32 @sadd_sat32_zext(i32 %a, i32 %b) {
; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[CONV1:%.*]] = zext i32 [[B:%.*]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.umin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP0]] to i32
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.umin.i64(i64 [[ADD]], i64 2147483647)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT]] to i32
; CHECK-NEXT: ret i32 [[CONV7]]
;
entry:
@@ -662,8 +662,8 @@ define i64 @sadd_sat32_notrunc(i32 %a, i32 %b) {
; CHECK-LABEL: @sadd_sat32_notrunc(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[B:%.*]], i32 [[A:%.*]])
-; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[TMP0]] to i64
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = sext i32 [[TMP0]] to i64
+; CHECK-NEXT: ret i64 [[SPEC_STORE_SELECT8]]
;
entry:
%conv = sext i32 %a to i64
@@ -742,9 +742,9 @@ define i32 @ashrA31(i64 %a, i32 %b) {
; CHECK-NEXT: [[CONV:%.*]] = ashr i64 [[A:%.*]], 31
; CHECK-NEXT: [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV]], [[CONV1]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648)
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP0]], i64 2147483647)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP1]] to i32
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[SPEC_STORE_SELECT]], i64 2147483647)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32
; CHECK-NEXT: ret i32 [[CONV7]]
;
entry:
@@ -785,9 +785,9 @@ define <2 x i8> @ashrv2i8(<2 x i16> %a, <2 x i8> %b) {
; CHECK-NEXT: [[CONV:%.*]] = ashr <2 x i16> [[A:%.*]], <i16 8, i16 12>
; CHECK-NEXT: [[CONV1:%.*]] = sext <2 x i8> [[B:%.*]] to <2 x i16>
; CHECK-NEXT: [[ADD:%.*]] = add <2 x i16> [[CONV]], [[CONV1]]
-; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[ADD]], <2 x i16> <i16 -128, i16 -128>)
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> <i16 127, i16 127>)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc <2 x i16> [[TMP1]] to <2 x i8>
+; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[ADD]], <2 x i16> <i16 -128, i16 -128>)
+; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[SPEC_STORE_SELECT]], <2 x i16> <i16 127, i16 127>)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc <2 x i16> [[SPEC_STORE_SELECT8]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[CONV7]]
;
entry:
@@ -827,8 +827,8 @@ define i16 @or(i8 %X, i16 %Y) {
; CHECK-NEXT: [[TMP1:%.*]] = trunc i16 [[Y:%.*]] to i8
; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], -16
; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.ssub.sat.i8(i8 [[X:%.*]], i8 [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = sext i8 [[TMP3]] to i16
-; CHECK-NEXT: ret i16 [[TMP4]]
+; CHECK-NEXT: [[L12:%.*]] = sext i8 [[TMP3]] to i16
+; CHECK-NEXT: ret i16 [[L12]]
;
%conv10 = sext i8 %X to i16
%conv14 = or i16 %Y, 65520
@@ -844,8 +844,8 @@ define i16 @const(i8 %X) {
; CHECK-LABEL: @const(
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smin.i8(i8 [[X:%.*]], i8 117)
; CHECK-NEXT: [[NARROW:%.*]] = add nsw i8 [[TMP1]], 10
-; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[NARROW]] to i16
-; CHECK-NEXT: ret i16 [[TMP2]]
+; CHECK-NEXT: [[L12:%.*]] = sext i8 [[NARROW]] to i16
+; CHECK-NEXT: ret i16 [[L12]]
;
%conv10 = sext i8 %X to i16
%sub = add i16 %conv10, 10
diff --git a/llvm/test/Transforms/InstCombine/sdiv-canonicalize.ll b/llvm/test/Transforms/InstCombine/sdiv-canonicalize.ll
index 7ac1d76d94a9f..3184395ccb12b 100644
--- a/llvm/test/Transforms/InstCombine/sdiv-canonicalize.ll
+++ b/llvm/test/Transforms/InstCombine/sdiv-canonicalize.ll
@@ -96,8 +96,8 @@ define i64 @test_sdiv_canonicalize_constexpr(i64 %L1) {
define i32 @sdiv_abs_nsw(i32 %x) {
; CHECK-LABEL: @sdiv_abs_nsw(
-; CHECK-NEXT: [[DOTINV:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT: [[R:%.*]] = select i1 [[DOTINV]], i32 1, i32 -1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -1
+; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i32 1, i32 -1
; CHECK-NEXT: ret i32 [[R]]
;
%a = call i32 @llvm.abs.i32(i32 %x, i1 true)
@@ -107,8 +107,8 @@ define i32 @sdiv_abs_nsw(i32 %x) {
define <4 x i32> @sdiv_abs_nsw_vec(<4 x i32> %x) {
; CHECK-LABEL: @sdiv_abs_nsw_vec(
-; CHECK-NEXT: [[DOTINV:%.*]] = icmp sgt <4 x i32> [[X:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTINV]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i32> [[R]]
;
%a = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %x, i1 true)
diff --git a/llvm/test/Transforms/InstCombine/sdiv-guard.ll b/llvm/test/Transforms/InstCombine/sdiv-guard.ll
index 85eb11b09eaef..ba9670924108b 100644
--- a/llvm/test/Transforms/InstCombine/sdiv-guard.ll
+++ b/llvm/test/Transforms/InstCombine/sdiv-guard.ll
@@ -7,7 +7,7 @@ declare void @llvm.experimental.guard(i1, ...)
define i32 @a(i1 %flag, i32 %X) nounwind readnone {
; CHECK-LABEL: @a(
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 0
-; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #2 [ "deopt"() ]
+; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #[[ATTR2:[0-9]+]] [ "deopt"() ]
; CHECK-NEXT: [[R:%.*]] = sdiv i32 100, [[X]]
; CHECK-NEXT: ret i32 [[R]]
;
diff --git a/llvm/test/Transforms/InstCombine/sdiv-of-non-negative-by-negative-power-of-two.ll b/llvm/test/Transforms/InstCombine/sdiv-of-non-negative-by-negative-power-of-two.ll
index 91c690e88ee5c..7e19d5a571054 100644
--- a/llvm/test/Transforms/InstCombine/sdiv-of-non-negative-by-negative-power-of-two.ll
+++ b/llvm/test/Transforms/InstCombine/sdiv-of-non-negative-by-negative-power-of-two.ll
@@ -13,8 +13,8 @@ define i8 @t0(i8 %x, i8 %y) {
; CHECK-LABEL: @t0(
; CHECK-NEXT: [[X_IS_NONNEGATIVE:%.*]] = icmp sgt i8 [[X:%.*]], -1
; CHECK-NEXT: call void @llvm.assume(i1 [[X_IS_NONNEGATIVE]])
-; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X]], 5
-; CHECK-NEXT: [[DIV:%.*]] = sub nsw i8 0, [[TMP1]]
+; CHECK-NEXT: [[DIV1:%.*]] = lshr i8 [[X]], 5
+; CHECK-NEXT: [[DIV:%.*]] = sub nsw i8 0, [[DIV1]]
; CHECK-NEXT: ret i8 [[DIV]]
;
%x_is_nonnegative = icmp sge i8 %x, 0
diff --git a/llvm/test/Transforms/InstCombine/select-2.ll b/llvm/test/Transforms/InstCombine/select-2.ll
index b6fe9a16cdc09..2e4161f5d80aa 100644
--- a/llvm/test/Transforms/InstCombine/select-2.ll
+++ b/llvm/test/Transforms/InstCombine/select-2.ll
@@ -33,8 +33,8 @@ define i32 @t2(i32 %c, i32 %x) {
define float @t3(float %x, float %y) {
; CHECK-LABEL: @t3(
; CHECK-NEXT: [[T1:%.*]] = fcmp ogt float [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[X_OP:%.*]] = fadd fast float [[X]], 1.000000e+00
-; CHECK-NEXT: [[T3:%.*]] = select i1 [[T1]], float [[X_OP]], float 2.000000e+00
+; CHECK-NEXT: [[TMP1:%.*]] = fadd fast float [[X]], 1.000000e+00
+; CHECK-NEXT: [[T3:%.*]] = select i1 [[T1]], float [[TMP1]], float 2.000000e+00
; CHECK-NEXT: ret float [[T3]]
;
%t1 = fcmp ogt float %x, %y
@@ -45,8 +45,8 @@ define float @t3(float %x, float %y) {
define i8 @ashr_exact_poison_constant_fold(i1 %b, i8 %x) {
; CHECK-LABEL: @ashr_exact_poison_constant_fold(
-; CHECK-NEXT: [[X_OP:%.*]] = ashr exact i8 [[X:%.*]], 3
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 5
+; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i8 [[X:%.*]], 3
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 5
; CHECK-NEXT: ret i8 [[R]]
;
%s = select i1 %b, i8 %x, i8 42
@@ -56,8 +56,8 @@ define i8 @ashr_exact_poison_constant_fold(i1 %b, i8 %x) {
define i8 @ashr_exact(i1 %b, i8 %x) {
; CHECK-LABEL: @ashr_exact(
-; CHECK-NEXT: [[X_OP:%.*]] = ashr exact i8 [[X:%.*]], 3
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 2
+; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i8 [[X:%.*]], 3
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 2
; CHECK-NEXT: ret i8 [[R]]
;
%s = select i1 %b, i8 %x, i8 16
@@ -67,8 +67,8 @@ define i8 @ashr_exact(i1 %b, i8 %x) {
define i8 @shl_nsw_nuw_poison_constant_fold(i1 %b, i8 %x) {
; CHECK-LABEL: @shl_nsw_nuw_poison_constant_fold(
-; CHECK-NEXT: [[X_OP:%.*]] = shl nuw nsw i8 16, [[X:%.*]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 -128, i8 [[X_OP]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i8 16, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 -128, i8 [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%s = select i1 %b, i8 3, i8 %x
@@ -78,8 +78,8 @@ define i8 @shl_nsw_nuw_poison_constant_fold(i1 %b, i8 %x) {
define i8 @shl_nsw_nuw(i1 %b, i8 %x) {
; CHECK-LABEL: @shl_nsw_nuw(
-; CHECK-NEXT: [[X_OP:%.*]] = shl nuw nsw i8 7, [[X:%.*]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 56, i8 [[X_OP]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i8 7, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 56, i8 [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%s = select i1 %b, i8 3, i8 %x
@@ -89,8 +89,8 @@ define i8 @shl_nsw_nuw(i1 %b, i8 %x) {
define i8 @add_nsw_poison_constant_fold(i1 %b, i8 %x) {
; CHECK-LABEL: @add_nsw_poison_constant_fold(
-; CHECK-NEXT: [[X_OP:%.*]] = add nsw i8 [[X:%.*]], 64
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 -127
+; CHECK-NEXT: [[TMP1:%.*]] = add nsw i8 [[X:%.*]], 64
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 -127
; CHECK-NEXT: ret i8 [[R]]
;
%s = select i1 %b, i8 %x, i8 65
@@ -100,8 +100,8 @@ define i8 @add_nsw_poison_constant_fold(i1 %b, i8 %x) {
define i8 @add_nsw(i1 %b, i8 %x) {
; CHECK-LABEL: @add_nsw(
-; CHECK-NEXT: [[X_OP:%.*]] = add nsw i8 [[X:%.*]], 64
-; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 71
+; CHECK-NEXT: [[TMP1:%.*]] = add nsw i8 [[X:%.*]], 64
+; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 71
; CHECK-NEXT: ret i8 [[R]]
;
%s = select i1 %b, i8 %x, i8 7
diff --git a/llvm/test/Transforms/InstCombine/select-and-or.ll b/llvm/test/Transforms/InstCombine/select-and-or.ll
index 883652e1f761d..b0f2138c7c571 100644
--- a/llvm/test/Transforms/InstCombine/select-and-or.ll
+++ b/llvm/test/Transforms/InstCombine/select-and-or.ll
@@ -70,8 +70,8 @@ define i1 @logical_or_cond_reuse(i1 %a, i1 %b) {
define i1 @logical_and_not_cond_reuse(i1 %a, i1 %b) {
; CHECK-LABEL: @logical_and_not_cond_reuse(
-; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]]
+; CHECK-NEXT: [[NOT_A:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[NOT_A]], i1 true, i1 [[B:%.*]]
; CHECK-NEXT: ret i1 [[RES]]
;
%a.not = xor i1 %a, true
@@ -81,8 +81,8 @@ define i1 @logical_and_not_cond_reuse(i1 %a, i1 %b) {
define i1 @logical_or_not_cond_reuse(i1 %a, i1 %b) {
; CHECK-LABEL: @logical_or_not_cond_reuse(
-; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[A_NOT]], i1 [[B:%.*]], i1 false
+; CHECK-NEXT: [[NOT_A:%.*]] = xor i1 [[A:%.*]], true
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[NOT_A]], i1 [[B:%.*]], i1 false
; CHECK-NEXT: ret i1 [[RES]]
;
%a.not = xor i1 %a, true
diff --git a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
index 624728e190cff..01faae90a65d7 100644
--- a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
+++ b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
@@ -490,7 +490,7 @@ define i32 @test_cttz_not_bw_multiuse(i32 %x) {
define <2 x i32> @test_ctlz_bw_vec(<2 x i32> %x) {
; CHECK-LABEL: @test_ctlz_bw_vec(
-; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i32> [[CT]]
;
%ct = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
@@ -501,7 +501,7 @@ define <2 x i32> @test_ctlz_bw_vec(<2 x i32> %x) {
define <2 x i32> @test_ctlz_not_bw_vec(<2 x i32> %x) {
; CHECK-LABEL: @test_ctlz_not_bw_vec(
-; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 true), !range [[RNG1]]
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[CMP_NOT]], <2 x i32> zeroinitializer, <2 x i32> [[CT]]
; CHECK-NEXT: ret <2 x i32> [[RES]]
@@ -514,7 +514,7 @@ define <2 x i32> @test_ctlz_not_bw_vec(<2 x i32> %x) {
define <2 x i32> @test_cttz_bw_vec(<2 x i32> %x) {
; CHECK-LABEL: @test_cttz_bw_vec(
-; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG1]]
; CHECK-NEXT: ret <2 x i32> [[CT]]
;
%ct = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true)
@@ -525,7 +525,7 @@ define <2 x i32> @test_cttz_bw_vec(<2 x i32> %x) {
define <2 x i32> @test_cttz_not_bw_vec(<2 x i32> %x) {
; CHECK-LABEL: @test_cttz_not_bw_vec(
-; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true), !range [[RNG1]]
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[CMP_NOT]], <2 x i32> zeroinitializer, <2 x i32> [[CT]]
; CHECK-NEXT: ret <2 x i32> [[RES]]
diff --git a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
index 0c4525a2731d3..2a210d659e66f 100644
--- a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
+++ b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
@@ -44,7 +44,7 @@ define i32 @select_clz_to_ctz_preserve_flag(i32 %a) {
define <2 x i32> @select_clz_to_ctz_vec(<2 x i32> %a) {
; CHECK-LABEL: @select_clz_to_ctz_vec(
-; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[A:%.*]], i1 true)
+; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[A:%.*]], i1 true), !range [[RNG0]]
; CHECK-NEXT: ret <2 x i32> [[COND]]
;
%sub = sub <2 x i32> zeroinitializer, %a
@@ -202,7 +202,7 @@ define <2 x i32> @select_clz_to_ctz_vec_with_undef(<2 x i32> %a) {
; CHECK-LABEL: @select_clz_to_ctz_vec_with_undef(
; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i32> zeroinitializer, [[A:%.*]]
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[SUB]], [[A]]
-; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[AND]], i1 true)
+; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[AND]], i1 true), !range [[RNG0]]
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq <2 x i32> [[A]], zeroinitializer
; CHECK-NEXT: [[SUB1:%.*]] = xor <2 x i32> [[LZ]], <i32 31, i32 undef>
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[TOBOOL]], <2 x i32> [[LZ]], <2 x i32> [[SUB1]]
@@ -222,8 +222,8 @@ define i4 @PR45762(i3 %x4) {
; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2:![0-9]+]]
; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4
; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]]
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i3 [[X4]], 0
-; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]]
+; CHECK-NEXT: [[OR_69_NOT:%.*]] = icmp eq i3 [[X4]], 0
+; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[OR_69_NOT]], i4 0, i4 [[T7]]
; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_231]]
; CHECK-NEXT: ret i4 [[SEL_71]]
;
@@ -251,8 +251,8 @@ define i4 @PR45762_logical(i3 %x4) {
; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2]]
; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4
; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]]
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i3 [[X4]], 0
-; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]]
+; CHECK-NEXT: [[OR_69_NOT:%.*]] = icmp eq i3 [[X4]], 0
+; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[OR_69_NOT]], i4 0, i4 [[T7]]
; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_231]]
; CHECK-NEXT: ret i4 [[SEL_71]]
;
diff --git a/llvm/test/Transforms/InstCombine/select-gep.ll b/llvm/test/Transforms/InstCombine/select-gep.ll
index 0f3445eae85fb..f3a906139bdf3 100644
--- a/llvm/test/Transforms/InstCombine/select-gep.ll
+++ b/llvm/test/Transforms/InstCombine/select-gep.ll
@@ -59,8 +59,8 @@ define ptr @test1d(ptr %p, ptr %q) {
define ptr @test2(ptr %p, i64 %x, i64 %y) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[X:%.*]], i64 [[Y:%.*]])
-; CHECK-NEXT: [[SELECT:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[TMP1]]
+; CHECK-NEXT: [[SELECT_V:%.*]] = call i64 @llvm.umax.i64(i64 [[X:%.*]], i64 [[Y:%.*]])
+; CHECK-NEXT: [[SELECT:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[SELECT_V]]
; CHECK-NEXT: ret ptr [[SELECT]]
;
%gep1 = getelementptr inbounds i32, ptr %p, i64 %x
diff --git a/llvm/test/Transforms/InstCombine/select-icmp-and.ll b/llvm/test/Transforms/InstCombine/select-icmp-and.ll
index 9dd19bbc6a943..283c01b3aacd5 100644
--- a/llvm/test/Transforms/InstCombine/select-icmp-and.ll
+++ b/llvm/test/Transforms/InstCombine/select-icmp-and.ll
@@ -315,8 +315,8 @@ define i32 @test15a(i32 %X) {
define i32 @test15b(i32 %X) {
; CHECK-LABEL: @test15b(
; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 32
-; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], 32
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[T1]], 32
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %X, 32
%t2 = icmp eq i32 %t1, 0
@@ -352,8 +352,8 @@ define i32 @test15d(i32 %X) {
define i32 @test15e(i32 %X) {
; CHECK-LABEL: @test15e(
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T1]], 256
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = and i32 [[T1]], 256
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %X, 128
%t2 = icmp ne i32 %t1, 0
@@ -366,8 +366,8 @@ define i32 @test15f(i32 %X) {
; CHECK-LABEL: @test15f(
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T1]], 256
-; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 256
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[TMP1]], 256
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %X, 128
%t2 = icmp ne i32 %t1, 0
@@ -378,8 +378,8 @@ define i32 @test15f(i32 %X) {
;; (a & 8) ? -1 : -9
define i32 @test15g(i32 %X) {
; CHECK-LABEL: @test15g(
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -9
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = or i32 [[X:%.*]], -9
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %X, 8
%t2 = icmp ne i32 %t1, 0
@@ -391,8 +391,8 @@ define i32 @test15g(i32 %X) {
define i32 @test15h(i32 %X) {
; CHECK-LABEL: @test15h(
; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
-; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], -1
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[T1]], -1
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %X, 8
%t2 = icmp ne i32 %t1, 0
@@ -437,9 +437,9 @@ define i32 @clear_to_set(i32 %x) {
; CHECK-LABEL: @clear_to_set(
; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], -3
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[T1]], -3
; CHECK-NEXT: call void @use1(i1 [[T2]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %x, 8
%t2 = icmp eq i32 %t1, 0
@@ -455,9 +455,9 @@ define i32 @clear_to_clear(i32 %x) {
; CHECK-LABEL: @clear_to_clear(
; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T1]], -11
+; CHECK-NEXT: [[T3:%.*]] = or i32 [[T1]], -11
; CHECK-NEXT: call void @use1(i1 [[T2]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %x, 8
%t2 = icmp eq i32 %t1, 0
@@ -473,9 +473,9 @@ define i32 @set_to_set(i32 %x) {
; CHECK-LABEL: @set_to_set(
; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T1]], -11
+; CHECK-NEXT: [[T3:%.*]] = or i32 [[T1]], -11
; CHECK-NEXT: call void @use1(i1 [[T2]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %x, 8
%t2 = icmp ne i32 %t1, 0
@@ -491,9 +491,9 @@ define i32 @set_to_clear(i32 %x) {
; CHECK-LABEL: @set_to_clear(
; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T1]], -3
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[T1]], -3
; CHECK-NEXT: call void @use1(i1 [[T2]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = and i32 %x, 8
%t2 = icmp ne i32 %t1, 0
@@ -507,8 +507,8 @@ define i32 @set_to_clear(i32 %x) {
define i8 @clear_to_set_decomposebittest(i8 %x) {
; CHECK-LABEL: @clear_to_set_decomposebittest(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], -125
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = xor i8 [[TMP1]], -125
+; CHECK-NEXT: ret i8 [[T3]]
;
%t2 = icmp sgt i8 %x, -1
%t3 = select i1 %t2, i8 131, i8 3
@@ -520,8 +520,8 @@ define i8 @clear_to_set_decomposebittest(i8 %x) {
define i8 @clear_to_clear_decomposebittest(i8 %x) {
; CHECK-LABEL: @clear_to_clear_decomposebittest(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 3
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = or i8 [[TMP1]], 3
+; CHECK-NEXT: ret i8 [[T3]]
;
%t2 = icmp sgt i8 %x, -1
%t3 = select i1 %t2, i8 3, i8 131
@@ -533,8 +533,8 @@ define i8 @clear_to_clear_decomposebittest(i8 %x) {
define i8 @set_to_set_decomposebittest(i8 %x) {
; CHECK-LABEL: @set_to_set_decomposebittest(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 3
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = or i8 [[TMP1]], 3
+; CHECK-NEXT: ret i8 [[T3]]
;
%t2 = icmp slt i8 %x, 0
%t3 = select i1 %t2, i8 131, i8 3
@@ -546,8 +546,8 @@ define i8 @set_to_set_decomposebittest(i8 %x) {
define i8 @set_to_clear_decomposebittest(i8 %x) {
; CHECK-LABEL: @set_to_clear_decomposebittest(
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -128
-; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], -125
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = xor i8 [[TMP1]], -125
+; CHECK-NEXT: ret i8 [[T3]]
;
%t2 = icmp slt i8 %x, 0
%t3 = select i1 %t2, i8 3, i8 131
diff --git a/llvm/test/Transforms/InstCombine/select-imm-canon.ll b/llvm/test/Transforms/InstCombine/select-imm-canon.ll
index f73a3d042f28a..f8d081644854d 100644
--- a/llvm/test/Transforms/InstCombine/select-imm-canon.ll
+++ b/llvm/test/Transforms/InstCombine/select-imm-canon.ll
@@ -4,9 +4,9 @@
define i8 @single(i32 %A) {
; CHECK-LABEL: @single(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128)
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[CONV71:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[CONV71]] to i8
+; CHECK-NEXT: ret i8 [[CONV7]]
;
entry:
%l1 = icmp slt i32 %A, -128
@@ -19,9 +19,9 @@ define i8 @double(i32 %A) {
; CHECK-LABEL: @double(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128)
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 127)
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[CONV71:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 127)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[CONV71]] to i8
+; CHECK-NEXT: ret i8 [[CONV7]]
;
entry:
%l1 = icmp slt i32 %A, -128
@@ -50,8 +50,8 @@ entry:
define i8 @original(i32 %A, i32 %B) {
; CHECK-LABEL: @original(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[TMP2]] to i8
+; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[SPEC_SELECT_I]] to i8
; CHECK-NEXT: ret i8 [[CONV7]]
;
%cmp4.i = icmp slt i32 127, %A
@@ -67,8 +67,8 @@ define i8 @original(i32 %A, i32 %B) {
define i8 @original_logical(i32 %A, i32 %B) {
; CHECK-LABEL: @original_logical(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
-; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[TMP2]] to i8
+; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
+; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[SPEC_SELECT_I]] to i8
; CHECK-NEXT: ret i8 [[CONV7]]
;
%cmp4.i = icmp slt i32 127, %A
diff --git a/llvm/test/Transforms/InstCombine/select-min-max.ll b/llvm/test/Transforms/InstCombine/select-min-max.ll
index 72344dc917b4d..f13223284e6a6 100644
--- a/llvm/test/Transforms/InstCombine/select-min-max.ll
+++ b/llvm/test/Transforms/InstCombine/select-min-max.ll
@@ -205,8 +205,8 @@ declare i8 @llvm.umin.i8(i8, i8);
define i32 @smax_smin(i32 %x) {
; CHECK-LABEL: @smax_smin(
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[S]]
;
%m = call i32 @llvm.smax.i32(i32 %x, i32 0)
%c = icmp slt i32 %x, 1
@@ -217,8 +217,8 @@ define i32 @smax_smin(i32 %x) {
define i32 @smin_smax(i32 %x) {
; CHECK-LABEL: @smin_smax(
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -2
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 -1, i32 -2
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = select i1 [[TMP1]], i32 -1, i32 -2
+; CHECK-NEXT: ret i32 [[S]]
;
%m = call i32 @llvm.smin.i32(i32 %x, i32 -1)
%c = icmp sgt i32 %x, -2
@@ -229,8 +229,8 @@ define i32 @smin_smax(i32 %x) {
define i8 @umax_umin(i8 %x) {
; CHECK-LABEL: @umax_umin(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], -127
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i8 -128, i8 -127
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = select i1 [[TMP1]], i8 -128, i8 -127
+; CHECK-NEXT: ret i8 [[S]]
;
%m = call i8 @llvm.umax.i8(i8 %x, i8 128)
%c = icmp ult i8 %x, 129
@@ -241,8 +241,8 @@ define i8 @umax_umin(i8 %x) {
define i8 @umin_umax(i8 %x) {
; CHECK-LABEL: @umin_umax(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 126
-; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i8 127, i8 126
-; CHECK-NEXT: ret i8 [[TMP2]]
+; CHECK-NEXT: [[S:%.*]] = select i1 [[TMP1]], i8 127, i8 126
+; CHECK-NEXT: ret i8 [[S]]
;
%m = call i8 @llvm.umin.i8(i8 %x, i8 127)
%c = icmp ugt i8 %x, 126
diff --git a/llvm/test/Transforms/InstCombine/select-safe-transforms.ll b/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
index e5c313c361d59..f0072e24161d4 100644
--- a/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
+++ b/llvm/test/Transforms/InstCombine/select-safe-transforms.ll
@@ -19,8 +19,8 @@ define i1 @cond_eq_and(i8 %X, i8 %Y, i8 noundef %C) {
define i1 @cond_eq_and_const(i8 %X, i8 %Y) {
; CHECK-LABEL: @cond_eq_and_const(
; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[X:%.*]], 10
-; CHECK-NEXT: [[LHS:%.*]] = icmp ugt i8 [[Y:%.*]], 10
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND]], i1 [[LHS]], i1 false
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], 10
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND]], i1 [[TMP1]], i1 false
; CHECK-NEXT: ret i1 [[RES]]
;
%cond = icmp eq i8 %X, 10
@@ -45,8 +45,8 @@ define i1 @cond_eq_or(i8 %X, i8 %Y, i8 noundef %C) {
define i1 @cond_eq_or_const(i8 %X, i8 %Y) {
; CHECK-LABEL: @cond_eq_or_const(
; CHECK-NEXT: [[COND:%.*]] = icmp ne i8 [[X:%.*]], 10
-; CHECK-NEXT: [[LHS:%.*]] = icmp ugt i8 [[Y:%.*]], 10
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND]], i1 true, i1 [[LHS]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], 10
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND]], i1 true, i1 [[TMP1]]
; CHECK-NEXT: ret i1 [[RES]]
;
%cond = icmp ne i8 %X, 10
diff --git a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
index 27b56e7851d34..04588fd7114c4 100644
--- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
+++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
@@ -10,8 +10,8 @@ define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2(
; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 1
%cmp = icmp eq i32 %and, 0
@@ -24,8 +24,8 @@ define <2 x i32> @select_icmp_eq_and_1_0_or_2_vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2_vec(
; CHECK-NEXT: [[AND:%.*]] = shl <2 x i32> [[X:%.*]], <i32 1, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 2, i32 2>
-; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 1, i32 1>
%cmp = icmp eq <2 x i32> %and, zeroinitializer
@@ -68,8 +68,8 @@ define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8(
; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 32
%cmp = icmp eq i32 %and, 0
@@ -82,8 +82,8 @@ define <2 x i32> @select_icmp_eq_and_32_0_or_8_vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8_vec(
; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 8, i32 8>
-; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 32, i32 32>
%cmp = icmp eq <2 x i32> %and, zeroinitializer
@@ -126,8 +126,8 @@ define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 4096
%cmp = icmp ne i32 0, %and
@@ -140,8 +140,8 @@ define <2 x i32> @select_icmp_ne_0_and_4096_or_4096_vec(<2 x i32> %x, <2 x i32>
; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096_vec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 4096, i32 4096>
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[AND]], <i32 4096, i32 4096>
-; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 4096, i32 4096>
%cmp = icmp ne <2 x i32> zeroinitializer, %and
@@ -183,8 +183,8 @@ define i32 @select_icmp_ne_0_and_4096_and_not_4096(i32 %x, i32 %y) {
define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 4096
%cmp = icmp eq i32 %and, 0
@@ -196,8 +196,8 @@ define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
define <2 x i32> @select_icmp_eq_and_4096_0_or_4096_vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096_vec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 4096, i32 4096>
-; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[AND]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[AND]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 4096, i32 4096>
%cmp = icmp eq <2 x i32> %and, zeroinitializer
@@ -240,8 +240,8 @@ define i32 @select_icmp_eq_0_and_1_or_1(i64 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i64 %x, 1
%cmp = icmp eq i64 %and, 0
@@ -254,8 +254,8 @@ define <2 x i32> @select_icmp_eq_0_and_1_or_1_vec(<2 x i64> %x, <2 x i32> %y) {
; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1_vec(
; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[X:%.*]] to <2 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i64> %x, <i64 1, i64 1>
%cmp = icmp eq <2 x i64> %and, zeroinitializer
@@ -267,8 +267,8 @@ define <2 x i32> @select_icmp_eq_0_and_1_or_1_vec(<2 x i64> %x, <2 x i32> %y) {
define i32 @select_icmp_eq_0_and_1_xor_1(i64 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_0_and_1_xor_1(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
-; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], 1
+; CHECK-NEXT: [[SELECT:%.*]] = xor i32 [[XOR]], [[Y:%.*]]
; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i64 %x, 1
@@ -298,8 +298,8 @@ define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {
; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 7
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 32
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 32
-; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 4096
%cmp = icmp ne i32 0, %and
@@ -343,8 +343,8 @@ define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) {
; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 7
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 4096
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 4096
-; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 32
%cmp = icmp ne i32 0, %and
@@ -358,8 +358,8 @@ define <2 x i32> @select_icmp_ne_0_and_32_or_4096_vec(<2 x i32> %x, <2 x i32> %y
; CHECK-NEXT: [[AND:%.*]] = shl <2 x i32> [[X:%.*]], <i32 7, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 4096, i32 4096>
; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], <i32 4096, i32 4096>
-; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 32, i32 32>
%cmp = icmp ne <2 x i32> zeroinitializer, %and
@@ -507,8 +507,8 @@ define <2 x i32> @select_icmp_eq_and_1_0_or_vector_of_2s(i32 %x, <2 x i32> %y) {
define i32 @select_icmp_and_8_ne_0_xor_8(i32 %x) {
; CHECK-LABEL: @select_icmp_and_8_ne_0_xor_8(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -9
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[X_XOR:%.*]] = and i32 [[X:%.*]], -9
+; CHECK-NEXT: ret i32 [[X_XOR]]
;
%and = and i32 %x, 8
%cmp = icmp eq i32 %and, 0
@@ -519,8 +519,8 @@ define i32 @select_icmp_and_8_ne_0_xor_8(i32 %x) {
define i32 @select_icmp_and_8_eq_0_xor_8(i32 %x) {
; CHECK-LABEL: @select_icmp_and_8_eq_0_xor_8(
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], 8
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[XOR_X:%.*]] = or i32 [[X:%.*]], 8
+; CHECK-NEXT: ret i32 [[XOR_X]]
;
%and = and i32 %x, 8
%cmp = icmp eq i32 %and, 0
@@ -564,8 +564,8 @@ define i64 @select_icmp_x_and_8_ne_0_y_or_8(i32 %x, i64 %y) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 8
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret i64 [[TMP3]]
+; CHECK-NEXT: [[OR_Y:%.*]] = or i64 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i64 [[OR_Y]]
;
%and = and i32 %x, 8
%cmp = icmp eq i32 %and, 0
@@ -579,8 +579,8 @@ define <2 x i64> @select_icmp_x_and_8_ne_0_y_or_8_vec(<2 x i32> %x, <2 x i64> %y
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 8, i32 8>
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[AND]], <i32 8, i32 8>
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i64> [[TMP3]]
+; CHECK-NEXT: [[OR_Y:%.*]] = or <2 x i64> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i64> [[OR_Y]]
;
%and = and <2 x i32> %x, <i32 8, i32 8>
%cmp = icmp eq <2 x i32> %and, zeroinitializer
@@ -606,8 +606,8 @@ define i64 @select_icmp_x_and_8_ne_0_y_and_not_8(i32 %x, i64 %y) {
define i32 @select_icmp_and_2147483648_ne_0_xor_2147483648(i32 %x) {
; CHECK-LABEL: @select_icmp_and_2147483648_ne_0_xor_2147483648(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[X_XOR:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT: ret i32 [[X_XOR]]
;
%and = and i32 %x, 2147483648
%cmp = icmp eq i32 %and, 0
@@ -618,8 +618,8 @@ define i32 @select_icmp_and_2147483648_ne_0_xor_2147483648(i32 %x) {
define i32 @select_icmp_and_2147483648_eq_0_xor_2147483648(i32 %x) {
; CHECK-LABEL: @select_icmp_and_2147483648_eq_0_xor_2147483648(
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[XOR_X:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT: ret i32 [[XOR_X]]
;
%and = and i32 %x, 2147483648
%cmp = icmp eq i32 %and, 0
@@ -644,8 +644,8 @@ define i32 @test68(i32 %x, i32 %y) {
; CHECK-LABEL: @test68(
; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 6
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 128
%cmp = icmp eq i32 %and, 0
@@ -658,8 +658,8 @@ define <2 x i32> @test68vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @test68vec(
; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 2, i32 2>
-; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 128, i32 128>
%cmp = icmp eq <2 x i32> %and, zeroinitializer
@@ -703,8 +703,8 @@ define i32 @test69(i32 %x, i32 %y) {
; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 6
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[SELECT]]
;
%and = and i32 %x, 128
%cmp = icmp ne i32 %and, 0
@@ -718,8 +718,8 @@ define <2 x i32> @test69vec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: [[AND:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 6, i32 6>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[AND]], <i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], <i32 2, i32 2>
-; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+; CHECK-NEXT: [[SELECT:%.*]] = or <2 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: ret <2 x i32> [[SELECT]]
;
%and = and <2 x i32> %x, <i32 128, i32 128>
%cmp = icmp ne <2 x i32> %and, zeroinitializer
@@ -776,8 +776,8 @@ define i32 @shift_no_xor_multiuse_or(i32 %x, i32 %y) {
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 1
@@ -826,8 +826,8 @@ define i32 @no_shift_no_xor_multiuse_or(i32 %x, i32 %y) {
; CHECK-LABEL: @no_shift_no_xor_multiuse_or(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[OR]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 4096
@@ -877,8 +877,8 @@ define i32 @no_shift_xor_multiuse_or(i32 %x, i32 %y) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 4096
@@ -979,9 +979,9 @@ define i32 @shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 1
@@ -1035,9 +1035,9 @@ define i32 @no_shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y:%.*]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 4096
@@ -1092,9 +1092,9 @@ define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
-; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32 [[W:%.*]], i32 [[Z:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: ret i32 [[RES]]
;
%and = and i32 %x, 4096
@@ -1269,9 +1269,9 @@ define i32 @no_shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]]
+; CHECK-NEXT: [[SELECT:%.*]] = or i32 [[AND]], [[Y]]
; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
; CHECK-NEXT: ret i32 [[RES2]]
;
diff --git a/llvm/test/Transforms/InstCombine/select_meta.ll b/llvm/test/Transforms/InstCombine/select_meta.ll
index 2b6dc9d059a1c..025548115accf 100644
--- a/llvm/test/Transforms/InstCombine/select_meta.ll
+++ b/llvm/test/Transforms/InstCombine/select_meta.ll
@@ -65,8 +65,8 @@ define i32 @foo2(i32, i32) local_unnamed_addr #0 {
define i64 @test43(i32 %a) nounwind {
; CHECK-LABEL: @test43(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[MAX:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[MAX]]
;
%a_ext = sext i32 %a to i64
%is_a_nonnegative = icmp sgt i32 %a, -1
@@ -131,8 +131,8 @@ define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
; SMAX(SMAX(x, y), x) -> SMAX(x, y)
define i32 @test30(i32 %x, i32 %y) {
; CHECK-LABEL: @test30(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp sgt i32 %x, %y
%cond = select i1 %cmp, i32 %x, i32 %y, !prof !1
@@ -144,8 +144,8 @@ define i32 @test30(i32 %x, i32 %y) {
; SMAX(SMAX(75, X), 36) -> SMAX(X, 75)
define i32 @test70(i32 %x) {
; CHECK-LABEL: @test70(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 75)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 75)
+; CHECK-NEXT: ret i32 [[COND]]
;
%cmp = icmp slt i32 %x, 75
%cond = select i1 %cmp, i32 75, i32 %x, !prof !1
@@ -158,8 +158,8 @@ define i32 @test70(i32 %x) {
; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
define i32 @test72(i32 %x) {
; CHECK-LABEL: @test72(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 11)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[RETVAL:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 11)
+; CHECK-NEXT: ret i32 [[RETVAL]]
;
%cmp = icmp sgt i32 %x, 92
%cond = select i1 %cmp, i32 92, i32 %x, !prof !1
@@ -172,9 +172,9 @@ define i32 @test72(i32 %x) {
; SMAX(SMAX(X, 36), 75) -> SMAX(X, 75)
define i32 @test74(i32 %x) {
; CHECK-LABEL: @test74(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 36)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP1]], i32 75)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 36)
+; CHECK-NEXT: [[RETVAL:%.*]] = call i32 @llvm.umax.i32(i32 [[COND]], i32 75)
+; CHECK-NEXT: ret i32 [[RETVAL]]
;
%cmp = icmp slt i32 %x, 36
%cond = select i1 %cmp, i32 36, i32 %x, !prof !1
@@ -187,8 +187,8 @@ define i32 @test74(i32 %x) {
define i32 @smin1(i32 %x) {
; CHECK-LABEL: @smin1(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
;
%not_x = xor i32 %x, -1
%cmp = icmp sgt i32 %x, 0
@@ -200,8 +200,8 @@ define i32 @smin1(i32 %x) {
define i32 @smin2(i32 %x) {
; CHECK-LABEL: @smin2(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
;
%not_x = xor i32 %x, -1
%cmp = icmp slt i32 %x, 0
@@ -213,8 +213,8 @@ define i32 @smin2(i32 %x) {
define i32 @smax1(i32 %x) {
; CHECK-LABEL: @smax1(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
;
%not_x = xor i32 %x, -1
%cmp = icmp slt i32 %x, 0
@@ -226,8 +226,8 @@ define i32 @smax1(i32 %x) {
define i32 @smax2(i32 %x) {
; CHECK-LABEL: @smax2(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 0)
-; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT: ret i32 [[SEL]]
;
%not_x = xor i32 %x, -1
%cmp = icmp sgt i32 %x, 0
@@ -238,8 +238,8 @@ define i32 @smax2(i32 %x) {
; The compare should change, but the metadata remains the same because the select operands are not swapped.
define i32 @umin1(i32 %x) {
; CHECK-LABEL: @umin1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 -2147483648)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 -2147483648)
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp sgt i32 %x, -1
%sel = select i1 %cmp, i32 %x, i32 -2147483648, !prof !1
@@ -249,8 +249,8 @@ define i32 @umin1(i32 %x) {
; The compare should change, and the metadata is swapped because the select operands are swapped.
define i32 @umin2(i32 %x) {
; CHECK-LABEL: @umin2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 2147483647)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 2147483647)
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp slt i32 %x, 0
%sel = select i1 %cmp, i32 2147483647, i32 %x, !prof !1
@@ -260,8 +260,8 @@ define i32 @umin2(i32 %x) {
; The compare should change, but the metadata remains the same because the select operands are not swapped.
define i32 @umax1(i32 %x) {
; CHECK-LABEL: @umax1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 2147483647)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 2147483647)
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp slt i32 %x, 0
%sel = select i1 %cmp, i32 %x, i32 2147483647, !prof !1
@@ -271,8 +271,8 @@ define i32 @umax1(i32 %x) {
; The compare should change, and the metadata is swapped because the select operands are swapped.
define i32 @umax2(i32 %x) {
; CHECK-LABEL: @umax2(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 -2147483648)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.umax.i32(i32 [[X:%.*]], i32 -2147483648)
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp sgt i32 %x, -1
%sel = select i1 %cmp, i32 -2147483648, i32 %x, !prof !1
diff --git a/llvm/test/Transforms/InstCombine/set.ll b/llvm/test/Transforms/InstCombine/set.ll
index 40f158c6054fc..50329ddf7caac 100644
--- a/llvm/test/Transforms/InstCombine/set.ll
+++ b/llvm/test/Transforms/InstCombine/set.ll
@@ -174,8 +174,8 @@ define <3 x i1> @test14vec(<3 x i1> %A, <3 x i1> %B) {
define i1 @bool_eq0(i64 %a) {
; CHECK-LABEL: @bool_eq0(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[AND:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[AND]]
;
%b = icmp sgt i64 %a, 0
%c = icmp eq i64 %a, 1
@@ -186,8 +186,8 @@ define i1 @bool_eq0(i64 %a) {
define i1 @bool_eq0_logical(i64 %a) {
; CHECK-LABEL: @bool_eq0_logical(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[AND:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[AND]]
;
%b = icmp sgt i64 %a, 0
%c = icmp eq i64 %a, 1
@@ -200,8 +200,8 @@ define i1 @bool_eq0_logical(i64 %a) {
define i1 @xor_of_icmps(i64 %a) {
; CHECK-LABEL: @xor_of_icmps(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[XOR]]
;
%b = icmp sgt i64 %a, 0
%c = icmp eq i64 %a, 1
@@ -213,8 +213,8 @@ define i1 @xor_of_icmps(i64 %a) {
define i1 @xor_of_icmps_commute(i64 %a) {
; CHECK-LABEL: @xor_of_icmps_commute(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[A:%.*]], 1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp sgt i64 [[A:%.*]], 1
+; CHECK-NEXT: ret i1 [[XOR]]
;
%b = icmp sgt i64 %a, 0
%c = icmp eq i64 %a, 1
@@ -224,8 +224,8 @@ define i1 @xor_of_icmps_commute(i64 %a) {
define i1 @xor_of_icmps_to_ne(i64 %a) {
; CHECK-LABEL: @xor_of_icmps_to_ne(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A:%.*]], 5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp ne i64 [[A:%.*]], 5
+; CHECK-NEXT: ret i1 [[XOR]]
;
%b = icmp sgt i64 %a, 4
%c = icmp slt i64 %a, 6
@@ -235,8 +235,8 @@ define i1 @xor_of_icmps_to_ne(i64 %a) {
define i1 @xor_of_icmps_to_ne_commute(i64 %a) {
; CHECK-LABEL: @xor_of_icmps_to_ne_commute(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A:%.*]], 5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp ne i64 [[A:%.*]], 5
+; CHECK-NEXT: ret i1 [[XOR]]
;
%c = icmp sgt i64 %a, 4
%b = icmp slt i64 %a, 6
@@ -246,8 +246,8 @@ define i1 @xor_of_icmps_to_ne_commute(i64 %a) {
define i1 @xor_of_icmps_neg_to_ne(i64 %a) {
; CHECK-LABEL: @xor_of_icmps_neg_to_ne(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A:%.*]], -5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp ne i64 [[A:%.*]], -5
+; CHECK-NEXT: ret i1 [[XOR]]
;
%b = icmp sgt i64 %a, -6
%c = icmp slt i64 %a, -4
@@ -257,8 +257,8 @@ define i1 @xor_of_icmps_neg_to_ne(i64 %a) {
define <2 x i1> @xor_of_icmps_to_ne_vector(<2 x i64> %a) {
; CHECK-LABEL: @xor_of_icmps_to_ne_vector(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> [[A:%.*]], <i64 5, i64 5>
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp ne <2 x i64> [[A:%.*]], <i64 5, i64 5>
+; CHECK-NEXT: ret <2 x i1> [[XOR]]
;
%b = icmp sgt <2 x i64> %a, <i64 4, i64 4>
%c = icmp slt <2 x i64> %a, <i64 6, i64 6>
@@ -283,8 +283,8 @@ define i1 @xor_of_icmps_to_ne_extra_use_one(i64 %a) {
; CHECK-LABEL: @xor_of_icmps_to_ne_extra_use_one(
; CHECK-NEXT: [[B:%.*]] = icmp sgt i64 [[A:%.*]], 4
; CHECK-NEXT: call void @use(i1 [[B]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 5
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[XOR:%.*]] = icmp ne i64 [[A]], 5
+; CHECK-NEXT: ret i1 [[XOR]]
;
%b = icmp sgt i64 %a, 4
%c = icmp slt i64 %a, 6
@@ -327,8 +327,8 @@ define i32 @PR2844(i32 %x) {
; CHECK-LABEL: @PR2844(
; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -638208502
-; CHECK-NEXT: [[NOT_OR:%.*]] = and i1 [[A]], [[B]]
-; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[NOT_OR]] to i32
+; CHECK-NEXT: [[OR_NOT:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[OR_NOT]] to i32
; CHECK-NEXT: ret i32 [[SEL]]
;
%A = icmp eq i32 %x, 0
@@ -342,8 +342,8 @@ define i32 @PR2844_logical(i32 %x) {
; CHECK-LABEL: @PR2844_logical(
; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], 0
; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -638208502
-; CHECK-NEXT: [[NOT_OR:%.*]] = and i1 [[A]], [[B]]
-; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[NOT_OR]] to i32
+; CHECK-NEXT: [[OR_NOT:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT: [[SEL:%.*]] = zext i1 [[OR_NOT]] to i32
; CHECK-NEXT: ret i32 [[SEL]]
;
%A = icmp eq i32 %x, 0
@@ -479,8 +479,8 @@ define i1 @test22_logical(i32 %A, i32 %X) {
define i32 @test23(i32 %a) {
; CHECK-LABEL: @test23(
; CHECK-NEXT: [[TMP_1:%.*]] = and i32 [[A:%.*]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[TMP_1]], 1
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[TMP_3:%.*]] = xor i32 [[TMP_1]], 1
+; CHECK-NEXT: ret i32 [[TMP_3]]
;
%tmp.1 = and i32 %a, 1
%tmp.2 = icmp eq i32 %tmp.1, 0
@@ -491,8 +491,8 @@ define i32 @test23(i32 %a) {
define <2 x i32> @test23vec(<2 x i32> %a) {
; CHECK-LABEL: @test23vec(
; CHECK-NEXT: [[TMP_1:%.*]] = and <2 x i32> [[A:%.*]], <i32 1, i32 1>
-; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[TMP_1]], <i32 1, i32 1>
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[TMP_3:%.*]] = xor <2 x i32> [[TMP_1]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[TMP_3]]
;
%tmp.1 = and <2 x i32> %a, <i32 1, i32 1>
%tmp.2 = icmp eq <2 x i32> %tmp.1, zeroinitializer
@@ -504,8 +504,8 @@ define i32 @test24(i32 %a) {
; CHECK-LABEL: @test24(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A:%.*]], 2
; CHECK-NEXT: [[DOTLOBIT:%.*]] = and i32 [[TMP1]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[DOTLOBIT]], 1
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[TMP_3:%.*]] = xor i32 [[DOTLOBIT]], 1
+; CHECK-NEXT: ret i32 [[TMP_3]]
;
%tmp1 = and i32 %a, 4
%tmp.1 = lshr i32 %tmp1, 2
@@ -518,8 +518,8 @@ define <2 x i32> @test24vec(<2 x i32> %a) {
; CHECK-LABEL: @test24vec(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 2, i32 2>
; CHECK-NEXT: [[DOTLOBIT:%.*]] = and <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[DOTLOBIT]], <i32 1, i32 1>
-; CHECK-NEXT: ret <2 x i32> [[TMP2]]
+; CHECK-NEXT: [[TMP_3:%.*]] = xor <2 x i32> [[DOTLOBIT]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[TMP_3]]
;
%tmp1 = and <2 x i32> %a, <i32 4, i32 4>
%tmp.1 = lshr <2 x i32> %tmp1, <i32 2, i32 2>
diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll
index 6dbb93e3c6b7a..c204b37ff85a5 100644
--- a/llvm/test/Transforms/InstCombine/sext.ll
+++ b/llvm/test/Transforms/InstCombine/sext.ll
@@ -295,8 +295,8 @@ define i32 @test17(i1 %x) {
define i32 @test18(i16 %x) {
; CHECK-LABEL: @test18(
-; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0)
-; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[TMP1]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 0)
+; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[SEL]] to i32
; CHECK-NEXT: ret i32 [[EXT]]
;
%cmp = icmp slt i16 %x, 0
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
index 28cf9737c6401..d48e4ab0d2342 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll
@@ -43,8 +43,8 @@ define i1 @n0(i32 %x, i64 %y, i32 %len) {
define i1 @t1(i64 %y, i32 %len) {
; CHECK-LABEL: @t1(
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 4294901760
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = shl i32 65535, %t0
@@ -60,8 +60,8 @@ define i1 @t1(i64 %y, i32 %len) {
define i1 @t1_single_bit(i64 %y, i32 %len) {
; CHECK-LABEL: @t1_single_bit(
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 2147483648
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = shl i32 32768, %t0
@@ -101,8 +101,8 @@ define i1 @n2(i64 %y, i32 %len) {
define i1 @t3(i32 %x, i32 %len) {
; CHECK-LABEL: @t3(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = shl i32 %x, %t0
@@ -118,8 +118,8 @@ define i1 @t3(i32 %x, i32 %len) {
define i1 @t3_singlebit(i32 %x, i32 %len) {
; CHECK-LABEL: @t3_singlebit(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = shl i32 %x, %t0
@@ -167,8 +167,8 @@ define <2 x i1> @t5_vec(<2 x i64> %y, <2 x i32> %len) {
; CHECK-LABEL: @t5_vec(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[Y:%.*]], <i64 16, i64 16>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[TMP1]], <i64 65535, i64 32767>
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 32, i32 32>, %len
%t1 = shl <2 x i32> <i32 65535, i32 32767>, %t0
@@ -208,8 +208,8 @@ define <2 x i1> @n6_vec(<2 x i64> %y, <2 x i32> %len) {
define <2 x i1> @t7_vec(<2 x i32> %x, <2 x i32> %len) {
; CHECK-LABEL: @t7_vec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 1, i32 0>
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 32, i32 32>, %len
%t1 = shl <2 x i32> %x, %t0
@@ -253,8 +253,8 @@ define i1 @t9_highest_bit(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[Y:%.*]], 63
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[TMP1]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 64, %len
%t1 = shl i32 %x, %t0
@@ -295,8 +295,8 @@ define i1 @t11_no_shift(i32 %x, i64 %y, i32 %len) {
; CHECK-LABEL: @t11_no_shift(
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 64, %len
%t1 = shl i32 %x, %t0
@@ -384,8 +384,8 @@ define <2 x i1> @n12_bad(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {
define i1 @t13_x_is_one(i64 %y, i32 %len) {
; CHECK-LABEL: @t13_x_is_one(
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 65536
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = shl i32 1, %t0
@@ -416,8 +416,8 @@ define <2 x i1> @t15_vec_x_is_one_or_zero(<2 x i64> %y, <2 x i32> %len) {
; CHECK-LABEL: @t15_vec_x_is_one_or_zero(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[Y:%.*]], <i64 48, i64 48>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[TMP1]], <i64 1, i64 0>
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 64, i32 64>, %len
%t1 = shl <2 x i32> <i32 1, i32 0>, %t0
@@ -453,8 +453,8 @@ define <2 x i1> @t16_vec_y_is_one_or_zero(<2 x i32> %x, <2 x i32> %len) {
; And that's the main motivational pattern:
define i1 @rawspeed_signbit(i64 %storage, i32 %nbits) {
; CHECK-LABEL: @rawspeed_signbit(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[STORAGE:%.*]], -1
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[ISBITUNSET:%.*]] = icmp sgt i64 [[STORAGE:%.*]], -1
+; CHECK-NEXT: ret i1 [[ISBITUNSET]]
;
%skipnbits = sub nsw i32 64, %nbits
%skipnbitswide = zext i32 %skipnbits to i64
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
index b33bda4c10ba2..8d36b1f3cb221 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll
@@ -18,8 +18,8 @@ define i1 @t0_const_after_fold_lshr_shl_ne(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = lshr i32 %x, %t0
@@ -41,8 +41,8 @@ define <2 x i1> @t1_vec_splat(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 31, i32 31>
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP4]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 32, i32 32>, %len
%t1 = lshr <2 x i32> %x, %t0
@@ -60,8 +60,8 @@ define <2 x i1> @t2_vec_nonsplat(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {
; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], <i64 31, i64 30>
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP4]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T5]]
;
%t0 = sub <2 x i32> <i32 30, i32 32>, %len
%t1 = lshr <2 x i32> %x, %t0
@@ -213,8 +213,8 @@ define i1 @t6_oneuse3(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
call void @use32(i32 %t0)
@@ -245,8 +245,8 @@ define i1 @t7_oneuse4(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
-; CHECK-NEXT: ret i1 [[TMP4]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP3]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len ; no extra uses
%t1 = lshr i32 %x, %t0 ; no extra uses
@@ -279,8 +279,8 @@ define i1 @t8_oneuse5(i32 %x, i64 %y, i32 %len) {
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: call void @use32(i32 [[T3_TRUNC]])
; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
call void @use32(i32 %t0)
@@ -349,8 +349,8 @@ define i1 @t10_constants(i32 %x, i64 %y) {
; CHECK-NEXT: [[Y_TR:%.*]] = trunc i64 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 26
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y_TR]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = lshr i32 %x, 12
%t1 = shl i64 %y, 14
@@ -365,8 +365,8 @@ define <2 x i1> @t11_constants_vec_splat(<2 x i32> %x, <2 x i64> %y) {
; CHECK-NEXT: [[Y_TR:%.*]] = trunc <2 x i64> [[Y:%.*]] to <2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 26, i32 26>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[Y_TR]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T3]]
;
%t0 = lshr <2 x i32> %x, <i32 12, i32 12>
%t1 = shl <2 x i64> %y, <i64 14, i64 14>
@@ -380,8 +380,8 @@ define <2 x i1> @t12_constants_vec_nonsplat(<2 x i32> %x, <2 x i64> %y) {
; CHECK-NEXT: [[Y_TR:%.*]] = trunc <2 x i64> [[Y:%.*]] to <2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 28, i32 28>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[Y_TR]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T3]]
;
%t0 = lshr <2 x i32> %x, <i32 12, i32 14>
%t1 = shl <2 x i64> %y, <i64 16, i64 14>
diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
index 2bb741052e53e..a539ee320674e 100644
--- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
+++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
@@ -13,8 +13,8 @@ define i1 @t0_const_lshr_shl_ne(i32 %x, i32 %y) {
; CHECK-LABEL: @t0_const_lshr_shl_ne(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = lshr i32 %x, 1
%t1 = shl i32 %y, 1
@@ -26,8 +26,8 @@ define i1 @t1_const_shl_lshr_ne(i32 %x, i32 %y) {
; CHECK-LABEL: @t1_const_shl_lshr_ne(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = shl i32 %x, 1
%t1 = lshr i32 %y, 1
@@ -41,8 +41,8 @@ define i1 @t2_const_lshr_shl_eq(i32 %x, i32 %y) {
; CHECK-LABEL: @t2_const_lshr_shl_eq(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = lshr i32 %x, 1
%t1 = shl i32 %y, 1
@@ -57,8 +57,8 @@ define i1 @t3_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
; CHECK-LABEL: @t3_const_after_fold_lshr_shl_ne(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = lshr i32 %x, %t0
@@ -72,8 +72,8 @@ define i1 @t4_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
; CHECK-LABEL: @t4_const_after_fold_lshr_shl_ne(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
%t1 = shl i32 %x, %t0
@@ -121,8 +121,8 @@ define <2 x i1> @t7_const_lshr_shl_ne_vec_splat(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @t7_const_lshr_shl_ne_vec_splat(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T3]]
;
%t0 = lshr <2 x i32> %x, <i32 1, i32 1>
%t1 = shl <2 x i32> %y, <i32 1, i32 1>
@@ -134,8 +134,8 @@ define <2 x i1> @t8_const_lshr_shl_ne_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @t8_const_lshr_shl_ne_vec_nonsplat(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 4, i32 6>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[T3]]
;
%t0 = lshr <2 x i32> %x, <i32 1, i32 2>
%t1 = shl <2 x i32> %y, <i32 3, i32 4>
@@ -147,8 +147,8 @@ define <3 x i1> @t9_const_lshr_shl_ne_vec_undef0(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t9_const_lshr_shl_ne_vec_undef0(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 undef, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
@@ -160,8 +160,8 @@ define <3 x i1> @t10_const_lshr_shl_ne_vec_undef1(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t10_const_lshr_shl_ne_vec_undef1(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 undef, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
@@ -173,8 +173,8 @@ define <3 x i1> @t11_const_lshr_shl_ne_vec_undef2(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t11_const_lshr_shl_ne_vec_undef2(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
@@ -186,8 +186,8 @@ define <3 x i1> @t12_const_lshr_shl_ne_vec_undef3(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t12_const_lshr_shl_ne_vec_undef3(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 undef, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
@@ -199,8 +199,8 @@ define <3 x i1> @t13_const_lshr_shl_ne_vec_undef4(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t13_const_lshr_shl_ne_vec_undef4(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 undef, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
@@ -212,8 +212,8 @@ define <3 x i1> @t14_const_lshr_shl_ne_vec_undef5(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t14_const_lshr_shl_ne_vec_undef5(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 undef, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
@@ -225,8 +225,8 @@ define <3 x i1> @t15_const_lshr_shl_ne_vec_undef6(<3 x i32> %x, <3 x i32> %y) {
; CHECK-LABEL: @t15_const_lshr_shl_ne_vec_undef6(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 2, i32 undef, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[T3]]
;
%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
@@ -244,8 +244,8 @@ define i1 @t16_commutativity0(i32 %x) {
; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32()
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%y = call i32 @gen32()
%t0 = lshr i32 %x, 1
@@ -260,8 +260,8 @@ define i1 @t17_commutativity1(i32 %y) {
; CHECK-NEXT: [[X:%.*]] = call i32 @gen32()
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%x = call i32 @gen32()
%t0 = lshr i32 %x, 1
@@ -281,8 +281,8 @@ define i1 @t18_const_oneuse0(i32 %x, i32 %y) {
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = lshr i32 %x, 1
call void @use32(i32 %t0)
@@ -297,8 +297,8 @@ define i1 @t19_const_oneuse1(i32 %x, i32 %y) {
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%t0 = lshr i32 %x, 1
%t1 = shl i32 %y, 1
@@ -535,8 +535,8 @@ define i1 @t32_shift_of_const_oneuse0(i32 %x, i32 %y, i32 %len) {
; CHECK-NEXT: [[T3:%.*]] = shl i32 [[Y:%.*]], [[T2]]
; CHECK-NEXT: call void @use32(i32 [[T3]])
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[T5]]
;
%t0 = sub i32 32, %len
call void @use32(i32 %t0)
@@ -585,8 +585,8 @@ define i1 @t34_commutativity0_oneuse0(i32 %x) {
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%y = call i32 @gen32()
%t0 = lshr i32 %x, 1
@@ -603,8 +603,8 @@ define i1 @t35_commutativity0_oneuse1(i32 %x) {
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%y = call i32 @gen32()
%t0 = lshr i32 %x, 1
@@ -622,8 +622,8 @@ define i1 @t36_commutativity1_oneuse0(i32 %y) {
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%x = call i32 @gen32()
%t0 = lshr i32 %x, 1
@@ -640,8 +640,8 @@ define i1 @t37_commutativity1_oneuse1(i32 %y) {
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 2
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT: ret i1 [[TMP3]]
+; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT: ret i1 [[T3]]
;
%x = call i32 @gen32()
%t0 = lshr i32 %x, 1
diff --git a/llvm/test/Transforms/InstCombine/shift-sra.ll b/llvm/test/Transforms/InstCombine/shift-sra.ll
index 34afdddedb189..2e32689e47108 100644
--- a/llvm/test/Transforms/InstCombine/shift-sra.ll
+++ b/llvm/test/Transforms/InstCombine/shift-sra.ll
@@ -20,8 +20,8 @@ define i32 @test2(i8 %a) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[B:%.*]] = zext i8 [[A:%.*]] to i32
; CHECK-NEXT: [[C:%.*]] = add nuw nsw i32 [[B]], 7
-; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[C]], 3
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = lshr i32 [[C]], 3
+; CHECK-NEXT: ret i32 [[D]]
;
%b = zext i8 %a to i32
%c = add i32 %b, 7
diff --git a/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
index a4549a7c0a32e..42b755f51a971 100644
--- a/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
@@ -195,8 +195,8 @@ define i1 @scalar_i32_shl_and_signbit_eq_X_is_constant1(i32 %y) {
define i1 @scalar_i32_shl_and_signbit_eq_X_is_constant2(i32 %y) {
; CHECK-LABEL: @scalar_i32_shl_and_signbit_eq_X_is_constant2(
-; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[Y:%.*]], 31
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 31
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%shl = shl i32 1, %y
%and = and i32 %shl, 2147483648
diff --git a/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
index 6a67aa885353a..e6420e35a2cf0 100644
--- a/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
@@ -405,8 +405,8 @@ define <4 x double> @frem(<4 x double> %v) {
define <4 x i32> @add_add(<4 x i32> %v0) {
; CHECK-LABEL: @add_add(
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -416,8 +416,8 @@ define <4 x i32> @add_add(<4 x i32> %v0) {
define <4 x i32> @add_add_nsw(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_nsw(
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add nsw <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -427,8 +427,8 @@ define <4 x i32> @add_add_nsw(<4 x i32> %v0) {
define <4 x i32> @add_add_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -440,8 +440,8 @@ define <4 x i32> @add_add_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_nsw_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -453,8 +453,8 @@ define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @sub_sub(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub(
-; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -464,8 +464,8 @@ define <4 x i32> @sub_sub(<4 x i32> %v0) {
define <4 x i32> @sub_sub_nuw(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_nuw(
-; CHECK-NEXT: [[TMP1:%.*]] = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -475,8 +475,8 @@ define <4 x i32> @sub_sub_nuw(<4 x i32> %v0) {
define <4 x i32> @sub_sub_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -488,8 +488,8 @@ define <4 x i32> @sub_sub_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_nuw_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -502,8 +502,8 @@ define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @mul_mul(<4 x i32> %v0) {
; CHECK-LABEL: @mul_mul(
-; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -515,8 +515,8 @@ define <4 x i32> @mul_mul(<4 x i32> %v0) {
define <4 x i32> @shl_shl(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -526,8 +526,8 @@ define <4 x i32> @shl_shl(<4 x i32> %v0) {
define <4 x i32> @shl_shl_nuw(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_nuw(
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -539,8 +539,8 @@ define <4 x i32> @shl_shl_nuw(<4 x i32> %v0) {
define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -552,8 +552,8 @@ define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_nuw_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -565,8 +565,8 @@ define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @lshr_lshr(<4 x i32> %v0) {
; CHECK-LABEL: @lshr_lshr(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -578,8 +578,8 @@ define <4 x i32> @lshr_lshr(<4 x i32> %v0) {
define <3 x i32> @ashr_ashr(<3 x i32> %v0) {
; CHECK-LABEL: @ashr_ashr(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 4, i32 2, i32 3>
-; CHECK-NEXT: ret <3 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 4, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
%t2 = ashr <3 x i32> %v0, <i32 4, i32 5, i32 6>
@@ -589,8 +589,8 @@ define <3 x i32> @ashr_ashr(<3 x i32> %v0) {
define <3 x i42> @and_and(<3 x i42> %v0) {
; CHECK-LABEL: @and_and(
-; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 5, i42 undef>
-; CHECK-NEXT: ret <3 x i42> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 5, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[T3]]
;
%t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
%t2 = and <3 x i42> %v0, <i42 4, i42 5, i42 6>
@@ -603,9 +603,9 @@ define <3 x i42> @and_and(<3 x i42> %v0) {
define <4 x i32> @or_or(<4 x i32> %v0) {
; CHECK-LABEL: @or_or(
; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
-; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = or <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -617,9 +617,9 @@ define <4 x i32> @or_or(<4 x i32> %v0) {
define <4 x i32> @xor_xor(<4 x i32> %v0) {
; CHECK-LABEL: @xor_xor(
; CHECK-NEXT: [[T2:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 7, i32 8>
-; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i32> [[V0]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: [[T3:%.*]] = xor <4 x i32> [[V0]], <i32 1, i32 6, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = xor <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = xor <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -632,10 +632,10 @@ define <4 x i32> @udiv_udiv(<4 x i32> %v0) {
; CHECK-LABEL: @udiv_udiv(
; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
-; CHECK-NEXT: [[TMP1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0]]
+; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0]]
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -649,8 +649,8 @@ define <4 x i32> @udiv_udiv(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -660,8 +660,8 @@ define <4 x i32> @sdiv_sdiv(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv_exact(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_exact(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -671,8 +671,8 @@ define <4 x i32> @sdiv_sdiv_exact(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -682,8 +682,8 @@ define <4 x i32> @sdiv_sdiv_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_exact_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -693,8 +693,8 @@ define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @urem_urem(<4 x i32> %v0) {
; CHECK-LABEL: @urem_urem(
-; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -706,8 +706,8 @@ define <4 x i32> @urem_urem(<4 x i32> %v0) {
define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @urem_urem_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 0>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 0>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -717,8 +717,8 @@ define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @srem_srem(<4 x i32> %v0) {
; CHECK-LABEL: @srem_srem(
-; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -730,8 +730,8 @@ define <4 x i32> @srem_srem(<4 x i32> %v0) {
define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @srem_srem_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> <i32 1, i32 0, i32 7, i32 4>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 0, i32 7, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -743,8 +743,8 @@ define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) {
define <4 x float> @fadd_fadd(<4 x float> %v0) {
; CHECK-LABEL: @fadd_fadd(
-; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fadd <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -754,8 +754,8 @@ define <4 x float> @fadd_fadd(<4 x float> %v0) {
define <4 x double> @fsub_fsub(<4 x double> %v0) {
; CHECK-LABEL: @fsub_fsub(
-; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
@@ -767,8 +767,8 @@ define <4 x double> @fsub_fsub(<4 x double> %v0) {
define <4 x float> @fmul_fmul(<4 x float> %v0) {
; CHECK-LABEL: @fmul_fmul(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fmul nnan ninf <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fmul nnan ninf <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -778,8 +778,8 @@ define <4 x float> @fmul_fmul(<4 x float> %v0) {
define <4 x double> @fdiv_fdiv(<4 x double> %v0) {
; CHECK-LABEL: @fdiv_fdiv(
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv arcp <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fdiv arcp <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = fdiv fast <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = fdiv nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
@@ -805,8 +805,8 @@ define <4 x double> @frem_frem(<4 x double> %v0) {
define <4 x i32> @add_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @add_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -819,8 +819,8 @@ define <4 x i32> @add_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -831,8 +831,8 @@ define <4 x i32> @sub_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_nsw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -843,8 +843,8 @@ define <4 x i32> @sub_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -857,8 +857,8 @@ define <4 x i32> @sub_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_nsw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -872,8 +872,8 @@ define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -884,8 +884,8 @@ define <4 x i32> @mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars_nuw(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_nuw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -896,8 +896,8 @@ define <4 x i32> @mul_2_vars_nuw(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -910,8 +910,8 @@ define <4 x i32> @mul_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_nuw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -924,8 +924,8 @@ define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -936,8 +936,8 @@ define <4 x i32> @shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_nsw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -950,8 +950,8 @@ define <4 x i32> @shl_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -964,8 +964,8 @@ define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_nsw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -978,8 +978,8 @@ define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @lshr_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @lshr_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -990,8 +990,8 @@ define <4 x i32> @lshr_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @lshr_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @lshr_2_vars_exact(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1034,8 +1034,8 @@ define <4 x i32> @lshr_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1)
define <3 x i32> @ashr_2_vars(<3 x i32> %v0, <3 x i32> %v1) {
; CHECK-LABEL: @ashr_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[V1:%.*]], <3 x i32> [[V0:%.*]], <3 x i32> <i32 0, i32 4, i32 5>
-; CHECK-NEXT: [[TMP2:%.*]] = ashr <3 x i32> [[TMP1]], <i32 4, i32 2, i32 3>
-; CHECK-NEXT: ret <3 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[TMP1]], <i32 4, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
%t2 = ashr <3 x i32> %v1, <i32 4, i32 5, i32 6>
@@ -1046,8 +1046,8 @@ define <3 x i32> @ashr_2_vars(<3 x i32> %v0, <3 x i32> %v1) {
define <3 x i42> @and_2_vars(<3 x i42> %v0, <3 x i42> %v1) {
; CHECK-LABEL: @and_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i42> [[V0:%.*]], <3 x i42> [[V1:%.*]], <3 x i32> <i32 0, i32 4, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i42> [[TMP1]], <i42 1, i42 5, i42 undef>
-; CHECK-NEXT: ret <3 x i42> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[TMP1]], <i42 1, i42 5, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[T3]]
;
%t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
%t2 = and <3 x i42> %v1, <i42 4, i42 5, i42 6>
@@ -1061,9 +1061,9 @@ define <4 x i32> @or_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @or_2_vars(
; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = or <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1096,8 +1096,8 @@ define <4 x i32> @xor_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = udiv <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1108,8 +1108,8 @@ define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @udiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars_exact(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = udiv exact <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = udiv exact <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1152,8 +1152,8 @@ define <4 x i32> @udiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1)
define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1164,8 +1164,8 @@ define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_exact(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1178,8 +1178,8 @@ define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sdiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1192,8 +1192,8 @@ define <4 x i32> @sdiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sdiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_exact_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1206,8 +1206,8 @@ define <4 x i32> @sdiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1)
define <4 x i32> @urem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @urem_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1233,8 +1233,8 @@ define <4 x i32> @srem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x float> @fadd_2_vars(<4 x float> %v0, <4 x float> %v1) {
; CHECK-LABEL: @fadd_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[V0:%.*]], <4 x float> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fadd <4 x float> %v1, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -1245,8 +1245,8 @@ define <4 x float> @fadd_2_vars(<4 x float> %v0, <4 x float> %v1) {
define <4 x double> @fsub_2_vars(<4 x double> %v0, <4 x double> %v1) {
; CHECK-LABEL: @fsub_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
-; CHECK-NEXT: ret <4 x double> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v1
@@ -1259,8 +1259,8 @@ define <4 x double> @fsub_2_vars(<4 x double> %v0, <4 x double> %v1) {
define <4 x float> @fmul_2_vars(<4 x float> %v0, <4 x float> %v1) {
; CHECK-LABEL: @fmul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[V0:%.*]], <4 x float> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = fmul reassoc nsz <4 x float> [[TMP1]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fmul reassoc nsz <4 x float> [[TMP1]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fmul reassoc nsz <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fmul reassoc nsz <4 x float> %v1, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -1271,8 +1271,8 @@ define <4 x float> @fmul_2_vars(<4 x float> %v0, <4 x float> %v1) {
define <4 x double> @frem_2_vars(<4 x double> %v0, <4 x double> %v1) {
; CHECK-LABEL: @frem_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = frem <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
-; CHECK-NEXT: ret <4 x double> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = frem <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = frem nnan ninf <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = frem nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v1
@@ -1299,8 +1299,8 @@ define <4 x double> @fdiv_2_vars(<4 x double> %v0, <4 x double> %v1) {
define <4 x i32> @mul_shl(<4 x i32> %v0) {
; CHECK-LABEL: @mul_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = mul nuw <4 x i32> [[V0:%.*]], <i32 32, i32 64, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[V0:%.*]], <i32 32, i32 64, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -1312,8 +1312,8 @@ define <4 x i32> @mul_shl(<4 x i32> %v0) {
define <4 x i32> @shl_mul(<4 x i32> %v0) {
; CHECK-LABEL: @shl_mul(
-; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 5, i32 undef, i32 8, i32 16>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 5, i32 undef, i32 8, i32 16>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -1325,8 +1325,8 @@ define <4 x i32> @shl_mul(<4 x i32> %v0) {
define <4 x i32> @mul_is_nop_shl(<4 x i32> %v0) {
; CHECK-LABEL: @mul_is_nop_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 7, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -1354,8 +1354,8 @@ define <4 x i32> @shl_mul_not_constant_shift_amount(<4 x i32> %v0) {
define <4 x i32> @mul_shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_shl_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 32, i32 64, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 32, i32 64, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1366,8 +1366,8 @@ define <4 x i32> @mul_shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_mul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 undef, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 5, i32 undef, i32 8, i32 16>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 5, i32 undef, i32 8, i32 16>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1382,8 +1382,8 @@ define <4 x i32> @shl_mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @add_or(<4 x i32> %v) {
; CHECK-LABEL: @add_or(
; CHECK-NEXT: [[V0:%.*]] = shl <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0]], <i32 31, i32 31, i32 65536, i32 65537>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%v0 = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> ; clear the bottom bits
%t1 = add <4 x i32> %v0, <i32 65534, i32 65535, i32 65536, i32 65537> ; this can't be converted to 'or'
@@ -1397,8 +1397,8 @@ define <4 x i32> @add_or(<4 x i32> %v) {
define <4 x i8> @or_add(<4 x i8> %v) {
; CHECK-LABEL: @or_add(
; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 3, i8 3, i8 3, i8 3>
-; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw <4 x i8> [[V0]], <i8 1, i8 2, i8 -64, i8 -64>
-; CHECK-NEXT: ret <4 x i8> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add nuw nsw <4 x i8> [[V0]], <i8 1, i8 2, i8 -64, i8 -64>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
;
%v0 = lshr <4 x i8> %v, <i8 3, i8 3, i8 3, i8 3> ; clear the top bits
%t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
@@ -1430,8 +1430,8 @@ define <4 x i32> @add_or_2_vars(<4 x i32> %v, <4 x i32> %v1) {
; CHECK-LABEL: @add_or_2_vars(
; CHECK-NEXT: [[V0:%.*]] = shl <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], <i32 31, i32 31, i32 65536, i32 65537>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[TMP1]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%v0 = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> ; clear the bottom bits
%t1 = add <4 x i32> %v1, <i32 65534, i32 65535, i32 65536, i32 65537> ; this can't be converted to 'or'
@@ -1444,8 +1444,8 @@ define <4 x i8> @or_add_2_vars(<4 x i8> %v, <4 x i8> %v1) {
; CHECK-LABEL: @or_add_2_vars(
; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 3, i8 3, i8 3, i8 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[V1:%.*]], <4 x i8> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw <4 x i8> [[TMP1]], <i8 1, i8 2, i8 -64, i8 -64>
-; CHECK-NEXT: ret <4 x i8> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = add nuw nsw <4 x i8> [[TMP1]], <i8 1, i8 2, i8 -64, i8 -64>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
;
%v0 = lshr <4 x i8> %v, <i8 3, i8 3, i8 3, i8 3> ; clear the top bits
%t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
diff --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll
index 044306f3b4811..49283cca3d817 100644
--- a/llvm/test/Transforms/InstCombine/shuffle_select.ll
+++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll
@@ -405,8 +405,8 @@ define <4 x double> @frem(<4 x double> %v) {
define <4 x i32> @add_add(<4 x i32> %v0) {
; CHECK-LABEL: @add_add(
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -416,8 +416,8 @@ define <4 x i32> @add_add(<4 x i32> %v0) {
define <4 x i32> @add_add_nsw(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_nsw(
-; CHECK-NEXT: [[TMP1:%.*]] = add nsw <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add nsw <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -427,8 +427,8 @@ define <4 x i32> @add_add_nsw(<4 x i32> %v0) {
define <4 x i32> @add_add_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -440,8 +440,8 @@ define <4 x i32> @add_add_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @add_add_nsw_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 undef, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -453,8 +453,8 @@ define <4 x i32> @add_add_nsw_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @sub_sub(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub(
-; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -464,8 +464,8 @@ define <4 x i32> @sub_sub(<4 x i32> %v0) {
define <4 x i32> @sub_sub_nuw(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_nuw(
-; CHECK-NEXT: [[TMP1:%.*]] = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -475,8 +475,8 @@ define <4 x i32> @sub_sub_nuw(<4 x i32> %v0) {
define <4 x i32> @sub_sub_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -488,8 +488,8 @@ define <4 x i32> @sub_sub_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sub_sub_nuw_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nuw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nuw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -502,8 +502,8 @@ define <4 x i32> @sub_sub_nuw_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @mul_mul(<4 x i32> %v0) {
; CHECK-LABEL: @mul_mul(
-; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -515,8 +515,8 @@ define <4 x i32> @mul_mul(<4 x i32> %v0) {
define <4 x i32> @shl_shl(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -526,8 +526,8 @@ define <4 x i32> @shl_shl(<4 x i32> %v0) {
define <4 x i32> @shl_shl_nuw(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_nuw(
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -539,8 +539,8 @@ define <4 x i32> @shl_shl_nuw(<4 x i32> %v0) {
define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -552,8 +552,8 @@ define <4 x i32> @shl_shl_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @shl_shl_nuw_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -565,8 +565,8 @@ define <4 x i32> @shl_shl_nuw_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @lshr_lshr(<4 x i32> %v0) {
; CHECK-LABEL: @lshr_lshr(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -578,8 +578,8 @@ define <4 x i32> @lshr_lshr(<4 x i32> %v0) {
define <3 x i32> @ashr_ashr(<3 x i32> %v0) {
; CHECK-LABEL: @ashr_ashr(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 4, i32 2, i32 3>
-; CHECK-NEXT: ret <3 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 4, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
%t2 = ashr <3 x i32> %v0, <i32 4, i32 5, i32 6>
@@ -589,8 +589,8 @@ define <3 x i32> @ashr_ashr(<3 x i32> %v0) {
define <3 x i42> @and_and(<3 x i42> %v0) {
; CHECK-LABEL: @and_and(
-; CHECK-NEXT: [[TMP1:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 5, i42 undef>
-; CHECK-NEXT: ret <3 x i42> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 5, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[T3]]
;
%t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
%t2 = and <3 x i42> %v0, <i42 4, i42 5, i42 6>
@@ -603,9 +603,9 @@ define <3 x i42> @and_and(<3 x i42> %v0) {
define <4 x i32> @or_or(<4 x i32> %v0) {
; CHECK-LABEL: @or_or(
; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
-; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = or <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -617,9 +617,9 @@ define <4 x i32> @or_or(<4 x i32> %v0) {
define <4 x i32> @xor_xor(<4 x i32> %v0) {
; CHECK-LABEL: @xor_xor(
; CHECK-NEXT: [[T2:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 7, i32 8>
-; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i32> [[V0]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: [[T3:%.*]] = xor <4 x i32> [[V0]], <i32 1, i32 6, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = xor <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = xor <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -632,10 +632,10 @@ define <4 x i32> @udiv_udiv(<4 x i32> %v0) {
; CHECK-LABEL: @udiv_udiv(
; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
-; CHECK-NEXT: [[TMP1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0]]
+; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0]]
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -649,8 +649,8 @@ define <4 x i32> @udiv_udiv(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -660,8 +660,8 @@ define <4 x i32> @sdiv_sdiv(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv_exact(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_exact(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -671,8 +671,8 @@ define <4 x i32> @sdiv_sdiv_exact(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -682,8 +682,8 @@ define <4 x i32> @sdiv_sdiv_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @sdiv_sdiv_exact_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -693,8 +693,8 @@ define <4 x i32> @sdiv_sdiv_exact_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @urem_urem(<4 x i32> %v0) {
; CHECK-LABEL: @urem_urem(
-; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -706,8 +706,8 @@ define <4 x i32> @urem_urem(<4 x i32> %v0) {
define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @urem_urem_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 0>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 0>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -717,8 +717,8 @@ define <4 x i32> @urem_urem_undef_mask_elt(<4 x i32> %v0) {
define <4 x i32> @srem_srem(<4 x i32> %v0) {
; CHECK-LABEL: @srem_srem(
-; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -730,8 +730,8 @@ define <4 x i32> @srem_srem(<4 x i32> %v0) {
define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) {
; CHECK-LABEL: @srem_srem_undef_mask_elt(
-; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> <i32 1, i32 0, i32 7, i32 4>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 0, i32 7, i32 4>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = srem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = srem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v0
@@ -743,8 +743,8 @@ define <4 x i32> @srem_srem_undef_mask_elt(<4 x i32> %v0) {
define <4 x float> @fadd_fadd(<4 x float> %v0) {
; CHECK-LABEL: @fadd_fadd(
-; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fadd <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -754,8 +754,8 @@ define <4 x float> @fadd_fadd(<4 x float> %v0) {
define <4 x double> @fsub_fsub(<4 x double> %v0) {
; CHECK-LABEL: @fsub_fsub(
-; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
@@ -767,8 +767,8 @@ define <4 x double> @fsub_fsub(<4 x double> %v0) {
define <4 x float> @fmul_fmul(<4 x float> %v0) {
; CHECK-LABEL: @fmul_fmul(
-; CHECK-NEXT: [[TMP1:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fmul nnan ninf <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fmul nnan ninf <4 x float> %v0, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -778,8 +778,8 @@ define <4 x float> @fmul_fmul(<4 x float> %v0) {
define <4 x double> @fdiv_fdiv(<4 x double> %v0) {
; CHECK-LABEL: @fdiv_fdiv(
-; CHECK-NEXT: [[TMP1:%.*]] = fdiv arcp <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
-; CHECK-NEXT: ret <4 x double> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = fdiv arcp <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = fdiv fast <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = fdiv nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v0
@@ -805,8 +805,8 @@ define <4 x double> @frem_frem(<4 x double> %v0) {
define <4 x i32> @add_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @add_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = add <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = add <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -819,8 +819,8 @@ define <4 x i32> @add_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -831,8 +831,8 @@ define <4 x i32> @sub_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_nsw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -843,8 +843,8 @@ define <4 x i32> @sub_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -857,8 +857,8 @@ define <4 x i32> @sub_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sub_2_vars_nsw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 undef, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sub nsw <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = sub nsw <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -872,8 +872,8 @@ define <4 x i32> @sub_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -884,8 +884,8 @@ define <4 x i32> @mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars_nuw(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_nuw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -896,8 +896,8 @@ define <4 x i32> @mul_2_vars_nuw(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -910,8 +910,8 @@ define <4 x i32> @mul_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_2_vars_nuw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 1, i32 undef, i32 3, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -924,8 +924,8 @@ define <4 x i32> @mul_2_vars_nuw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -936,8 +936,8 @@ define <4 x i32> @shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_nsw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 1, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -950,8 +950,8 @@ define <4 x i32> @shl_2_vars_nsw(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -964,8 +964,8 @@ define <4 x i32> @shl_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_2_vars_nsw_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = shl nsw <4 x i32> [[TMP1]], <i32 0, i32 6, i32 3, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -978,8 +978,8 @@ define <4 x i32> @shl_2_vars_nsw_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @lshr_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @lshr_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = lshr <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -990,8 +990,8 @@ define <4 x i32> @lshr_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @lshr_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @lshr_2_vars_exact(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = lshr exact <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = lshr exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = lshr exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1034,8 +1034,8 @@ define <4 x i32> @lshr_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1)
define <3 x i32> @ashr_2_vars(<3 x i32> %v0, <3 x i32> %v1) {
; CHECK-LABEL: @ashr_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[V1:%.*]], <3 x i32> [[V0:%.*]], <3 x i32> <i32 0, i32 4, i32 5>
-; CHECK-NEXT: [[TMP2:%.*]] = ashr <3 x i32> [[TMP1]], <i32 4, i32 2, i32 3>
-; CHECK-NEXT: ret <3 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[TMP1]], <i32 4, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x i32> [[T3]]
;
%t1 = ashr <3 x i32> %v0, <i32 1, i32 2, i32 3>
%t2 = ashr <3 x i32> %v1, <i32 4, i32 5, i32 6>
@@ -1046,8 +1046,8 @@ define <3 x i32> @ashr_2_vars(<3 x i32> %v0, <3 x i32> %v1) {
define <3 x i42> @and_2_vars(<3 x i42> %v0, <3 x i42> %v1) {
; CHECK-LABEL: @and_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i42> [[V0:%.*]], <3 x i42> [[V1:%.*]], <3 x i32> <i32 0, i32 4, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = and <3 x i42> [[TMP1]], <i42 1, i42 5, i42 undef>
-; CHECK-NEXT: ret <3 x i42> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[TMP1]], <i42 1, i42 5, i42 undef>
+; CHECK-NEXT: ret <3 x i42> [[T3]]
;
%t1 = and <3 x i42> %v0, <i42 1, i42 2, i42 3>
%t2 = and <3 x i42> %v1, <i42 4, i42 5, i42 6>
@@ -1062,8 +1062,8 @@ define <4 x i32> @or_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
call void @use_v4i32(<4 x i32> %t1)
@@ -1077,8 +1077,8 @@ define <4 x i32> @or_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 undef>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[TMP1]], <i32 5, i32 6, i32 3, i32 undef>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = or <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
call void @use_v4i32(<4 x i32> %t1)
@@ -1111,8 +1111,8 @@ define <4 x i32> @xor_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = udiv <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1123,8 +1123,8 @@ define <4 x i32> @udiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @udiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @udiv_2_vars_exact(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = udiv exact <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = udiv exact <4 x i32> <i32 5, i32 2, i32 3, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = udiv exact <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = udiv exact <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1167,8 +1167,8 @@ define <4 x i32> @udiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1)
define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1179,8 +1179,8 @@ define <4 x i32> @sdiv_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_exact(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1193,8 +1193,8 @@ define <4 x i32> @sdiv_2_vars_exact(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sdiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1207,8 +1207,8 @@ define <4 x i32> @sdiv_2_vars_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @sdiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @sdiv_2_vars_exact_undef_mask_elt(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = sdiv exact <4 x i32> [[TMP1]], <i32 1, i32 2, i32 7, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = sdiv exact <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = sdiv exact <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1221,8 +1221,8 @@ define <4 x i32> @sdiv_2_vars_exact_undef_mask_elt(<4 x i32> %v0, <4 x i32> %v1)
define <4 x i32> @urem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @urem_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[TMP1]]
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 8>, [[TMP1]]
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = urem <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %v0
%t2 = urem <4 x i32> <i32 5, i32 6, i32 7, i32 8>, %v1
@@ -1248,8 +1248,8 @@ define <4 x i32> @srem_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x float> @fadd_2_vars(<4 x float> %v0, <4 x float> %v1) {
; CHECK-LABEL: @fadd_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[V0:%.*]], <4 x float> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fadd <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fadd <4 x float> %v1, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -1260,8 +1260,8 @@ define <4 x float> @fadd_2_vars(<4 x float> %v0, <4 x float> %v1) {
define <4 x double> @fsub_2_vars(<4 x double> %v0, <4 x double> %v1) {
; CHECK-LABEL: @fsub_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
-; CHECK-NEXT: ret <4 x double> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = fsub <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = fsub <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v1
@@ -1274,8 +1274,8 @@ define <4 x double> @fsub_2_vars(<4 x double> %v0, <4 x double> %v1) {
define <4 x float> @fmul_2_vars(<4 x float> %v0, <4 x float> %v1) {
; CHECK-LABEL: @fmul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[V0:%.*]], <4 x float> [[V1:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = fmul reassoc nsz <4 x float> [[TMP1]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
-; CHECK-NEXT: ret <4 x float> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = fmul reassoc nsz <4 x float> [[TMP1]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
+; CHECK-NEXT: ret <4 x float> [[T3]]
;
%t1 = fmul reassoc nsz <4 x float> %v0, <float 1.0, float 2.0, float 3.0, float 4.0>
%t2 = fmul reassoc nsz <4 x float> %v1, <float 5.0, float 6.0, float 7.0, float 8.0>
@@ -1286,8 +1286,8 @@ define <4 x float> @fmul_2_vars(<4 x float> %v0, <4 x float> %v1) {
define <4 x double> @frem_2_vars(<4 x double> %v0, <4 x double> %v1) {
; CHECK-LABEL: @frem_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = frem <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
-; CHECK-NEXT: ret <4 x double> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = frem <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[TMP1]]
+; CHECK-NEXT: ret <4 x double> [[T3]]
;
%t1 = frem nnan ninf <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
%t2 = frem nnan arcp <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, %v1
@@ -1314,8 +1314,8 @@ define <4 x double> @fdiv_2_vars(<4 x double> %v0, <4 x double> %v1) {
define <4 x i32> @mul_shl(<4 x i32> %v0) {
; CHECK-LABEL: @mul_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = mul nuw <4 x i32> [[V0:%.*]], <i32 32, i32 64, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[V0:%.*]], <i32 32, i32 64, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -1327,8 +1327,8 @@ define <4 x i32> @mul_shl(<4 x i32> %v0) {
define <4 x i32> @shl_mul(<4 x i32> %v0) {
; CHECK-LABEL: @shl_mul(
-; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 5, i32 undef, i32 8, i32 16>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 5, i32 undef, i32 8, i32 16>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nsw <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -1340,8 +1340,8 @@ define <4 x i32> @shl_mul(<4 x i32> %v0) {
define <4 x i32> @mul_is_nop_shl(<4 x i32> %v0) {
; CHECK-LABEL: @mul_is_nop_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 7, i32 8>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = shl <4 x i32> [[V0:%.*]], <i32 0, i32 6, i32 7, i32 8>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl <4 x i32> %v0, <i32 5, i32 6, i32 7, i32 8>
@@ -1369,8 +1369,8 @@ define <4 x i32> @shl_mul_not_constant_shift_amount(<4 x i32> %v0) {
define <4 x i32> @mul_shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @mul_shl_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 32, i32 64, i32 3, i32 4>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul nuw <4 x i32> [[TMP1]], <i32 32, i32 64, i32 3, i32 4>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = mul nuw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = shl nuw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1381,8 +1381,8 @@ define <4 x i32> @mul_shl_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @shl_mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @shl_mul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <4 x i32> <i32 0, i32 undef, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 5, i32 undef, i32 8, i32 16>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[TMP1]], <i32 5, i32 undef, i32 8, i32 16>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%t1 = shl nsw <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%t2 = mul nsw <4 x i32> %v1, <i32 5, i32 6, i32 7, i32 8>
@@ -1394,8 +1394,8 @@ define <4 x i32> @shl_mul_2_vars(<4 x i32> %v0, <4 x i32> %v1) {
define <4 x i32> @mul_neg(<4 x i32> %x) {
; CHECK-LABEL: @mul_neg(
-; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[X:%.*]], <i32 257, i32 -3, i32 -1, i32 -9>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = mul <4 x i32> [[X:%.*]], <i32 257, i32 -3, i32 -1, i32 -9>
+; CHECK-NEXT: ret <4 x i32> [[R]]
;
%m = mul <4 x i32> %x, <i32 257, i32 -3, i32 poison, i32 -9>
%n = sub <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, %x
@@ -1405,8 +1405,8 @@ define <4 x i32> @mul_neg(<4 x i32> %x) {
define <3 x i79> @neg_mul(<3 x i79> %x) {
; CHECK-LABEL: @neg_mul(
-; CHECK-NEXT: [[TMP1:%.*]] = mul nsw <3 x i79> [[X:%.*]], <i79 -1, i79 -3, i79 -1>
-; CHECK-NEXT: ret <3 x i79> [[TMP1]]
+; CHECK-NEXT: [[R:%.*]] = mul nsw <3 x i79> [[X:%.*]], <i79 -1, i79 -3, i79 -1>
+; CHECK-NEXT: ret <3 x i79> [[R]]
;
%n = sub nsw <3 x i79> <i79 0, i79 poison, i79 0>, %x
%m = mul nsw <3 x i79> %x, <i79 poison, i79 -3, i79 poison>
@@ -1417,8 +1417,8 @@ define <3 x i79> @neg_mul(<3 x i79> %x) {
define <4 x i32> @mul_neg_2_vars(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @mul_neg_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 42, i32 -1, i32 -1, i32 6>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = mul <4 x i32> [[TMP1]], <i32 42, i32 -1, i32 -1, i32 6>
+; CHECK-NEXT: ret <4 x i32> [[R]]
;
%m = mul nuw <4 x i32> %x, <i32 42, i32 poison, i32 poison, i32 6>
%n = sub nsw <4 x i32> <i32 poison, i32 0, i32 0, i32 poison>, %y
@@ -1429,8 +1429,8 @@ define <4 x i32> @mul_neg_2_vars(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @neg_mul_2_vars(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @neg_mul_2_vars(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = mul nsw <4 x i32> [[TMP1]], <i32 -1, i32 42, i32 -1, i32 6>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = mul nsw <4 x i32> [[TMP1]], <i32 -1, i32 42, i32 -1, i32 6>
+; CHECK-NEXT: ret <4 x i32> [[R]]
;
%n = sub nsw <4 x i32> <i32 0, i32 poison, i32 0, i32 poison>, %y
%m = mul nuw nsw <4 x i32> %x, <i32 poison, i32 42, i32 poison, i32 6>
@@ -1445,8 +1445,8 @@ define <4 x i32> @neg_mul_2_vars(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @add_or(<4 x i32> %v) {
; CHECK-LABEL: @add_or(
; CHECK-NEXT: [[V0:%.*]] = shl <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
-; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[V0]], <i32 31, i32 31, i32 65536, i32 65537>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%v0 = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> ; clear the bottom bits
%t1 = add <4 x i32> %v0, <i32 65534, i32 65535, i32 65536, i32 65537> ; this can't be converted to 'or'
@@ -1460,8 +1460,8 @@ define <4 x i32> @add_or(<4 x i32> %v) {
define <4 x i8> @or_add(<4 x i8> %v) {
; CHECK-LABEL: @or_add(
; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 3, i8 3, i8 3, i8 3>
-; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw <4 x i8> [[V0]], <i8 1, i8 2, i8 -64, i8 -64>
-; CHECK-NEXT: ret <4 x i8> [[TMP1]]
+; CHECK-NEXT: [[T3:%.*]] = add nuw nsw <4 x i8> [[V0]], <i8 1, i8 2, i8 -64, i8 -64>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
;
%v0 = lshr <4 x i8> %v, <i8 3, i8 3, i8 3, i8 3> ; clear the top bits
%t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
@@ -1493,8 +1493,8 @@ define <4 x i32> @add_or_2_vars(<4 x i32> %v, <4 x i32> %v1) {
; CHECK-LABEL: @add_or_2_vars(
; CHECK-NEXT: [[V0:%.*]] = shl <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0]], <4 x i32> [[V1:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], <i32 31, i32 31, i32 65536, i32 65537>
-; CHECK-NEXT: ret <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[TMP1]], <i32 31, i32 31, i32 65536, i32 65537>
+; CHECK-NEXT: ret <4 x i32> [[T3]]
;
%v0 = shl <4 x i32> %v, <i32 5, i32 5, i32 5, i32 5> ; clear the bottom bits
%t1 = add <4 x i32> %v1, <i32 65534, i32 65535, i32 65536, i32 65537> ; this can't be converted to 'or'
@@ -1507,8 +1507,8 @@ define <4 x i8> @or_add_2_vars(<4 x i8> %v, <4 x i8> %v1) {
; CHECK-LABEL: @or_add_2_vars(
; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 3, i8 3, i8 3, i8 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[V1:%.*]], <4 x i8> [[V0]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw <4 x i8> [[TMP1]], <i8 1, i8 2, i8 -64, i8 -64>
-; CHECK-NEXT: ret <4 x i8> [[TMP2]]
+; CHECK-NEXT: [[T3:%.*]] = add nuw nsw <4 x i8> [[TMP1]], <i8 1, i8 2, i8 -64, i8 -64>
+; CHECK-NEXT: ret <4 x i8> [[T3]]
;
%v0 = lshr <4 x i8> %v, <i8 3, i8 3, i8 3, i8 3> ; clear the top bits
%t1 = or <4 x i8> %v0, <i8 192, i8 192, i8 192, i8 192> ; set some top bits
diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
index d7684aa4a204b..442175d9c9691 100644
--- a/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
@@ -89,8 +89,8 @@ define <2 x i16> @test_udiv(i16 %a, i1 %cmp) {
define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_fdiv(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1
-; CHECK-NEXT: [[TMP2:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
-; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[TMP2]]
+; CHECK-NEXT: [[SPLAT_OP:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
+; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]]
;
%splatinsert = insertelement <2 x float> poison, float %a, i32 0
@@ -106,8 +106,8 @@ define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
define <2 x float> @test_frem(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_frem(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1
-; CHECK-NEXT: [[TMP2:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
-; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[TMP2]]
+; CHECK-NEXT: [[SPLAT_OP:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
+; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]]
;
%splatinsert = insertelement <2 x float> poison, float %a, i32 0
diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
index 6345a586741c9..0aadcbc5cdefd 100644
--- a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
@@ -89,8 +89,8 @@ define <2 x i16> @test_udiv(i16 %a, i1 %cmp) {
define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_fdiv(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1
-; CHECK-NEXT: [[TMP2:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
-; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[TMP2]]
+; CHECK-NEXT: [[SPLAT_OP:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
+; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]]
;
%splatinsert = insertelement <2 x float> undef, float %a, i32 0
@@ -106,8 +106,8 @@ define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
define <2 x float> @test_frem(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_frem(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1
-; CHECK-NEXT: [[TMP2:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
-; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[TMP2]]
+; CHECK-NEXT: [[SPLAT_OP:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
+; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]]
;
%splatinsert = insertelement <2 x float> undef, float %a, i32 0
diff --git a/llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll
index 4775dd80338ab..1633ec8a89d3b 100644
--- a/llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll
@@ -200,8 +200,8 @@ define i1 @scalar_i32_signbit_lshr_and_eq_X_is_constant1(i32 %y) {
define i1 @scalar_i32_signbit_lshr_and_eq_X_is_constant2(i32 %y) {
; CHECK-LABEL: @scalar_i32_signbit_lshr_and_eq_X_is_constant2(
-; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[Y:%.*]], 31
-; CHECK-NEXT: ret i1 [[R]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 31
+; CHECK-NEXT: ret i1 [[TMP1]]
;
%lshr = lshr i32 2147483648, %y
%and = and i32 %lshr, 1
diff --git a/llvm/test/Transforms/InstCombine/signed-comparison.ll b/llvm/test/Transforms/InstCombine/signed-comparison.ll
index 9c80248ca2b5d..71f3265e7894b 100644
--- a/llvm/test/Transforms/InstCombine/signed-comparison.ll
+++ b/llvm/test/Transforms/InstCombine/signed-comparison.ll
@@ -5,7 +5,7 @@
define i1 @scalar_zext_slt(i16 %t4) {
; CHECK-LABEL: @scalar_zext_slt(
-; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
+; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 [[T4:%.*]], 500
; CHECK-NEXT: ret i1 [[T6]]
;
%t5 = zext i16 %t4 to i32
@@ -15,7 +15,7 @@ define i1 @scalar_zext_slt(i16 %t4) {
define <4 x i1> @vector_zext_slt(<4 x i16> %t4) {
; CHECK-LABEL: @vector_zext_slt(
-; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
+; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> [[T4:%.*]], <i16 500, i16 0, i16 501, i16 -1>
; CHECK-NEXT: ret <4 x i1> [[T6]]
;
%t5 = zext <4 x i16> %t4 to <4 x i32>
diff --git a/llvm/test/Transforms/InstCombine/sink-into-catchswitch.ll b/llvm/test/Transforms/InstCombine/sink-into-catchswitch.ll
index 443141314811e..0e4c3f9205831 100644
--- a/llvm/test/Transforms/InstCombine/sink-into-catchswitch.ll
+++ b/llvm/test/Transforms/InstCombine/sink-into-catchswitch.ll
@@ -9,8 +9,8 @@ target triple = "x86_64-pc-windows-msvc18.0.0"
define void @test1(ptr %p) personality ptr @__CxxFrameHandler3 {
; CHECK-LABEL: @test1(
; CHECK-NEXT: invoke.cont:
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[P:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[P:%.*]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[TMP0]], i64 0
; CHECK-NEXT: invoke void @throw()
; CHECK-NEXT: to label [[UNREACHABLE:%.*]] unwind label [[CATCH_DISPATCH:%.*]]
; CHECK: catch.dispatch:
@@ -20,7 +20,7 @@ define void @test1(ptr %p) personality ptr @__CxxFrameHandler3 {
; CHECK-NEXT: invoke void @throw() [ "funclet"(token [[CATCH]]) ]
; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[EHCLEANUP]]
; CHECK: ehcleanup:
-; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[TMP2]], [[CATCH_DISPATCH]] ], [ 9, [[INVOKE_CONT1:%.*]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[TMP1]], [[CATCH_DISPATCH]] ], [ 9, [[INVOKE_CONT1:%.*]] ]
; CHECK-NEXT: [[CLEANUP:%.*]] = cleanuppad within none []
; CHECK-NEXT: call void @release(i64 [[PHI]]) [ "funclet"(token [[CLEANUP]]) ]
; CHECK-NEXT: cleanupret from [[CLEANUP]] unwind to caller
diff --git a/llvm/test/Transforms/InstCombine/sink_instruction.ll b/llvm/test/Transforms/InstCombine/sink_instruction.ll
index 631043c478007..37a72b92d2db7 100644
--- a/llvm/test/Transforms/InstCombine/sink_instruction.ll
+++ b/llvm/test/Transforms/InstCombine/sink_instruction.ll
@@ -41,7 +41,7 @@ define i32 @test2(i32 %x) nounwind ssp {
; CHECK: bb1:
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[X_ADDR_17]], 1
; CHECK-NEXT: [[TMP2:%.*]] = sdiv i32 [[TMP1]], [[X_ADDR_17]]
-; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @bar() #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @bar() #[[ATTR3:[0-9]+]]
; CHECK-NEXT: br label [[BB2]]
; CHECK: bb2:
; CHECK-NEXT: [[X_ADDR_0]] = phi i32 [ [[TMP2]], [[BB1]] ], [ [[X_ADDR_17]], [[BB]] ]
@@ -179,10 +179,10 @@ sw.epilog: ; preds = %entry, %sw.bb
define i32 @test6(ptr nocapture readonly %P, i32 %i, i1 %cond) {
; CHECK-LABEL: @test6(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ADD:%.*]] = shl nsw i32 [[I]], 1
+; CHECK-NEXT: [[ADD:%.*]] = shl nsw i32 [[I:%.*]], 1
; CHECK-NEXT: br label [[DISPATCHBB:%.*]]
; CHECK: dispatchBB:
-; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[I:%.*]] to i64
+; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[I]] to i64
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[IDXPROM]]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: switch i32 [[I]], label [[SW_BB:%.*]] [
diff --git a/llvm/test/Transforms/InstCombine/sprintf-1.ll b/llvm/test/Transforms/InstCombine/sprintf-1.ll
index 88e4245132604..b9354bb4b2990 100644
--- a/llvm/test/Transforms/InstCombine/sprintf-1.ll
+++ b/llvm/test/Transforms/InstCombine/sprintf-1.ll
@@ -97,8 +97,8 @@ define i32 @test_simplify7(ptr %dst, ptr %str) {
; WITHSTPCPY-NEXT: [[STPCPY:%.*]] = call ptr @stpcpy(ptr [[DST:%.*]], ptr [[STR:%.*]])
; WITHSTPCPY-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[STPCPY]] to i32
; WITHSTPCPY-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[DST]] to i32
-; WITHSTPCPY-NEXT: [[TMP3:%.*]] = sub i32 [[TMP1]], [[TMP2]]
-; WITHSTPCPY-NEXT: ret i32 [[TMP3]]
+; WITHSTPCPY-NEXT: [[R:%.*]] = sub i32 [[TMP1]], [[TMP2]]
+; WITHSTPCPY-NEXT: ret i32 [[R]]
;
; NOSTPCPY-LABEL: @test_simplify7(
; NOSTPCPY-NEXT: [[STRLEN:%.*]] = call i32 @strlen(ptr noundef nonnull dereferenceable(1) [[STR:%.*]])
@@ -127,8 +127,8 @@ define i32 @test_simplify9(ptr %dst, ptr %str) {
; WITHSTPCPY-NEXT: [[STPCPY:%.*]] = call ptr @stpcpy(ptr [[DST:%.*]], ptr [[STR:%.*]])
; WITHSTPCPY-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[STPCPY]] to i32
; WITHSTPCPY-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[DST]] to i32
-; WITHSTPCPY-NEXT: [[TMP3:%.*]] = sub i32 [[TMP1]], [[TMP2]]
-; WITHSTPCPY-NEXT: ret i32 [[TMP3]]
+; WITHSTPCPY-NEXT: [[R:%.*]] = sub i32 [[TMP1]], [[TMP2]]
+; WITHSTPCPY-NEXT: ret i32 [[R]]
;
; NOSTPCPY-LABEL: @test_simplify9(
; NOSTPCPY-NEXT: [[STRLEN:%.*]] = call i32 @strlen(ptr noundef nonnull dereferenceable(1) [[STR:%.*]])
@@ -163,8 +163,8 @@ define i32 @test_no_simplify3(ptr %dst, ptr %str) minsize {
; WITHSTPCPY-NEXT: [[STPCPY:%.*]] = call ptr @stpcpy(ptr [[DST:%.*]], ptr [[STR:%.*]])
; WITHSTPCPY-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[STPCPY]] to i32
; WITHSTPCPY-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[DST]] to i32
-; WITHSTPCPY-NEXT: [[TMP3:%.*]] = sub i32 [[TMP1]], [[TMP2]]
-; WITHSTPCPY-NEXT: ret i32 [[TMP3]]
+; WITHSTPCPY-NEXT: [[R:%.*]] = sub i32 [[TMP1]], [[TMP2]]
+; WITHSTPCPY-NEXT: ret i32 [[R]]
;
; NOSTPCPY-LABEL: @test_no_simplify3(
; NOSTPCPY-NEXT: [[R:%.*]] = call i32 (ptr, ptr, ...) @sprintf(ptr noundef nonnull dereferenceable(1) [[DST:%.*]], ptr noundef nonnull dereferenceable(1) @percent_s, ptr [[STR:%.*]])
diff --git a/llvm/test/Transforms/InstCombine/sprintf-3.ll b/llvm/test/Transforms/InstCombine/sprintf-3.ll
index f88e6920d562c..7e47d90e6f29b 100644
--- a/llvm/test/Transforms/InstCombine/sprintf-3.ll
+++ b/llvm/test/Transforms/InstCombine/sprintf-3.ll
@@ -1,6 +1,6 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; Regression test for PR51200.
;
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
;
; This transformation requires the pointer size, as it assumes that size_t is
@@ -11,9 +11,16 @@
declare i32 @sprintf(ptr, ptr, ...)
define i32 @PR51200(ptr %p, ptr %p2) {
-; CHECK-LABEL: @PR51200(
-; Don't check anything, just expect the test to compile successfully.
+; CHECK-LABEL: define i32 @PR51200
+; CHECK-SAME: (ptr [[P:%.*]], ptr [[P2:%.*]]) {
+; CHECK-NEXT: [[STPCPY:%.*]] = call ptr @stpcpy(ptr [[P]], ptr [[P2]])
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[STPCPY]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[CALL:%.*]] = trunc i64 [[TMP3]] to i32
+; CHECK-NEXT: ret i32 [[CALL]]
;
+; Don't check anything, just expect the test to compile successfully.
%call = call i32 (ptr, ptr, ...) @sprintf(ptr %p, ptr @percent_s, ptr %p2)
ret i32 %call
}
diff --git a/llvm/test/Transforms/InstCombine/ssub-with-overflow.ll b/llvm/test/Transforms/InstCombine/ssub-with-overflow.ll
index 16a4409e585b6..70fd4eefe74f5 100644
--- a/llvm/test/Transforms/InstCombine/ssub-with-overflow.ll
+++ b/llvm/test/Transforms/InstCombine/ssub-with-overflow.ll
@@ -11,8 +11,8 @@ declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8)
define { i32, i1 } @simple_fold(i32 %x) {
; CHECK-LABEL: @simple_fold(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 -20)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 -20)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = sub nsw i32 %x, 7
%b = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 13)
@@ -32,8 +32,8 @@ define { i32, i1 } @fold_mixed_signs(i32 %x) {
define { i8, i1 } @fold_on_constant_sub_no_overflow(i8 %x) {
; CHECK-LABEL: @fold_on_constant_sub_no_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X:%.*]], i8 -128)
-; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X:%.*]], i8 -128)
+; CHECK-NEXT: ret { i8, i1 } [[B]]
;
%a = sub nsw i8 %x, 100
%b = tail call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %a, i8 28)
@@ -43,8 +43,8 @@ define { i8, i1 } @fold_on_constant_sub_no_overflow(i8 %x) {
define { i8, i1 } @no_fold_on_constant_sub_overflow(i8 %x) {
; CHECK-LABEL: @no_fold_on_constant_sub_overflow(
; CHECK-NEXT: [[A:%.*]] = add nsw i8 [[X:%.*]], -100
-; CHECK-NEXT: [[TMP1:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A]], i8 -29)
-; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A]], i8 -29)
+; CHECK-NEXT: ret { i8, i1 } [[B]]
;
%a = sub nsw i8 %x, 100
%b = tail call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %a, i8 29)
@@ -53,8 +53,8 @@ define { i8, i1 } @no_fold_on_constant_sub_overflow(i8 %x) {
define { <2 x i32>, <2 x i1> } @fold_simple_splat_constant(<2 x i32> %x) {
; CHECK-LABEL: @fold_simple_splat_constant(
-; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -42, i32 -42>)
-; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -42, i32 -42>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
;
%a = sub nsw <2 x i32> %x, <i32 12, i32 12>
%b = tail call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
@@ -64,8 +64,8 @@ define { <2 x i32>, <2 x i1> } @fold_simple_splat_constant(<2 x i32> %x) {
define { <2 x i32>, <2 x i1> } @no_fold_splat_undef_constant(<2 x i32> %x) {
; CHECK-LABEL: @no_fold_splat_undef_constant(
; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[X:%.*]], <i32 -12, i32 undef>
-; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[A]], <2 x i32> <i32 -30, i32 -30>)
-; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[A]], <2 x i32> <i32 -30, i32 -30>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
;
%a = sub nsw <2 x i32> %x, <i32 12, i32 undef>
%b = tail call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
@@ -75,8 +75,8 @@ define { <2 x i32>, <2 x i1> } @no_fold_splat_undef_constant(<2 x i32> %x) {
define { <2 x i32>, <2 x i1> } @no_fold_splat_not_constant(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @no_fold_splat_not_constant(
; CHECK-NEXT: [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[A]], <2 x i32> <i32 -30, i32 -30>)
-; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[A]], <2 x i32> <i32 -30, i32 -30>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
;
%a = sub nsw <2 x i32> %x, %y
%b = tail call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
@@ -85,8 +85,8 @@ define { <2 x i32>, <2 x i1> } @no_fold_splat_not_constant(<2 x i32> %x, <2 x i3
define { i32, i1 } @fold_nuwnsw(i32 %x) {
; CHECK-LABEL: @fold_nuwnsw(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 -42)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 -42)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = sub nuw nsw i32 %x, 12
%b = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 30)
@@ -96,8 +96,8 @@ define { i32, i1 } @fold_nuwnsw(i32 %x) {
define { i32, i1 } @no_fold_nuw(i32 %x) {
; CHECK-LABEL: @no_fold_nuw(
; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], -12
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A]], i32 -30)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A]], i32 -30)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = sub nuw i32 %x, 12
%b = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 30)
@@ -117,8 +117,8 @@ define { i32, i1 } @no_fold_wrapped_sub(i32 %x) {
define { i32, i1 } @fold_add_simple(i32 %x) {
; CHECK-LABEL: @fold_add_simple(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 -42)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[X:%.*]], i32 -42)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = add nsw i32 %x, -12
%b = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 30)
@@ -136,8 +136,8 @@ define { <2 x i32>, <2 x i1> } @keep_ssubo_undef(<2 x i32> %x) {
define { <2 x i32>, <2 x i1> } @keep_ssubo_non_splat(<2 x i32> %x) {
; CHECK-LABEL: @keep_ssubo_non_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -30, i32 -31>)
-; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+; CHECK-NEXT: [[A:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -30, i32 -31>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[A]]
;
%a = tail call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> %x, <2 x i32> <i32 30, i32 31>)
ret { <2 x i32>, <2 x i1> } %a
diff --git a/llvm/test/Transforms/InstCombine/store.ll b/llvm/test/Transforms/InstCombine/store.ll
index 95ba64c9e6401..70f5d9a1209ae 100644
--- a/llvm/test/Transforms/InstCombine/store.ll
+++ b/llvm/test/Transforms/InstCombine/store.ll
@@ -340,6 +340,7 @@ define void @store_to_constant() {
define void @store_to_readonly_noalias(ptr readonly noalias %0) {
; CHECK-LABEL: @store_to_readonly_noalias(
; CHECK-NEXT: ret void
+;
store i32 3, ptr %0, align 4
ret void
}
diff --git a/llvm/test/Transforms/InstCombine/strcmp-1.ll b/llvm/test/Transforms/InstCombine/strcmp-1.ll
index 7ac433ad862a1..0dff891171fe1 100644
--- a/llvm/test/Transforms/InstCombine/strcmp-1.ll
+++ b/llvm/test/Transforms/InstCombine/strcmp-1.ll
@@ -22,14 +22,14 @@ define i32 @test1(ptr %str2) {
; NOBCMP-LABEL: @test1(
; NOBCMP-NEXT: [[STRCMPLOAD:%.*]] = load i8, ptr [[STR2:%.*]], align 1
; NOBCMP-NEXT: [[TMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
-; NOBCMP-NEXT: [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
-; NOBCMP-NEXT: ret i32 [[TMP2]]
+; NOBCMP-NEXT: [[TEMP1:%.*]] = sub nsw i32 0, [[TMP1]]
+; NOBCMP-NEXT: ret i32 [[TEMP1]]
;
; BCMP-LABEL: @test1(
; BCMP-NEXT: [[STRCMPLOAD:%.*]] = load i8, ptr [[STR2:%.*]], align 1
; BCMP-NEXT: [[TMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
-; BCMP-NEXT: [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
-; BCMP-NEXT: ret i32 [[TMP2]]
+; BCMP-NEXT: [[TEMP1:%.*]] = sub nsw i32 0, [[TMP1]]
+; BCMP-NEXT: ret i32 [[TEMP1]]
;
%temp1 = call i32 @strcmp(ptr @null, ptr %str2)
ret i32 %temp1
@@ -44,13 +44,13 @@ define i32 @test2(ptr %str1) {
; CHECK: ret i32 %1
; NOBCMP-LABEL: @test2(
; NOBCMP-NEXT: [[STRCMPLOAD:%.*]] = load i8, ptr [[STR1:%.*]], align 1
-; NOBCMP-NEXT: [[TMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
-; NOBCMP-NEXT: ret i32 [[TMP1]]
+; NOBCMP-NEXT: [[TEMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
+; NOBCMP-NEXT: ret i32 [[TEMP1]]
;
; BCMP-LABEL: @test2(
; BCMP-NEXT: [[STRCMPLOAD:%.*]] = load i8, ptr [[STR1:%.*]], align 1
-; BCMP-NEXT: [[TMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
-; BCMP-NEXT: ret i32 [[TMP1]]
+; BCMP-NEXT: [[TEMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
+; BCMP-NEXT: ret i32 [[TEMP1]]
;
%temp1 = call i32 @strcmp(ptr %str1, ptr @null)
ret i32 %temp1
diff --git a/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll b/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
index f1702596b5dd9..7fdfa35e0d138 100644
--- a/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
+++ b/llvm/test/Transforms/InstCombine/strcpy_chk-1.ll
@@ -79,8 +79,8 @@ define ptr @test_simplify4_tail() {
define ptr @test_simplify5() {
; CHECK-LABEL: @test_simplify5(
; CHECK-NEXT: [[LEN:%.*]] = call i32 @llvm.objectsize.i32.p0(ptr @a, i1 false, i1 false, i1 false)
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr @__memcpy_chk(ptr nonnull @a, ptr nonnull @.str, i32 12, i32 [[LEN]])
-; CHECK-NEXT: ret ptr [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = call ptr @__memcpy_chk(ptr nonnull @a, ptr nonnull @.str, i32 12, i32 [[LEN]])
+; CHECK-NEXT: ret ptr [[RET]]
;
%len = call i32 @llvm.objectsize.i32.p0(ptr @a, i1 false, i1 false, i1 false)
diff --git a/llvm/test/Transforms/InstCombine/strlen-1.ll b/llvm/test/Transforms/InstCombine/strlen-1.ll
index e1b6a968d7484..bd4c4a2ce47e9 100644
--- a/llvm/test/Transforms/InstCombine/strlen-1.ll
+++ b/llvm/test/Transforms/InstCombine/strlen-1.ll
@@ -95,8 +95,8 @@ define i1 @test_simplify8(ptr %str_p) {
define i32 @test_simplify9(i1 %x) {
; CHECK-LABEL: @test_simplify9(
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i32 5, i32 6
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = select i1 [[X:%.*]], i32 5, i32 6
+; CHECK-NEXT: ret i32 [[L]]
;
%s = select i1 %x, ptr @hello, ptr @longer
%l = call i32 @strlen(ptr %s)
@@ -108,8 +108,8 @@ define i32 @test_simplify9(i1 %x) {
define i32 @test_simplify10_inbounds(i32 %x) {
; CHECK-LABEL: @test_simplify10_inbounds(
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 5, [[X:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[HELLO_L:%.*]] = sub i32 5, [[X:%.*]]
+; CHECK-NEXT: ret i32 [[HELLO_L]]
;
%hello_p = getelementptr inbounds [6 x i8], ptr @hello, i32 0, i32 %x
%hello_l = call i32 @strlen(ptr %hello_p)
@@ -118,8 +118,8 @@ define i32 @test_simplify10_inbounds(i32 %x) {
define i32 @test_simplify10_no_inbounds(i32 %x) {
; CHECK-LABEL: @test_simplify10_no_inbounds(
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 5, [[X:%.*]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[HELLO_L:%.*]] = sub i32 5, [[X:%.*]]
+; CHECK-NEXT: ret i32 [[HELLO_L]]
;
%hello_p = getelementptr [6 x i8], ptr @hello, i32 0, i32 %x
%hello_l = call i32 @strlen(ptr %hello_p)
@@ -131,8 +131,8 @@ define i32 @test_simplify10_no_inbounds(i32 %x) {
define i32 @test_simplify11(i32 %x) {
; CHECK-LABEL: @test_simplify11(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 7
-; CHECK-NEXT: [[TMP1:%.*]] = sub nuw nsw i32 9, [[AND]]
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[HELLO_L:%.*]] = sub nuw nsw i32 9, [[AND]]
+; CHECK-NEXT: ret i32 [[HELLO_L]]
;
%and = and i32 %x, 7
%hello_p = getelementptr inbounds [13 x i8], ptr @null_hello_mid, i32 0, i32 %and
diff --git a/llvm/test/Transforms/InstCombine/strncmp-1.ll b/llvm/test/Transforms/InstCombine/strncmp-1.ll
index da16448983552..9a33b85a4049c 100644
--- a/llvm/test/Transforms/InstCombine/strncmp-1.ll
+++ b/llvm/test/Transforms/InstCombine/strncmp-1.ll
@@ -16,8 +16,8 @@ define i32 @test1(ptr %str2) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[STRCMPLOAD:%.*]] = load i8, ptr [[STR2:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[TEMP1:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: ret i32 [[TEMP1]]
;
%temp1 = call i32 @strncmp(ptr @null, ptr %str2, i32 10)
@@ -28,8 +28,8 @@ define i32 @test1(ptr %str2) {
define i32 @test2(ptr %str1) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[STRCMPLOAD:%.*]] = load i8, ptr [[STR1:%.*]], align 1
-; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[TEMP1:%.*]] = zext i8 [[STRCMPLOAD]] to i32
+; CHECK-NEXT: ret i32 [[TEMP1]]
;
%temp1 = call i32 @strncmp(ptr %str1, ptr @null, i32 10)
diff --git a/llvm/test/Transforms/InstCombine/strncmp-5.ll b/llvm/test/Transforms/InstCombine/strncmp-5.ll
index 4630a5e5d6bb1..1065091fc4c71 100644
--- a/llvm/test/Transforms/InstCombine/strncmp-5.ll
+++ b/llvm/test/Transforms/InstCombine/strncmp-5.ll
@@ -20,27 +20,27 @@ define void @fold_strncmp_a_b_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_strncmp_a_b_n(
; CHECK-NEXT: store i32 0, ptr [[PCMP:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[N:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: [[C0_1:%.*]] = sext i1 [[TMP1]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[S0_1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_2:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S0_2:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S0_2]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[C0_2]], ptr [[S0_2]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_3:%.*]] = sext i1 [[TMP3]] to i32
; CHECK-NEXT: [[S0_3:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[S0_3]], align 4
+; CHECK-NEXT: store i32 [[C0_3]], ptr [[S0_3]], align 4
; CHECK-NEXT: [[S0_4:%.*]] = getelementptr i32, ptr [[PCMP]], i64 4
; CHECK-NEXT: store i32 0, ptr [[S0_4]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_5:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[S0_5:%.*]] = getelementptr i32, ptr [[PCMP]], i64 5
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[S0_5]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP10:%.*]] = zext i1 [[TMP9]] to i32
+; CHECK-NEXT: store i32 [[C0_5]], ptr [[S0_5]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C5_0:%.*]] = zext i1 [[TMP5]] to i32
; CHECK-NEXT: [[S5_0:%.*]] = getelementptr i32, ptr [[PCMP]], i64 6
-; CHECK-NEXT: store i32 [[TMP10]], ptr [[S5_0]], align 4
+; CHECK-NEXT: store i32 [[C5_0]], ptr [[S5_0]], align 4
; CHECK-NEXT: ret void
;
@@ -113,28 +113,28 @@ define void @call_strncmp_a_ax_n(ptr %pcmp, i64 %n) {
define void @fold_strncmp_a_c_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_strncmp_a_c_n(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[N:%.*]], 7
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[PCMP:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: [[C0_0:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: store i32 [[C0_0]], ptr [[PCMP:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_1:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S0_1]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_2:%.*]] = sext i1 [[TMP3]] to i32
; CHECK-NEXT: [[S0_2:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[S0_2]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = sext i1 [[TMP7]] to i32
+; CHECK-NEXT: store i32 [[C0_2]], ptr [[S0_2]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_3:%.*]] = sext i1 [[TMP4]] to i32
; CHECK-NEXT: [[S0_3:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[S0_3]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 3
-; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i32
+; CHECK-NEXT: store i32 [[C0_3]], ptr [[S0_3]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[N]], 3
+; CHECK-NEXT: [[C0_4:%.*]] = sext i1 [[TMP5]] to i32
; CHECK-NEXT: [[S0_4:%.*]] = getelementptr i32, ptr [[PCMP]], i64 4
-; CHECK-NEXT: store i32 [[TMP10]], ptr [[S0_4]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[N]], 3
-; CHECK-NEXT: [[TMP12:%.*]] = sext i1 [[TMP11]] to i32
+; CHECK-NEXT: store i32 [[C0_4]], ptr [[S0_4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[N]], 3
+; CHECK-NEXT: [[C0_5:%.*]] = sext i1 [[TMP6]] to i32
; CHECK-NEXT: [[S0_5:%.*]] = getelementptr i32, ptr [[PCMP]], i64 5
-; CHECK-NEXT: store i32 [[TMP12]], ptr [[S0_5]], align 4
+; CHECK-NEXT: store i32 [[C0_5]], ptr [[S0_5]], align 4
; CHECK-NEXT: ret void
;
@@ -184,28 +184,28 @@ define void @fold_strncmp_a_c_n(ptr %pcmp, i64 %n) {
define void @fold_strncmp_a_d_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_strncmp_a_d_n(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[N:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[PCMP:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: [[C0_0:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: store i32 [[C0_0]], ptr [[PCMP:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C0_1:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S0_1]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[N]], 3
-; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[N]], 3
+; CHECK-NEXT: [[C1_1:%.*]] = zext i1 [[TMP3]] to i32
; CHECK-NEXT: [[S1_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[S1_1]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[N]], 2
-; CHECK-NEXT: [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
+; CHECK-NEXT: store i32 [[C1_1]], ptr [[S1_1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i64 [[N]], 2
+; CHECK-NEXT: [[C2_2:%.*]] = zext i1 [[TMP4]] to i32
; CHECK-NEXT: [[S2_2:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[S2_2]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP10:%.*]] = zext i1 [[TMP9]] to i32
+; CHECK-NEXT: store i32 [[C2_2]], ptr [[S2_2]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C4_4:%.*]] = zext i1 [[TMP5]] to i32
; CHECK-NEXT: [[S4_4:%.*]] = getelementptr i32, ptr [[PCMP]], i64 4
-; CHECK-NEXT: store i32 [[TMP10]], ptr [[S4_4]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP12:%.*]] = sext i1 [[TMP11]] to i32
+; CHECK-NEXT: store i32 [[C4_4]], ptr [[S4_4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C4_4_2:%.*]] = sext i1 [[TMP6]] to i32
; CHECK-NEXT: [[S4_4_2:%.*]] = getelementptr i32, ptr [[PCMP]], i64 5
-; CHECK-NEXT: store i32 [[TMP12]], ptr [[S4_4_2]], align 4
+; CHECK-NEXT: store i32 [[C4_4_2]], ptr [[S4_4_2]], align 4
; CHECK-NEXT: [[S5_5:%.*]] = getelementptr i32, ptr [[PCMP]], i64 6
; CHECK-NEXT: store i32 0, ptr [[S5_5]], align 4
; CHECK-NEXT: [[S6_6:%.*]] = getelementptr i32, ptr [[PCMP]], i64 7
@@ -300,13 +300,13 @@ define void @fold_strncmp_d_e_n(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_strncmp_d_e_n(
; CHECK-NEXT: store i32 0, ptr [[PCMP:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[N:%.*]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT: [[C0_1:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: [[S0_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[S0_1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[TMP3]] to i32
+; CHECK-NEXT: store i32 [[C0_1]], ptr [[S0_1]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[C1_0:%.*]] = sext i1 [[TMP2]] to i32
; CHECK-NEXT: [[S1_0:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[S1_0]], align 4
+; CHECK-NEXT: store i32 [[C1_0]], ptr [[S1_0]], align 4
; CHECK-NEXT: [[S1_1:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
; CHECK-NEXT: store i32 0, ptr [[S1_1]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/InstCombine/strncmp-6.ll b/llvm/test/Transforms/InstCombine/strncmp-6.ll
index 6d2eb9739229f..e4ab9e78583f4 100644
--- a/llvm/test/Transforms/InstCombine/strncmp-6.ll
+++ b/llvm/test/Transforms/InstCombine/strncmp-6.ll
@@ -59,20 +59,20 @@ define void @fold_strncmp_cst_cst(ptr %pcmp) {
define void @fold_strncmp_cst_var(ptr %pcmp, i64 %n) {
; CHECK-LABEL: @fold_strncmp_cst_var(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[N:%.*]], 6
-; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[PCMP:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[N]], 6
-; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT: [[CA0_B0:%.*]] = sext i1 [[TMP1]] to i32
+; CHECK-NEXT: store i32 [[CA0_B0]], ptr [[PCMP:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[N]], 6
+; CHECK-NEXT: [[CB0_A0:%.*]] = zext i1 [[TMP2]] to i32
; CHECK-NEXT: [[SB0_A0:%.*]] = getelementptr i32, ptr [[PCMP]], i64 1
-; CHECK-NEXT: store i32 [[TMP4]], ptr [[SB0_A0]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32
+; CHECK-NEXT: store i32 [[CB0_A0]], ptr [[SB0_A0]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[CA6_B6:%.*]] = sext i1 [[TMP3]] to i32
; CHECK-NEXT: [[SA6_B6:%.*]] = getelementptr i32, ptr [[PCMP]], i64 2
-; CHECK-NEXT: store i32 [[TMP6]], ptr [[SA6_B6]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[N]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
+; CHECK-NEXT: store i32 [[CA6_B6]], ptr [[SA6_B6]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[N]], 0
+; CHECK-NEXT: [[CB6_A6:%.*]] = zext i1 [[TMP4]] to i32
; CHECK-NEXT: [[SB6_A6:%.*]] = getelementptr i32, ptr [[PCMP]], i64 3
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[SB6_A6]], align 4
+; CHECK-NEXT: store i32 [[CB6_A6]], ptr [[SB6_A6]], align 4
; CHECK-NEXT: ret void
;
%p6 = getelementptr [7 x i8], ptr @a, i64 0, i64 6
diff --git a/llvm/test/Transforms/InstCombine/strnlen-1.ll b/llvm/test/Transforms/InstCombine/strnlen-1.ll
index d6b7ed9b1aa28..9cf4efe542eac 100644
--- a/llvm/test/Transforms/InstCombine/strnlen-1.ll
+++ b/llvm/test/Transforms/InstCombine/strnlen-1.ll
@@ -69,8 +69,8 @@ define i64 @fold_strnlen_ax_1() {
; CHECK-LABEL: @fold_strnlen_ax_1(
; CHECK-NEXT: [[STRNLEN_CHAR0:%.*]] = load i8, ptr @ax, align 1
; CHECK-NEXT: [[STRNLEN_CHAR0CMP:%.*]] = icmp ne i8 [[STRNLEN_CHAR0]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[STRNLEN_CHAR0CMP]] to i64
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[LEN:%.*]] = zext i1 [[STRNLEN_CHAR0CMP]] to i64
+; CHECK-NEXT: ret i64 [[LEN]]
;
%len = call i64 @strnlen(ptr @ax, i64 1)
ret i64 %len
diff --git a/llvm/test/Transforms/InstCombine/strnlen-3.ll b/llvm/test/Transforms/InstCombine/strnlen-3.ll
index 23748b8339d2f..f988f86fc15b3 100644
--- a/llvm/test/Transforms/InstCombine/strnlen-3.ll
+++ b/llvm/test/Transforms/InstCombine/strnlen-3.ll
@@ -125,8 +125,8 @@ define i64 @call_strnlen_s5_3_pi_n(i64 zeroext %i, i64 %n) {
define i64 @fold_strnlen_a3_n(i64 %n) {
; CHECK-LABEL: @fold_strnlen_a3_n(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umin.i64(i64 [[N:%.*]], i64 3)
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[LEN:%.*]] = call i64 @llvm.umin.i64(i64 [[N:%.*]], i64 3)
+; CHECK-NEXT: ret i64 [[LEN]]
;
%len = call i64 @strnlen(ptr @a3, i64 %n)
@@ -138,8 +138,8 @@ define i64 @fold_strnlen_a3_n(i64 %n) {
define i64 @fold_strnlen_s3_n(i64 %n) {
; CHECK-LABEL: @fold_strnlen_s3_n(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umin.i64(i64 [[N:%.*]], i64 3)
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[LEN:%.*]] = call i64 @llvm.umin.i64(i64 [[N:%.*]], i64 3)
+; CHECK-NEXT: ret i64 [[LEN]]
;
%len = call i64 @strnlen(ptr @s3, i64 %n)
diff --git a/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll b/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
index 5a3408dfdacfc..b075673e40ac3 100644
--- a/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
@@ -12,8 +12,8 @@
define i32 @clamp255_i32(i32 %x) {
; CHECK-LABEL: @clamp255_i32(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 255
+; CHECK-NEXT: [[OR:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[OR]], 255
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 255, %x
diff --git a/llvm/test/Transforms/InstCombine/sub-gep.ll b/llvm/test/Transforms/InstCombine/sub-gep.ll
index fed081c96d44d..015a8734a3675 100644
--- a/llvm/test/Transforms/InstCombine/sub-gep.ll
+++ b/llvm/test/Transforms/InstCombine/sub-gep.ll
@@ -66,8 +66,8 @@ define i64 @test_nuw(ptr %base, i64 %idx) {
define i32 @test_inbounds_nuw_trunc(ptr %base, i64 %idx) {
; CHECK-LABEL: @test_inbounds_nuw_trunc(
; CHECK-NEXT: [[IDX_TR:%.*]] = trunc i64 [[IDX:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[IDX_TR]], 2
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[D:%.*]] = shl i32 [[IDX_TR]], 2
+; CHECK-NEXT: ret i32 [[D]]
;
%p2 = getelementptr inbounds [0 x i32], ptr %base, i64 0, i64 %idx
%i1 = ptrtoint ptr %base to i64
@@ -173,8 +173,8 @@ define i64 @test_inbounds_nuw_multi_index(ptr %base, i64 %idx, i64 %idx2) {
; rdar://7362831
define i32 @test23(ptr %P, i64 %A){
; CHECK-LABEL: @test23(
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A:%.*]] to i32
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[G:%.*]] = trunc i64 [[A:%.*]] to i32
+; CHECK-NEXT: ret i32 [[G]]
;
%B = getelementptr inbounds i8, ptr %P, i64 %A
%C = ptrtoint ptr %B to i64
@@ -187,8 +187,8 @@ define i32 @test23(ptr %P, i64 %A){
define i8 @test23_as1(ptr addrspace(1) %P, i16 %A) {
; CHECK-LABEL: @test23_as1(
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i16 [[A:%.*]] to i8
-; CHECK-NEXT: ret i8 [[TMP1]]
+; CHECK-NEXT: [[G:%.*]] = trunc i16 [[A:%.*]] to i8
+; CHECK-NEXT: ret i8 [[G]]
;
%B = getelementptr inbounds i8, ptr addrspace(1) %P, i16 %A
%C = ptrtoint ptr addrspace(1) %B to i16
diff --git a/llvm/test/Transforms/InstCombine/sub-not.ll b/llvm/test/Transforms/InstCombine/sub-not.ll
index 690e7d6581d29..ec36754d3e9b1 100644
--- a/llvm/test/Transforms/InstCombine/sub-not.ll
+++ b/llvm/test/Transforms/InstCombine/sub-not.ll
@@ -75,8 +75,8 @@ define <2 x i8> @dec_sub_vec(<2 x i8> %x, <2 x i8> %y) {
define i8 @sub_inc(i8 %x, i8 %y) {
; CHECK-LABEL: @sub_inc(
-; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X:%.*]], -1
-; CHECK-NEXT: [[R:%.*]] = add i8 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[S_NEG:%.*]] = xor i8 [[X:%.*]], -1
+; CHECK-NEXT: [[R:%.*]] = add i8 [[S_NEG]], [[Y:%.*]]
; CHECK-NEXT: ret i8 [[R]]
;
%s = add i8 %x, 1
@@ -99,8 +99,8 @@ define i8 @sub_inc_extra_use(i8 %x, i8 %y) {
define <2 x i8> @sub_inc_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @sub_inc_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], <i8 -1, i8 -1>
-; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[S_NEG:%.*]] = xor <2 x i8> [[X:%.*]], <i8 -1, i8 -1>
+; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[S_NEG]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%s = add <2 x i8> %x, <i8 undef, i8 1>
diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
index 9dcdac2ae62fd..d56c19f52773d 100644
--- a/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
@@ -1296,8 +1296,8 @@ define i8 @negate_abs(i8 %x, i8 %y) {
; CHECK-LABEL: @negate_abs(
; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X]], i1 false)
-; CHECK-NEXT: [[T3:%.*]] = sub i8 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: [[T2:%.*]] = call i8 @llvm.abs.i8(i8 [[X]], i1 false)
+; CHECK-NEXT: [[T3:%.*]] = sub i8 [[Y:%.*]], [[T2]]
; CHECK-NEXT: ret i8 [[T3]]
;
%t0 = sub i8 0, %x
diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
index 89b22f1005e79..727dea404d84b 100644
--- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
+++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
@@ -1320,8 +1320,8 @@ define i8 @negate_abs(i8 %x, i8 %y) {
; CHECK-LABEL: @negate_abs(
; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X]], i1 false)
-; CHECK-NEXT: [[T3:%.*]] = sub i8 [[Y:%.*]], [[TMP1]]
+; CHECK-NEXT: [[T2:%.*]] = call i8 @llvm.abs.i8(i8 [[X]], i1 false)
+; CHECK-NEXT: [[T3:%.*]] = sub i8 [[Y:%.*]], [[T2]]
; CHECK-NEXT: ret i8 [[T3]]
;
%t0 = sub i8 0, %x
diff --git a/llvm/test/Transforms/InstCombine/subtract-from-one-hand-of-select.ll b/llvm/test/Transforms/InstCombine/subtract-from-one-hand-of-select.ll
index 0a80151ee642d..52d6706417c5f 100644
--- a/llvm/test/Transforms/InstCombine/subtract-from-one-hand-of-select.ll
+++ b/llvm/test/Transforms/InstCombine/subtract-from-one-hand-of-select.ll
@@ -13,7 +13,7 @@
define i8 @t0_sub_from_trueval(i1 %c, i8 %Op0, i8 %FalseVal) {
; CHECK-LABEL: @t0_sub_from_trueval(
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]], !prof !0
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]], !prof [[PROF0:![0-9]+]]
; CHECK-NEXT: ret i8 [[R]]
;
%o = select i1 %c, i8 %Op0, i8 %FalseVal, !prof !0 ; while there, ensure preservation of prof md
@@ -23,7 +23,7 @@ define i8 @t0_sub_from_trueval(i1 %c, i8 %Op0, i8 %FalseVal) {
define i8 @t1_sub_from_falseval(i1 %c, i8 %TrueVal, i8 %Op0) {
; CHECK-LABEL: @t1_sub_from_falseval(
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0, !prof !0
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0, !prof [[PROF0]]
; CHECK-NEXT: ret i8 [[R]]
;
%o = select i1 %c, i8 %TrueVal, i8 %Op0, !prof !0 ; while there, ensure preservation of prof md
diff --git a/llvm/test/Transforms/InstCombine/subtract-of-one-hand-of-select.ll b/llvm/test/Transforms/InstCombine/subtract-of-one-hand-of-select.ll
index 6efed5da76022..60fff1af648e5 100644
--- a/llvm/test/Transforms/InstCombine/subtract-of-one-hand-of-select.ll
+++ b/llvm/test/Transforms/InstCombine/subtract-of-one-hand-of-select.ll
@@ -13,7 +13,7 @@
define i8 @t0_sub_of_trueval(i1 %c, i8 %Op1, i8 %FalseVal) {
; CHECK-LABEL: @t0_sub_of_trueval(
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[FALSEVAL:%.*]], [[OP1:%.*]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]], !prof !0
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]], !prof [[PROF0:![0-9]+]]
; CHECK-NEXT: ret i8 [[R]]
;
%o = select i1 %c, i8 %Op1, i8 %FalseVal, !prof !0 ; while there, ensure preservation of prof md
@@ -23,7 +23,7 @@ define i8 @t0_sub_of_trueval(i1 %c, i8 %Op1, i8 %FalseVal) {
define i8 @t1_sub_of_falseval(i1 %c, i8 %TrueVal, i8 %Op1) {
; CHECK-LABEL: @t1_sub_of_falseval(
; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[TRUEVAL:%.*]], [[OP1:%.*]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0, !prof !0
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0, !prof [[PROF0]]
; CHECK-NEXT: ret i8 [[R]]
;
%o = select i1 %c, i8 %TrueVal, i8 %Op1, !prof !0 ; while there, ensure preservation of prof md
diff --git a/llvm/test/Transforms/InstCombine/switch-constant-expr.ll b/llvm/test/Transforms/InstCombine/switch-constant-expr.ll
index 9e7b5ea55003a..4116177103d26 100644
--- a/llvm/test/Transforms/InstCombine/switch-constant-expr.ll
+++ b/llvm/test/Transforms/InstCombine/switch-constant-expr.ll
@@ -6,7 +6,7 @@
; PR30486
define i32 @single_case() {
; CHECK-LABEL: @single_case(
-; CHECK-NEXT: switch i32 ptrtoint (ptr @g to i32), label %x [
+; CHECK-NEXT: switch i32 ptrtoint (ptr @g to i32), label [[X:%.*]] [
; CHECK-NEXT: ]
; CHECK: x:
; CHECK-NEXT: ret i32 0
@@ -18,9 +18,9 @@ x:
define i32 @multiple_cases() {
; CHECK-LABEL: @multiple_cases(
-; CHECK-NEXT: switch i32 ptrtoint (ptr @g to i32), label %x [
-; CHECK-NEXT: i32 2, label %one
-; CHECK-NEXT: i32 3, label %two
+; CHECK-NEXT: switch i32 ptrtoint (ptr @g to i32), label [[X:%.*]] [
+; CHECK-NEXT: i32 2, label [[ONE:%.*]]
+; CHECK-NEXT: i32 3, label [[TWO:%.*]]
; CHECK-NEXT: ]
; CHECK: x:
; CHECK-NEXT: ret i32 0
diff --git a/llvm/test/Transforms/InstCombine/trivial-dse-calls.ll b/llvm/test/Transforms/InstCombine/trivial-dse-calls.ll
index 731961e0ab2d3..1d54fe0827ce4 100644
--- a/llvm/test/Transforms/InstCombine/trivial-dse-calls.ll
+++ b/llvm/test/Transforms/InstCombine/trivial-dse-calls.ll
@@ -126,8 +126,8 @@ define i32 @test_neg_captured_by_call() {
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[A2:%.*]] = alloca ptr, align 8
; CHECK-NEXT: call void @f2(ptr nonnull writeonly [[A]], ptr nonnull [[A2]]) #[[ATTR3]]
-; CHECK-NEXT: [[A_COPY_CAST1:%.*]] = load ptr, ptr [[A2]], align 8
-; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[A_COPY_CAST1]], align 4
+; CHECK-NEXT: [[A_COPY_CAST:%.*]] = load ptr, ptr [[A2]], align 8
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[A_COPY_CAST]], align 4
; CHECK-NEXT: ret i32 [[RES]]
;
%a = alloca i32, align 4
diff --git a/llvm/test/Transforms/InstCombine/truncating-saturate.ll b/llvm/test/Transforms/InstCombine/truncating-saturate.ll
index 0f1697906d7f1..e4df94afd1741 100644
--- a/llvm/test/Transforms/InstCombine/truncating-saturate.ll
+++ b/llvm/test/Transforms/InstCombine/truncating-saturate.ll
@@ -10,8 +10,8 @@ define i8 @testi16i8(i16 %add) {
; CHECK-LABEL: @testi16i8(
; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ADD:%.*]], i16 -128)
; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i16 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[COND_I:%.*]] = trunc i16 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[COND_I]]
;
%sh = lshr i16 %add, 8
%conv.i = trunc i16 %sh to i8
@@ -29,8 +29,8 @@ define i32 @testi64i32(i64 %add) {
; CHECK-LABEL: @testi64i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD:%.*]], i64 -2147483648)
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP1]], i64 2147483647)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
-; CHECK-NEXT: ret i32 [[TMP3]]
+; CHECK-NEXT: [[COND_I:%.*]] = trunc i64 [[TMP2]] to i32
+; CHECK-NEXT: ret i32 [[COND_I]]
;
%sh = lshr i64 %add, 32
%conv.i = trunc i64 %sh to i32
@@ -48,8 +48,8 @@ define i16 @testi32i16i8(i32 %add) {
; CHECK-LABEL: @testi32i16i8(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD:%.*]], i32 -128)
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
-; CHECK-NEXT: ret i16 [[TMP3]]
+; CHECK-NEXT: [[R:%.*]] = trunc i32 [[TMP2]] to i16
+; CHECK-NEXT: ret i16 [[R]]
;
%a = add i32 %add, 128
%cmp = icmp ult i32 %a, 256
@@ -64,8 +64,8 @@ define <4 x i16> @testv4i32i16i8(<4 x i32> %add) {
; CHECK-LABEL: @testv4i32i16i8(
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[ADD:%.*]], <4 x i32> <i32 -128, i32 -128, i32 -128, i32 -128>)
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[TMP1]], <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>
-; CHECK-NEXT: ret <4 x i16> [[TMP3]]
+; CHECK-NEXT: [[R:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>
+; CHECK-NEXT: ret <4 x i16> [[R]]
;
%a = add <4 x i32> %add, <i32 128, i32 128, i32 128, i32 128>
%cmp = icmp ult <4 x i32> %a, <i32 256, i32 256, i32 256, i32 256>
@@ -79,8 +79,8 @@ define <4 x i16> @testv4i32i16i8(<4 x i32> %add) {
define i32 @testi32i32i8(i32 %add) {
; CHECK-LABEL: @testi32i32i8(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD:%.*]], i32 -128)
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
+; CHECK-NEXT: ret i32 [[R]]
;
%a = add i32 %add, 128
%cmp = icmp ult i32 %a, 256
@@ -94,8 +94,8 @@ define i16 @test_truncfirst(i32 %add) {
; CHECK-LABEL: @test_truncfirst(
; CHECK-NEXT: [[T:%.*]] = trunc i32 [[ADD:%.*]] to i16
; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[T]], i16 -128)
-; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
-; CHECK-NEXT: ret i16 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
+; CHECK-NEXT: ret i16 [[R]]
;
%t = trunc i32 %add to i16
%a = add i16 %t, 128
@@ -149,8 +149,8 @@ define <4 x i8> @testv4i16i8(<4 x i16> %add) {
; CHECK-LABEL: @testv4i16i8(
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[ADD:%.*]], <4 x i16> <i16 -128, i16 -128, i16 -128, i16 -128>)
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP1]], <4 x i16> <i16 127, i16 127, i16 127, i16 127>)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i16> [[TMP2]] to <4 x i8>
-; CHECK-NEXT: ret <4 x i8> [[TMP3]]
+; CHECK-NEXT: [[COND_I:%.*]] = trunc <4 x i16> [[TMP2]] to <4 x i8>
+; CHECK-NEXT: ret <4 x i8> [[COND_I]]
;
%sh = lshr <4 x i16> %add, <i16 8, i16 8, i16 8, i16 8>
%conv.i = trunc <4 x i16> %sh to <4 x i8>
@@ -188,8 +188,8 @@ define i8 @testi16i8_revcmp(i16 %add) {
; CHECK-LABEL: @testi16i8_revcmp(
; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ADD:%.*]], i16 -128)
; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i16 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[COND_I:%.*]] = trunc i16 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[COND_I]]
;
%sh = lshr i16 %add, 8
%conv.i = trunc i16 %sh to i8
@@ -207,8 +207,8 @@ define i8 @testi16i8_revselect(i16 %add) {
; CHECK-LABEL: @testi16i8_revselect(
; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ADD:%.*]], i16 -128)
; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i16 [[TMP2]] to i8
-; CHECK-NEXT: ret i8 [[TMP3]]
+; CHECK-NEXT: [[COND_I:%.*]] = trunc i16 [[TMP2]] to i8
+; CHECK-NEXT: ret i8 [[COND_I]]
;
%sh = lshr i16 %add, 8
%conv.i = trunc i16 %sh to i8
@@ -253,8 +253,8 @@ define i16 @
diff erentconsts(i32 %x, i16 %replacement_low, i16 %replacement_high)
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[X]] to i16
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i16 256, i16 [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i16 -1, i16 [[TMP4]]
-; CHECK-NEXT: ret i16 [[TMP5]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], i16 -1, i16 [[TMP4]]
+; CHECK-NEXT: ret i16 [[R]]
;
%t0 = icmp slt i32 %x, 128
%t1 = select i1 %t0, i16 256, i16 65535
@@ -342,8 +342,8 @@ define i8 @badimm4(i16 %add) {
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i16 [[ADD]], 127
; CHECK-NEXT: [[TMP3:%.*]] = trunc i16 [[ADD]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i8 -127, i8 [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i8 126, i8 [[TMP4]]
-; CHECK-NEXT: ret i8 [[TMP5]]
+; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[TMP2]], i8 126, i8 [[TMP4]]
+; CHECK-NEXT: ret i8 [[COND_I]]
;
%sh = lshr i16 %add, 8
%conv.i = trunc i16 %sh to i8
@@ -513,9 +513,9 @@ define i16 @
diff erentconsts_useadd(i32 %x, i16 %replacement_low, i16 %replacemen
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[X]] to i16
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], i16 256, i16 [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP2]], i16 -1, i16 [[TMP4]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP2]], i16 -1, i16 [[TMP4]]
; CHECK-NEXT: call void @use(i32 [[T2]])
-; CHECK-NEXT: ret i16 [[TMP5]]
+; CHECK-NEXT: ret i16 [[R]]
;
%t0 = icmp slt i32 %x, 128
%t1 = select i1 %t0, i16 256, i16 65535
diff --git a/llvm/test/Transforms/InstCombine/uadd-with-overflow.ll b/llvm/test/Transforms/InstCombine/uadd-with-overflow.ll
index 39e6db15f4a14..28d309baaa41d 100644
--- a/llvm/test/Transforms/InstCombine/uadd-with-overflow.ll
+++ b/llvm/test/Transforms/InstCombine/uadd-with-overflow.ll
@@ -11,8 +11,8 @@ declare { i8, i1 } @llvm.uadd.with.overflow.i8(i8, i8)
define { i32, i1 } @simple_fold(i32 %x) {
; CHECK-LABEL: @simple_fold(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[X:%.*]], i32 20)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[X:%.*]], i32 20)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = add nuw i32 %x, 7
%b = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 13)
@@ -21,8 +21,8 @@ define { i32, i1 } @simple_fold(i32 %x) {
define { i8, i1 } @fold_on_constant_add_no_overflow(i8 %x) {
; CHECK-LABEL: @fold_on_constant_add_no_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[X:%.*]], i8 -1)
-; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[X:%.*]], i8 -1)
+; CHECK-NEXT: ret { i8, i1 } [[B]]
;
%a = add nuw i8 %x, 200
%b = tail call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 %a, i8 55)
@@ -63,8 +63,8 @@ define { <2 x i8>, <2 x i1> } @no_fold_vector_overflow(<2 x i8> %x) {
define { <2 x i32>, <2 x i1> } @fold_simple_splat_constant(<2 x i32> %x) {
; CHECK-LABEL: @fold_simple_splat_constant(
-; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 42, i32 42>)
-; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 42, i32 42>)
+; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[B]]
;
%a = add nuw <2 x i32> %x, <i32 12, i32 12>
%b = tail call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> <i32 30, i32 30>)
@@ -95,8 +95,8 @@ define { <2 x i32>, <2 x i1> } @no_fold_splat_not_constant(<2 x i32> %x, <2 x i3
define { i32, i1 } @fold_nuwnsw(i32 %x) {
; CHECK-LABEL: @fold_nuwnsw(
-; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
-; CHECK-NEXT: ret { i32, i1 } [[TMP1]]
+; CHECK-NEXT: [[B:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[X:%.*]], i32 42)
+; CHECK-NEXT: ret { i32, i1 } [[B]]
;
%a = add nuw nsw i32 %x, 12
%b = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 30)
diff --git a/llvm/test/Transforms/InstCombine/uaddo.ll b/llvm/test/Transforms/InstCombine/uaddo.ll
index 01a6cc7bb9c2d..c638c0adef055 100644
--- a/llvm/test/Transforms/InstCombine/uaddo.ll
+++ b/llvm/test/Transforms/InstCombine/uaddo.ll
@@ -140,8 +140,8 @@ define i32 @uaddo_wrong_pred2(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @uaddo_wrong_pred2(
; CHECK-NEXT: [[NOTY:%.*]] = xor i32 [[Y:%.*]], -1
; CHECK-NEXT: [[A:%.*]] = add i32 [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[NOTY]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A]], i32 [[Z:%.*]]
+; CHECK-NEXT: [[C_NOT:%.*]] = icmp ugt i32 [[NOTY]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C_NOT]], i32 [[A]], i32 [[Z:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%noty = xor i32 %y, -1
diff --git a/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll b/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
index fa545122278d4..824ed4f2b4394 100644
--- a/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
+++ b/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
@@ -6,9 +6,9 @@
define i64 @test(i64 %X, i1 %Cond ) {
; CHECK-LABEL: @test(
-; CHECK-NEXT: [[QUOTIENT1:%.*]] = lshr i64 [[X:%.*]], 4
-; CHECK-NEXT: [[QUOTIENT2:%.*]] = lshr i64 [[X]], 3
-; CHECK-NEXT: [[SUM:%.*]] = add nuw nsw i64 [[QUOTIENT1]], [[QUOTIENT2]]
+; CHECK-NEXT: [[QUOTIENT11:%.*]] = lshr i64 [[X:%.*]], 4
+; CHECK-NEXT: [[QUOTIENT22:%.*]] = lshr i64 [[X]], 3
+; CHECK-NEXT: [[SUM:%.*]] = add nuw nsw i64 [[QUOTIENT11]], [[QUOTIENT22]]
; CHECK-NEXT: ret i64 [[SUM]]
;
%divisor1 = select i1 %Cond, i64 16, i64 8
diff --git a/llvm/test/Transforms/InstCombine/unordered-fcmp-select.ll b/llvm/test/Transforms/InstCombine/unordered-fcmp-select.ll
index fd3df3b17a567..62c12c15a075c 100644
--- a/llvm/test/Transforms/InstCombine/unordered-fcmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/unordered-fcmp-select.ll
@@ -2,10 +2,10 @@
; RUN: opt -S -passes=instcombine < %s | FileCheck %s
define float @select_max_ugt(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_max_ugt(
+; CHECK-LABEL: @select_max_ugt(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp arcp ole float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select arcp i1 [[CMP_INV]], float [[B]], float [[A]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select arcp i1 [[CMP_INV]], float [[B]], float [[A]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp arcp ugt float %a, %b
%sel = select arcp i1 %cmp, float %a, float %b
@@ -13,10 +13,10 @@ define float @select_max_ugt(float %a, float %b) {
}
define float @select_max_uge(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_max_uge(
+; CHECK-LABEL: @select_max_uge(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp nnan olt float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select nnan i1 [[CMP_INV]], float [[B]], float [[A]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select nnan i1 [[CMP_INV]], float [[B]], float [[A]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp nnan uge float %a, %b
%sel = select ninf i1 %cmp, float %a, float %b
@@ -24,9 +24,9 @@ define float @select_max_uge(float %a, float %b) {
}
define float @select_min_ugt(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_min_ugt(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-LABEL: @select_min_ugt(
+; CHECK-NEXT: [[SEL:%.*]] = call fast float @llvm.minnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp fast ugt float %a, %b
%sel = select reassoc i1 %cmp, float %b, float %a
@@ -34,10 +34,10 @@ define float @select_min_ugt(float %a, float %b) {
}
define float @select_min_uge(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_min_uge(
+; CHECK-LABEL: @select_min_uge(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp nsz olt float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select nsz i1 [[CMP_INV]], float [[A]], float [[B]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select nsz i1 [[CMP_INV]], float [[A]], float [[B]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp nsz uge float %a, %b
%sel = select fast i1 %cmp, float %b, float %a
@@ -45,10 +45,10 @@ define float @select_min_uge(float %a, float %b) {
}
define float @select_max_ult(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_max_ult(
+; CHECK-LABEL: @select_max_ult(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp arcp oge float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select arcp i1 [[CMP_INV]], float [[A]], float [[B]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select arcp i1 [[CMP_INV]], float [[A]], float [[B]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp arcp ult float %a, %b
%sel = select ninf nnan i1 %cmp, float %b, float %a
@@ -56,9 +56,9 @@ define float @select_max_ult(float %a, float %b) {
}
define float @select_max_ule(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_max_ule(
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-LABEL: @select_max_ule(
+; CHECK-NEXT: [[SEL:%.*]] = call fast float @llvm.maxnum.f32(float [[A:%.*]], float [[B:%.*]])
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp fast ule float %a, %b
%sel = select nsz i1 %cmp, float %b, float %a
@@ -66,10 +66,10 @@ define float @select_max_ule(float %a, float %b) {
}
define float @select_min_ult(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_min_ult(
+; CHECK-LABEL: @select_min_ult(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp nsz oge float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select nsz i1 [[CMP_INV]], float [[B]], float [[A]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select nsz i1 [[CMP_INV]], float [[B]], float [[A]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp nsz ult float %a, %b
%sel = select fast i1 %cmp, float %a, float %b
@@ -77,10 +77,10 @@ define float @select_min_ult(float %a, float %b) {
}
define float @select_min_ule(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_min_ule(
+; CHECK-LABEL: @select_min_ule(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp arcp ogt float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select arcp i1 [[CMP_INV]], float [[B]], float [[A]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select arcp i1 [[CMP_INV]], float [[B]], float [[A]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp arcp ule float %a, %b
%sel = select ninf i1 %cmp, float %a, float %b
@@ -88,10 +88,10 @@ define float @select_min_ule(float %a, float %b) {
}
define float @select_fcmp_une(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_fcmp_une(
+; CHECK-LABEL: @select_fcmp_une(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp reassoc oeq float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select reassoc i1 [[CMP_INV]], float [[B]], float [[A]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select reassoc i1 [[CMP_INV]], float [[B]], float [[A]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp reassoc une float %a, %b
%sel = select nnan i1 %cmp, float %a, float %b
@@ -99,10 +99,10 @@ define float @select_fcmp_une(float %a, float %b) {
}
define float @select_fcmp_ueq(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_fcmp_ueq(
+; CHECK-LABEL: @select_fcmp_ueq(
; CHECK-NEXT: [[CMP_INV:%.*]] = fcmp reassoc one float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = select reassoc i1 [[CMP_INV]], float [[B]], float [[A]]
-; CHECK-NEXT: ret float [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = select reassoc i1 [[CMP_INV]], float [[B]], float [[A]]
+; CHECK-NEXT: ret float [[SEL]]
;
%cmp = fcmp reassoc ueq float %a, %b
%sel = select arcp nnan i1 %cmp, float %a, float %b
@@ -112,7 +112,7 @@ define float @select_fcmp_ueq(float %a, float %b) {
declare void @foo(i1)
define float @select_max_ugt_2_use_cmp(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_max_ugt_2_use_cmp(
+; CHECK-LABEL: @select_max_ugt_2_use_cmp(
; CHECK-NEXT: [[CMP:%.*]] = fcmp reassoc ugt float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: call void @foo(i1 [[CMP]])
; CHECK-NEXT: [[SEL:%.*]] = select fast i1 [[CMP]], float [[A]], float [[B]]
@@ -125,7 +125,7 @@ define float @select_max_ugt_2_use_cmp(float %a, float %b) {
}
define float @select_min_uge_2_use_cmp(float %a, float %b) {
-; CHECK-LABEL: define {{[^@]+}}@select_min_uge_2_use_cmp(
+; CHECK-LABEL: @select_min_uge_2_use_cmp(
; CHECK-NEXT: [[CMP:%.*]] = fcmp ninf uge float [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: call void @foo(i1 [[CMP]])
; CHECK-NEXT: [[SEL:%.*]] = select nsz i1 [[CMP]], float [[B]], float [[A]]
diff --git a/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-mul-udiv.ll b/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-mul-udiv.ll
index 0c2bf404947a3..89e065033da19 100644
--- a/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-mul-udiv.ll
+++ b/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-mul-udiv.ll
@@ -8,10 +8,10 @@
define i1 @t0_basic(i8 %x, i8 %y) {
; CHECK-LABEL: @t0_basic(
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%t0 = mul i8 %x, %y
%t1 = udiv i8 %t0, %x
@@ -21,10 +21,10 @@ define i1 @t0_basic(i8 %x, i8 %y) {
define <2 x i1> @t1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @t1_vec(
-; CHECK-NEXT: [[UMUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor <2 x i1> [[UMUL_OV]], <i1 true, i1 true>
-; CHECK-NEXT: ret <2 x i1> [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor <2 x i1> [[MUL_OV]], <i1 true, i1 true>
+; CHECK-NEXT: ret <2 x i1> [[MUL_NOT_OV]]
;
%t0 = mul <2 x i8> %x, %y
%t1 = udiv <2 x i8> %t0, %x
@@ -37,10 +37,10 @@ declare i8 @gen8()
define i1 @t2_commutative(i8 %x) {
; CHECK-LABEL: @t2_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%y = call i8 @gen8()
%t0 = mul i8 %y, %x ; swapped
@@ -52,10 +52,10 @@ define i1 @t2_commutative(i8 %x) {
define i1 @t3_commutative(i8 %x) {
; CHECK-LABEL: @t3_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%y = call i8 @gen8()
%t0 = mul i8 %y, %x ; swapped
@@ -67,10 +67,10 @@ define i1 @t3_commutative(i8 %x) {
define i1 @t4_commutative(i8 %x) {
; CHECK-LABEL: @t4_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%y = call i8 @gen8()
%t0 = mul i8 %y, %x ; swapped
@@ -85,12 +85,12 @@ declare void @use8(i8)
define i1 @t5_extrause0(i8 %x, i8 %y) {
; CHECK-LABEL: @t5_extrause0(
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_VAL:%.*]] = extractvalue { i8, i1 } [[UMUL]], 0
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: call void @use8(i8 [[UMUL_VAL]])
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
+; CHECK-NEXT: [[MUL_VAL:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: call void @use8(i8 [[MUL_VAL]])
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%t0 = mul i8 %x, %y
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll b/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
index 103711b7a098a..1ffcfb4424e31 100644
--- a/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
+++ b/llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
@@ -8,10 +8,10 @@
define i1 @t0_basic(i8 %x, i8 %y) {
; CHECK-LABEL: @t0_basic(
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%t0 = udiv i8 -1, %x
%r = icmp uge i8 %t0, %y
@@ -20,10 +20,10 @@ define i1 @t0_basic(i8 %x, i8 %y) {
define <2 x i1> @t1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @t1_vec(
-; CHECK-NEXT: [[UMUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor <2 x i1> [[UMUL_OV]], <i1 true, i1 true>
-; CHECK-NEXT: ret <2 x i1> [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor <2 x i1> [[MUL_OV]], <i1 true, i1 true>
+; CHECK-NEXT: ret <2 x i1> [[MUL_NOT_OV]]
;
%t0 = udiv <2 x i8> <i8 -1, i8 -1>, %x
%r = icmp uge <2 x i8> %t0, %y
@@ -32,10 +32,10 @@ define <2 x i1> @t1_vec(<2 x i8> %x, <2 x i8> %y) {
define <3 x i1> @t2_vec_undef(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @t2_vec_undef(
-; CHECK-NEXT: [[UMUL:%.*]] = call { <3 x i8>, <3 x i1> } @llvm.umul.with.overflow.v3i8(<3 x i8> [[X:%.*]], <3 x i8> [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { <3 x i8>, <3 x i1> } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor <3 x i1> [[UMUL_OV]], <i1 true, i1 true, i1 true>
-; CHECK-NEXT: ret <3 x i1> [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { <3 x i8>, <3 x i1> } @llvm.umul.with.overflow.v3i8(<3 x i8> [[X:%.*]], <3 x i8> [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { <3 x i8>, <3 x i1> } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor <3 x i1> [[MUL_OV]], <i1 true, i1 true, i1 true>
+; CHECK-NEXT: ret <3 x i1> [[MUL_NOT_OV]]
;
%t0 = udiv <3 x i8> <i8 -1, i8 undef, i8 -1>, %x
%r = icmp uge <3 x i8> %t0, %y
@@ -47,10 +47,10 @@ declare i8 @gen8()
define i1 @t3_commutative(i8 %x) {
; CHECK-LABEL: @t3_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
-; CHECK-NEXT: ret i1 [[UMUL_NOT_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: [[MUL_NOT_OV:%.*]] = xor i1 [[MUL_OV]], true
+; CHECK-NEXT: ret i1 [[MUL_NOT_OV]]
;
%t0 = udiv i8 -1, %x
%y = call i8 @gen8()
diff --git a/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-mul-udiv.ll b/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-mul-udiv.ll
index 1d99067737b20..da4daca3b0e27 100644
--- a/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-mul-udiv.ll
+++ b/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-mul-udiv.ll
@@ -8,9 +8,9 @@
define i1 @t0_basic(i8 %x, i8 %y) {
; CHECK-LABEL: @t0_basic(
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%t0 = mul i8 %x, %y
%t1 = udiv i8 %t0, %x
@@ -20,9 +20,9 @@ define i1 @t0_basic(i8 %x, i8 %y) {
define <2 x i1> @t1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @t1_vec(
-; CHECK-NEXT: [[UMUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[UMUL]], 1
-; CHECK-NEXT: ret <2 x i1> [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[MUL]], 1
+; CHECK-NEXT: ret <2 x i1> [[MUL_OV]]
;
%t0 = mul <2 x i8> %x, %y
%t1 = udiv <2 x i8> %t0, %x
@@ -35,9 +35,9 @@ declare i8 @gen8()
define i1 @t2_commutative(i8 %x) {
; CHECK-LABEL: @t2_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%y = call i8 @gen8()
%t0 = mul i8 %y, %x ; swapped
@@ -49,9 +49,9 @@ define i1 @t2_commutative(i8 %x) {
define i1 @t3_commutative(i8 %x) {
; CHECK-LABEL: @t3_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%y = call i8 @gen8()
%t0 = mul i8 %y, %x ; swapped
@@ -63,9 +63,9 @@ define i1 @t3_commutative(i8 %x) {
define i1 @t4_commutative(i8 %x) {
; CHECK-LABEL: @t4_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%y = call i8 @gen8()
%t0 = mul i8 %y, %x ; swapped
@@ -80,11 +80,11 @@ declare void @use8(i8)
define i1 @t5_extrause0(i8 %x, i8 %y) {
; CHECK-LABEL: @t5_extrause0(
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_VAL:%.*]] = extractvalue { i8, i1 } [[UMUL]], 0
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: call void @use8(i8 [[UMUL_VAL]])
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
+; CHECK-NEXT: [[MUL_VAL:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: call void @use8(i8 [[MUL_VAL]])
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%t0 = mul i8 %x, %y
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll b/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
index eca94db5ffd47..710a09f6e16a1 100644
--- a/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
+++ b/llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
@@ -8,9 +8,9 @@
define i1 @t0_basic(i8 %x, i8 %y) {
; CHECK-LABEL: @t0_basic(
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%t0 = udiv i8 -1, %x
%r = icmp ult i8 %t0, %y
@@ -19,9 +19,9 @@ define i1 @t0_basic(i8 %x, i8 %y) {
define <2 x i1> @t1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @t1_vec(
-; CHECK-NEXT: [[UMUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[UMUL]], 1
-; CHECK-NEXT: ret <2 x i1> [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.umul.with.overflow.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[MUL]], 1
+; CHECK-NEXT: ret <2 x i1> [[MUL_OV]]
;
%t0 = udiv <2 x i8> <i8 -1, i8 -1>, %x
%r = icmp ult <2 x i8> %t0, %y
@@ -30,9 +30,9 @@ define <2 x i1> @t1_vec(<2 x i8> %x, <2 x i8> %y) {
define <3 x i1> @t2_vec_undef(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @t2_vec_undef(
-; CHECK-NEXT: [[UMUL:%.*]] = call { <3 x i8>, <3 x i1> } @llvm.umul.with.overflow.v3i8(<3 x i8> [[X:%.*]], <3 x i8> [[Y:%.*]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { <3 x i8>, <3 x i1> } [[UMUL]], 1
-; CHECK-NEXT: ret <3 x i1> [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { <3 x i8>, <3 x i1> } @llvm.umul.with.overflow.v3i8(<3 x i8> [[X:%.*]], <3 x i8> [[Y:%.*]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { <3 x i8>, <3 x i1> } [[MUL]], 1
+; CHECK-NEXT: ret <3 x i1> [[MUL_OV]]
;
%t0 = udiv <3 x i8> <i8 -1, i8 undef, i8 -1>, %x
%r = icmp ult <3 x i8> %t0, %y
@@ -44,9 +44,9 @@ declare i8 @gen8()
define i1 @t3_commutative(i8 %x) {
; CHECK-LABEL: @t3_commutative(
; CHECK-NEXT: [[Y:%.*]] = call i8 @gen8()
-; CHECK-NEXT: [[UMUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
-; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i8, i1 } [[UMUL]], 1
-; CHECK-NEXT: ret i1 [[UMUL_OV]]
+; CHECK-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X:%.*]], i8 [[Y]])
+; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
+; CHECK-NEXT: ret i1 [[MUL_OV]]
;
%t0 = udiv i8 -1, %x
%y = call i8 @gen8()
diff --git a/llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll b/llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
index 75b3c0d66a54d..5cece931b8d98 100644
--- a/llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
+++ b/llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
@@ -12,8 +12,8 @@ declare void @usei1(i1)
define i64 @max_sub_ugt(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_ugt(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ugt i64 %a, %b
%sub = sub i64 %a, %b
@@ -25,8 +25,8 @@ define i64 @max_sub_ugt(i64 %a, i64 %b) {
define i64 @max_sub_uge(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_uge(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp uge i64 %a, %b
%sub = sub i64 %a, %b
@@ -37,9 +37,9 @@ define i64 @max_sub_uge(i64 %a, i64 %b) {
define i64 @max_sub_uge_extrause1(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_uge_extrause1(
; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
; CHECK-NEXT: call void @use(i64 [[SUB]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp uge i64 %a, %b
%sub = sub i64 %a, %b
@@ -51,9 +51,9 @@ define i64 @max_sub_uge_extrause1(i64 %a, i64 %b) {
define i64 @max_sub_uge_extrause2(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_uge_extrause2(
; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
; CHECK-NEXT: call void @usei1(i1 [[CMP]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp uge i64 %a, %b
%sub = sub i64 %a, %b
@@ -66,10 +66,10 @@ define i64 @max_sub_uge_extrause3(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_uge_extrause3(
; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A]], [[B]]
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
; CHECK-NEXT: call void @use(i64 [[SUB]])
; CHECK-NEXT: call void @usei1(i1 [[CMP]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp uge i64 %a, %b
%sub = sub i64 %a, %b
@@ -84,8 +84,8 @@ define i64 @max_sub_uge_extrause3(i64 %a, i64 %b) {
define <4 x i32> @max_sub_ugt_vec(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @max_sub_ugt_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
+; CHECK-NEXT: ret <4 x i32> [[SEL]]
;
%cmp = icmp ugt <4 x i32> %a, %b
%sub = sub <4 x i32> %a, %b
@@ -98,10 +98,10 @@ define <4 x i32> @max_sub_ugt_vec(<4 x i32> %a, <4 x i32> %b) {
define i64 @max_sub_ult(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_ult(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
; CHECK-NEXT: [[EXTRASUB:%.*]] = sub i64 [[B]], [[A]]
; CHECK-NEXT: call void @use(i64 [[EXTRASUB]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ult i64 %b, %a
%sub = sub i64 %a, %b
@@ -115,10 +115,10 @@ define i64 @max_sub_ult(i64 %a, i64 %b) {
define i64 @max_sub_ugt_sel_swapped(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_ugt_sel_swapped(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
; CHECK-NEXT: [[EXTRASUB:%.*]] = sub i64 [[B]], [[A]]
; CHECK-NEXT: call void @use(i64 [[EXTRASUB]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ugt i64 %b, %a
%sub = sub i64 %a, %b
@@ -132,8 +132,8 @@ define i64 @max_sub_ugt_sel_swapped(i64 %a, i64 %b) {
define i64 @max_sub_ult_sel_swapped(i64 %a, i64 %b) {
; CHECK-LABEL: @max_sub_ult_sel_swapped(
-; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ult i64 %a, %b
%sub = sub i64 %a, %b
@@ -146,10 +146,10 @@ define i64 @max_sub_ult_sel_swapped(i64 %a, i64 %b) {
define i64 @neg_max_sub_ugt(i64 %a, i64 %b) {
; CHECK-LABEL: @neg_max_sub_ugt(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 0, [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = sub i64 0, [[TMP1]]
; CHECK-NEXT: [[EXTRASUB:%.*]] = sub i64 [[A]], [[B]]
; CHECK-NEXT: call void @use(i64 [[EXTRASUB]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ugt i64 %a, %b
%sub = sub i64 %b, %a
@@ -164,8 +164,8 @@ define i64 @neg_max_sub_ugt(i64 %a, i64 %b) {
define i64 @neg_max_sub_ult(i64 %a, i64 %b) {
; CHECK-LABEL: @neg_max_sub_ult(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 0, [[TMP1]]
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = sub i64 0, [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ult i64 %b, %a
%sub = sub i64 %b, %a
@@ -178,8 +178,8 @@ define i64 @neg_max_sub_ult(i64 %a, i64 %b) {
define i64 @neg_max_sub_ugt_sel_swapped(i64 %a, i64 %b) {
; CHECK-LABEL: @neg_max_sub_ugt_sel_swapped(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 0, [[TMP1]]
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = sub i64 0, [[TMP1]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ugt i64 %b, %a
%sub = sub i64 %b, %a
@@ -191,9 +191,9 @@ define i64 @neg_max_sub_ugt_sel_swapped_extrause1(i64 %a, i64 %b) {
; CHECK-LABEL: @neg_max_sub_ugt_sel_swapped_extrause1(
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[B:%.*]], [[A:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 0, [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = sub i64 0, [[TMP1]]
; CHECK-NEXT: call void @usei1(i1 [[CMP]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ugt i64 %b, %a
%sub = sub i64 %b, %a
@@ -206,9 +206,9 @@ define i64 @neg_max_sub_ugt_sel_swapped_extrause2(i64 %a, i64 %b) {
; CHECK-LABEL: @neg_max_sub_ugt_sel_swapped_extrause2(
; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 0, [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = sub i64 0, [[TMP1]]
; CHECK-NEXT: call void @use(i64 [[SUB]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ugt i64 %b, %a
%sub = sub i64 %b, %a
@@ -239,10 +239,10 @@ define i64 @neg_max_sub_ugt_sel_swapped_extrause3(i64 %a, i64 %b) {
define i64 @neg_max_sub_ult_sel_swapped(i64 %a, i64 %b) {
; CHECK-LABEL: @neg_max_sub_ult_sel_swapped(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A:%.*]], i64 [[B:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 0, [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = sub i64 0, [[TMP1]]
; CHECK-NEXT: [[EXTRASUB:%.*]] = sub i64 [[A]], [[B]]
; CHECK-NEXT: call void @use(i64 [[EXTRASUB]])
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: ret i64 [[SEL]]
;
%cmp = icmp ult i64 %a, %b
%sub = sub i64 %b, %a
@@ -254,8 +254,8 @@ define i64 @neg_max_sub_ult_sel_swapped(i64 %a, i64 %b) {
define i32 @max_sub_ugt_c1(i32 %a) {
; CHECK-LABEL: @max_sub_ugt_c1(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[A:%.*]], i32 1)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[A:%.*]], i32 1)
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp ugt i32 %a, 1
%sub = add i32 %a, -1
@@ -276,8 +276,8 @@ define i32 @max_sub_ugt_c01(i32 %a) {
define i32 @max_sub_ugt_c10(i32 %a) {
; CHECK-LABEL: @max_sub_ugt_c10(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[A:%.*]], i32 10)
-; CHECK-NEXT: ret i32 [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[A:%.*]], i32 10)
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp ugt i32 %a, 10
%sub = add i32 %a, -10
@@ -349,8 +349,8 @@ define i32 @max_sub_ult_c1(i32 %a) {
define i32 @max_sub_ult_c2(i32 %a) {
; CHECK-LABEL: @max_sub_ult_c2(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.usub.sat.i32(i32 2, i32 [[A:%.*]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[SEL:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp ult i32 %a, 2
%sub = add i32 %a, -2
@@ -362,9 +362,9 @@ define i32 @max_sub_ult_c2_oneuseicmp(i32 %a) {
; CHECK-LABEL: @max_sub_ult_c2_oneuseicmp(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[A:%.*]], 2
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.usub.sat.i32(i32 2, i32 [[A]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = sub nsw i32 0, [[TMP1]]
; CHECK-NEXT: call void @usei1(i1 [[CMP]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp ult i32 %a, 2
%sub = add i32 %a, -2
@@ -377,9 +377,9 @@ define i32 @max_sub_ult_c2_oneusesub(i32 %a) {
; CHECK-LABEL: @max_sub_ult_c2_oneusesub(
; CHECK-NEXT: [[SUB:%.*]] = add i32 [[A:%.*]], -2
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.usub.sat.i32(i32 2, i32 [[A]])
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT: [[SEL:%.*]] = sub nsw i32 0, [[TMP1]]
; CHECK-NEXT: call void @usei32(i32 [[SUB]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp = icmp ult i32 %a, 2
%sub = add i32 %a, -2
diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
index 8ed54fa298dd6..3a1ca6c8dd5ea 100644
--- a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
@@ -76,8 +76,8 @@ define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
define <2 x float> @test_fptrunc(double %f) {
; CHECK-LABEL: @test_fptrunc(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[F:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
-; CHECK-NEXT: ret <2 x float> [[TMP2]]
+; CHECK-NEXT: [[RET:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
+; CHECK-NEXT: ret <2 x float> [[RET]]
;
%t9 = insertelement <4 x double> poison, double %f, i32 0
%t10 = insertelement <4 x double> %t9, double 0.000000e+00, i32 1
@@ -91,8 +91,8 @@ define <2 x float> @test_fptrunc(double %f) {
define <2 x double> @test_fpext(float %f) {
; CHECK-LABEL: @test_fpext(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[F:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
-; CHECK-NEXT: ret <2 x double> [[TMP2]]
+; CHECK-NEXT: [[RET:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
+; CHECK-NEXT: ret <2 x double> [[RET]]
;
%t9 = insertelement <4 x float> poison, float %f, i32 0
%t10 = insertelement <4 x float> %t9, float 0.000000e+00, i32 1
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
index 3256d40bfac6e..0b2419e1158a8 100644
--- a/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
@@ -231,8 +231,8 @@ define <2 x i8> @test13a(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13a(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X2:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1
-; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5>
-; CHECK-NEXT: ret <2 x i8> [[TMP3]]
+; CHECK-NEXT: [[D:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5>
+; CHECK-NEXT: ret <2 x i8> [[D]]
;
%A = insertelement <2 x i8> poison, i8 %x1, i32 0
%B = insertelement <2 x i8> %A, i8 %x2, i32 1
@@ -280,8 +280,8 @@ define <3 x i32> @div_wider(i32 %y, i32 %z) {
define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) {
; CHECK-LABEL: @fold_inselts_with_widening_shuffle(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1
-; CHECK-NEXT: ret <3 x i8> [[TMP2]]
+; CHECK-NEXT: [[WIDEN:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1
+; CHECK-NEXT: ret <3 x i8> [[WIDEN]]
;
%ins0 = insertelement <2 x i8> poison, i8 %x, i32 0
%ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1
@@ -302,8 +302,8 @@ define <2 x i8> @test13b(i8 %x) {
define <2 x i8> @test13c(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13c(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1
-; CHECK-NEXT: ret <2 x i8> [[TMP2]]
+; CHECK-NEXT: [[C:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1
+; CHECK-NEXT: ret <2 x i8> [[C]]
;
%A = insertelement <4 x i8> poison, i8 %x1, i32 0
%B = insertelement <4 x i8> %A, i8 %x2, i32 2
diff --git a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
index 1bd2510f84be3..b2409e59777a8 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
@@ -53,8 +53,8 @@ define <2 x i1> @and_cmp_is_trunc_even_with_undef_elts(<2 x i64> %a) {
define <2 x i64> @test2(<2 x i64> %a) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i64> [[A:%.*]], <i64 1, i64 1>
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[B]], <i64 32767, i64 32767>
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[T:%.*]] = and <2 x i64> [[B]], <i64 32767, i64 32767>
+; CHECK-NEXT: ret <2 x i64> [[T]]
;
%b = and <2 x i64> %a, <i64 65535, i64 65535>
%t = ashr <2 x i64> %b, <i64 1, i64 1>
@@ -63,8 +63,8 @@ define <2 x i64> @test2(<2 x i64> %a) {
define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: [[AND1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32>
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[CONV]]
;
@@ -79,8 +79,8 @@ define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) {
define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: [[OR1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[OR1]] to <4 x i32>
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[OR]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[CONV]]
;
diff --git a/llvm/test/Transforms/InstCombine/vector-casts.ll b/llvm/test/Transforms/InstCombine/vector-casts.ll
index 44016939c9d70..877e20d3c2981 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -53,8 +53,8 @@ define <2 x i1> @and_cmp_is_trunc_even_with_undef_elts(<2 x i64> %a) {
define <2 x i64> @test2(<2 x i64> %a) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i64> [[A:%.*]], <i64 1, i64 1>
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[B]], <i64 32767, i64 32767>
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[T:%.*]] = and <2 x i64> [[B]], <i64 32767, i64 32767>
+; CHECK-NEXT: ret <2 x i64> [[T]]
;
%b = and <2 x i64> %a, <i64 65535, i64 65535>
%t = ashr <2 x i64> %b, <i64 1, i64 1>
@@ -63,8 +63,8 @@ define <2 x i64> @test2(<2 x i64> %a) {
define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: [[AND1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32>
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[CONV]]
;
@@ -79,8 +79,8 @@ define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) {
define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: [[OR1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[OR1]] to <4 x i32>
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[OR]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[CONV]]
;
diff --git a/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll b/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
index 2a8719ee6e5e2..9bb307ebf71e8 100644
--- a/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
+++ b/llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
@@ -4,8 +4,8 @@
define i1 @reduction_logical_or(<4 x i1> %x) {
; CHECK-LABEL: @reduction_logical_or(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i4 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)
ret i1 %r
@@ -14,8 +14,8 @@ define i1 @reduction_logical_or(<4 x i1> %x) {
define i1 @reduction_logical_and(<4 x i1> %x) {
; CHECK-LABEL: @reduction_logical_and(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i4 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%r = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)
ret i1 %r
diff --git a/llvm/test/Transforms/InstCombine/vector-reductions.ll b/llvm/test/Transforms/InstCombine/vector-reductions.ll
index b5422ee9b4827..2614ffd386952 100644
--- a/llvm/test/Transforms/InstCombine/vector-reductions.ll
+++ b/llvm/test/Transforms/InstCombine/vector-reductions.ll
@@ -89,8 +89,8 @@ define float @
diff _of_sums_type_mismatch(float %a0, <4 x float> %v0, float %a1,
define i32 @
diff _of_sums_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @
diff _of_sums_v4i32(
; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> [[V0:%.*]], [[V1:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
-; CHECK-NEXT: ret i32 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: ret i32 [[R]]
;
%r0 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v0)
%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v1)
diff --git a/llvm/test/Transforms/InstCombine/vector-xor.ll b/llvm/test/Transforms/InstCombine/vector-xor.ll
index 5dfabc942ed7f..171dd6e35b4e1 100644
--- a/llvm/test/Transforms/InstCombine/vector-xor.ll
+++ b/llvm/test/Transforms/InstCombine/vector-xor.ll
@@ -96,8 +96,8 @@ define <4 x i32> @test_v4i32_demorgan_or(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @test_v4i32_not_ashr_not(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @test_v4i32_not_ashr_not(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[DOTNOT:%.*]] = ashr <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[DOTNOT]]
;
%1 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
%2 = ashr <4 x i32> %1, %y
@@ -107,8 +107,8 @@ define <4 x i32> @test_v4i32_not_ashr_not(<4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @test_v4i32_not_ashr_not_undef(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @test_v4i32_not_ashr_not_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[DOTNOT:%.*]] = ashr <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[DOTNOT]]
;
%1 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 undef>, %x
%2 = ashr <4 x i32> %1, %y
diff --git a/llvm/test/Transforms/InstCombine/vscale_gep.ll b/llvm/test/Transforms/InstCombine/vscale_gep.ll
index 537c8cfc1f504..8bb4e2cb95ac9 100644
--- a/llvm/test/Transforms/InstCombine/vscale_gep.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_gep.ll
@@ -25,7 +25,7 @@ define ptr @gep_num_of_indices_1(ptr %p) {
define void @gep_bitcast(ptr %p) {
; CHECK-LABEL: @gep_bitcast(
; CHECK-NEXT: store <vscale x 16 x i8> zeroinitializer, ptr [[P:%.*]], align 16
-; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[P:%.*]], i64 1
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr <vscale x 16 x i8>, ptr [[P]], i64 1
; CHECK-NEXT: store <vscale x 16 x i8> zeroinitializer, ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstCombine/vscale_trunc.ll b/llvm/test/Transforms/InstCombine/vscale_trunc.ll
index 626917f75306b..e7e416eaf7818 100644
--- a/llvm/test/Transforms/InstCombine/vscale_trunc.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_trunc.ll
@@ -6,6 +6,7 @@ define i8 @vscale_trunc_i32toi8() vscale_range(1, 255) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
; CHECK-NEXT: ret i8 [[TMP0]]
+;
entry:
%0 = call i32 @llvm.vscale.i32()
%1 = trunc i32 %0 to i8
@@ -19,6 +20,7 @@ define i8 @vscale_trunc_i32toi8_poison() vscale_range(1, 256) {
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
; CHECK-NEXT: ret i8 [[TMP1]]
+;
entry:
%0 = call i32 @llvm.vscale.i32()
%1 = trunc i32 %0 to i8
@@ -31,6 +33,7 @@ define i8 @vscale_trunc_i32toi8_noAttr() {
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
; CHECK-NEXT: ret i8 [[TMP1]]
+;
entry:
%0 = call i32 @llvm.vscale.i32()
%1 = trunc i32 %0 to i8
diff --git a/llvm/test/Transforms/InstCombine/wcslen-3.ll b/llvm/test/Transforms/InstCombine/wcslen-3.ll
index 26252cd3bd885..c463b6b1e9526 100644
--- a/llvm/test/Transforms/InstCombine/wcslen-3.ll
+++ b/llvm/test/Transforms/InstCombine/wcslen-3.ll
@@ -97,8 +97,8 @@ define i1 @test_simplify8(ptr %str_p) {
define i64 @test_simplify9(i1 %x) {
; CHECK-LABEL: @test_simplify9(
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[X:%.*]], i64 5, i64 6
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[L:%.*]] = select i1 [[X:%.*]], i64 5, i64 6
+; CHECK-NEXT: ret i64 [[L]]
;
%s = select i1 %x, ptr @hello, ptr @longer
%l = call i64 @wcslen(ptr %s)
@@ -111,8 +111,8 @@ define i64 @test_simplify9(i1 %x) {
define i64 @test_simplify10(i16 %x) {
; CHECK-LABEL: @test_simplify10(
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i64 5, [[TMP1]]
-; CHECK-NEXT: ret i64 [[TMP2]]
+; CHECK-NEXT: [[HELLO_L:%.*]] = sub nsw i64 5, [[TMP1]]
+; CHECK-NEXT: ret i64 [[HELLO_L]]
;
%hello_p = getelementptr inbounds [6 x i16], ptr @hello, i16 0, i16 %x
%hello_l = call i64 @wcslen(ptr %hello_p)
@@ -125,8 +125,8 @@ define i64 @test_simplify11(i16 %x) {
; CHECK-LABEL: @test_simplify11(
; CHECK-NEXT: [[AND:%.*]] = and i16 [[X:%.*]], 7
; CHECK-NEXT: [[NARROW:%.*]] = sub nuw nsw i16 9, [[AND]]
-; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[NARROW]] to i64
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[HELLO_L:%.*]] = zext i16 [[NARROW]] to i64
+; CHECK-NEXT: ret i64 [[HELLO_L]]
;
%and = and i16 %x, 7
%hello_p = getelementptr inbounds [13 x i16], ptr @null_hello_mid, i16 0, i16 %and
diff --git a/llvm/test/Transforms/InstCombine/with_overflow.ll b/llvm/test/Transforms/InstCombine/with_overflow.ll
index 9b83197a8d764..4e3cb34931d07 100644
--- a/llvm/test/Transforms/InstCombine/with_overflow.ll
+++ b/llvm/test/Transforms/InstCombine/with_overflow.ll
@@ -535,9 +535,9 @@ define { i32, i1 } @umul_canonicalize_constant_arg0(i32 %x) nounwind {
define { i8, i1 } @uadd_always_overflow(i8 %x) nounwind {
; CHECK-LABEL: @uadd_always_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 63
-; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[TMP1]], 0
-; CHECK-NEXT: ret { i8, i1 } [[TMP2]]
+; CHECK-NEXT: [[A:%.*]] = and i8 [[X:%.*]], 63
+; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
+; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
;
%y = or i8 %x, 192
%a = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 %y, i8 64)
@@ -569,10 +569,10 @@ define { i8, i1 } @umul_always_overflow(i8 %x) nounwind {
define { i8, i1 } @sadd_always_overflow(i8 %x) nounwind {
; CHECK-LABEL: @sadd_always_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
-; CHECK-NEXT: [[A:%.*]] = add nuw i8 [[TMP1]], 28
-; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
-; CHECK-NEXT: ret { i8, i1 } [[TMP2]]
+; CHECK-NEXT: [[Y:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
+; CHECK-NEXT: [[A:%.*]] = add nuw i8 [[Y]], 28
+; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
+; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
;
%c = icmp sgt i8 %x, 100
%y = select i1 %c, i8 %x, i8 100
@@ -582,10 +582,10 @@ define { i8, i1 } @sadd_always_overflow(i8 %x) nounwind {
define { i8, i1 } @ssub_always_overflow(i8 %x) nounwind {
; CHECK-LABEL: @ssub_always_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 29)
-; CHECK-NEXT: [[A:%.*]] = sub nuw i8 -100, [[TMP1]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
-; CHECK-NEXT: ret { i8, i1 } [[TMP2]]
+; CHECK-NEXT: [[Y:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 29)
+; CHECK-NEXT: [[A:%.*]] = sub nuw i8 -100, [[Y]]
+; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
+; CHECK-NEXT: ret { i8, i1 } [[TMP1]]
;
%c = icmp sgt i8 %x, 29
%y = select i1 %c, i8 %x, i8 29
@@ -595,8 +595,8 @@ define { i8, i1 } @ssub_always_overflow(i8 %x) nounwind {
define { i8, i1 } @smul_always_overflow(i8 %x) nounwind {
; CHECK-LABEL: @smul_always_overflow(
-; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
-; CHECK-NEXT: [[A:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[TMP1]], i8 2)
+; CHECK-NEXT: [[Y:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
+; CHECK-NEXT: [[A:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[Y]], i8 2)
; CHECK-NEXT: ret { i8, i1 } [[A]]
;
%c = icmp sgt i8 %x, 100
diff --git a/llvm/test/Transforms/InstCombine/xor-and-or.ll b/llvm/test/Transforms/InstCombine/xor-and-or.ll
index c36d8775fd2c4..feba47912b1da 100644
--- a/llvm/test/Transforms/InstCombine/xor-and-or.ll
+++ b/llvm/test/Transforms/InstCombine/xor-and-or.ll
@@ -197,7 +197,7 @@ define <2 x i1> @xor_logic_and_or_vector_poison(<2 x i1> %c, <2 x i1> %x, <2 x i
ret <2 x i1> %r
}
-;; even through we save a instruction here, select is heavier than normal
+;; even through we save a instruction here, select is heavier than normal
;; and/or/xor on most backend, do we really need to do this transform?
define i1 @xor_and_or(i1 %c, i1 %x, i1 %y) {
; CHECK-LABEL: @xor_and_or(
@@ -211,7 +211,7 @@ define i1 @xor_and_or(i1 %c, i1 %x, i1 %y) {
ret i1 %r
}
-;; even though we save a instruction here, select is heavier than normal
+;; even though we save a instruction here, select is heavier than normal
;; and/or/xor on most backend, do we really need to do this transform?
define <4 x i1> @xor_and_or_vector(<4 x i1> %c, <4 x i1> %x, <4 x i1> %y) {
; CHECK-LABEL: @xor_and_or_vector(
diff --git a/llvm/test/Transforms/InstCombine/xor-icmps.ll b/llvm/test/Transforms/InstCombine/xor-icmps.ll
index d139d97d9d3c6..c85993ea9a7e0 100644
--- a/llvm/test/Transforms/InstCombine/xor-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/xor-icmps.ll
@@ -43,8 +43,8 @@ define i1 @eq_ne_zero(i4 %x, i4 %y) {
define i1 @slt_zero(i4 %x, i4 %y) {
; CHECK-LABEL: @slt_zero(
; CHECK-NEXT: [[TMP1:%.*]] = xor i4 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i4 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i4 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%i0 = icmp slt i4 %x, 0
%i1 = icmp slt i4 %y, 0
@@ -89,8 +89,8 @@ define i1 @sgt_zero(i4 %x, i4 %y) {
define i1 @sgt_minus1(i4 %x, i4 %y) {
; CHECK-LABEL: @sgt_minus1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i4 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i4 [[TMP1]], 0
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp slt i4 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[R]]
;
%i0 = icmp sgt i4 %x, -1
%i1 = icmp sgt i4 %y, -1
@@ -101,8 +101,8 @@ define i1 @sgt_minus1(i4 %x, i4 %y) {
define i1 @slt_zero_sgt_minus1(i4 %x, i4 %y) {
; CHECK-LABEL: @slt_zero_sgt_minus1(
; CHECK-NEXT: [[TMP1:%.*]] = xor i4 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i4 [[TMP1]], -1
-; CHECK-NEXT: ret i1 [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i4 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[R]]
;
%i0 = icmp slt i4 %x, 0
%i1 = icmp sgt i4 %y, -1
@@ -113,8 +113,8 @@ define i1 @slt_zero_sgt_minus1(i4 %x, i4 %y) {
define <2 x i1> @sgt_minus1_slt_zero_sgt(<2 x i4> %x, <2 x i4> %y) {
; CHECK-LABEL: @sgt_minus1_slt_zero_sgt(
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i4> [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i4> [[TMP1]], <i4 -1, i4 -1>
-; CHECK-NEXT: ret <2 x i1> [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i4> [[TMP1]], <i4 -1, i4 -1>
+; CHECK-NEXT: ret <2 x i1> [[R]]
;
%i1 = icmp sgt <2 x i4> %x, <i4 -1, i4 -1>
%i0 = icmp slt <2 x i4> %y, zeroinitializer
@@ -139,8 +139,8 @@ define i1 @
diff erent_type_cmp_ops(i32 %x, i64 %y) {
define i1 @test13(i8 %A, i8 %B) {
; CHECK-LABEL: @test13(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[E:%.*]] = icmp ne i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i1 [[E]]
;
%C = icmp ult i8 %A, %B
%D = icmp ugt i8 %A, %B
diff --git a/llvm/test/Transforms/InstCombine/xor-of-icmps-with-extra-uses.ll b/llvm/test/Transforms/InstCombine/xor-of-icmps-with-extra-uses.ll
index b2ba3100ae544..b4d92abe07893 100644
--- a/llvm/test/Transforms/InstCombine/xor-of-icmps-with-extra-uses.ll
+++ b/llvm/test/Transforms/InstCombine/xor-of-icmps-with-extra-uses.ll
@@ -10,9 +10,9 @@ define i1 @v0_select_of_consts(i32 %X, ptr %selected) {
; CHECK-NEXT: [[COND0_INV:%.*]] = icmp sgt i32 [[X:%.*]], 32767
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0_INV]], i32 32767, i32 -32768
; CHECK-NEXT: store i32 [[SELECT]], ptr [[SELECTED:%.*]], align 4
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X]], 32767
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 65535
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 32767
+; CHECK-NEXT: [[RES:%.*]] = icmp ult i32 [[TMP1]], 65535
+; CHECK-NEXT: ret i1 [[RES]]
;
%cond0 = icmp sgt i32 %X, 32767
%cond1 = icmp sgt i32 %X, -32768
@@ -26,9 +26,9 @@ define i1 @v1_select_of_var_and_const(i32 %X, i32 %Y, ptr %selected) {
; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[X:%.*]], 32768
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 -32768, i32 [[Y:%.*]]
; CHECK-NEXT: store i32 [[SELECT]], ptr [[SELECTED:%.*]], align 4
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X]], 32767
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 65535
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 32767
+; CHECK-NEXT: [[RES:%.*]] = icmp ult i32 [[TMP1]], 65535
+; CHECK-NEXT: ret i1 [[RES]]
;
%cond0 = icmp sgt i32 %X, 32767
%cond1 = icmp sgt i32 %X, -32768
@@ -42,9 +42,9 @@ define i1 @v2_select_of_const_and_var(i32 %X, i32 %Y, ptr %selected) {
; CHECK-NEXT: [[COND0_INV:%.*]] = icmp sgt i32 [[X:%.*]], 32767
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0_INV]], i32 32767, i32 [[Y:%.*]]
; CHECK-NEXT: store i32 [[SELECT]], ptr [[SELECTED:%.*]], align 4
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X]], 32767
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 65535
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 32767
+; CHECK-NEXT: [[RES:%.*]] = icmp ult i32 [[TMP1]], 65535
+; CHECK-NEXT: ret i1 [[RES]]
;
%cond0 = icmp sgt i32 %X, 32767
%cond1 = icmp sgt i32 %X, -32768
@@ -67,9 +67,9 @@ define i1 @v3_branch(i32 %X, ptr %dst0, ptr %dst1) {
; CHECK-NEXT: store i32 0, ptr [[DST1:%.*]], align 4
; CHECK-NEXT: br label [[END]]
; CHECK: end:
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X]], 32767
-; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X_OFF]], 65535
-; CHECK-NEXT: ret i1 [[TMP0]]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[X]], 32767
+; CHECK-NEXT: [[RES:%.*]] = icmp ult i32 [[TMP0]], 65535
+; CHECK-NEXT: ret i1 [[RES]]
;
begin:
%cond0 = icmp sgt i32 %X, 32767
@@ -91,9 +91,9 @@ define i1 @v4_not_store(i32 %X, ptr %not_cond) {
; CHECK-LABEL: @v4_not_store(
; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[X:%.*]], 32768
; CHECK-NEXT: store i1 [[COND0]], ptr [[NOT_COND:%.*]], align 1
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X]], 32767
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 65535
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 32767
+; CHECK-NEXT: [[RES:%.*]] = icmp ult i32 [[TMP1]], 65535
+; CHECK-NEXT: ret i1 [[RES]]
;
%cond0 = icmp sgt i32 %X, 32767
%not_cond0 = xor i1 %cond0, -1
@@ -111,9 +111,9 @@ define i1 @v5_select_and_not(i32 %X, i32 %Y, ptr %selected, ptr %not_cond) {
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 [[Y:%.*]], i32 32767
; CHECK-NEXT: store i1 [[COND0]], ptr [[NOT_COND:%.*]], align 1
; CHECK-NEXT: store i32 [[SELECT]], ptr [[SELECTED:%.*]], align 4
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X]], 32767
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 65535
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 32767
+; CHECK-NEXT: [[RES:%.*]] = icmp ult i32 [[TMP1]], 65535
+; CHECK-NEXT: ret i1 [[RES]]
;
%cond0 = icmp sgt i32 %X, 32767
%cond1 = icmp sgt i32 %X, -32768
diff --git a/llvm/test/Transforms/InstCombine/xor.ll b/llvm/test/Transforms/InstCombine/xor.ll
index a03b1a3b04503..479714fb478a8 100644
--- a/llvm/test/Transforms/InstCombine/xor.ll
+++ b/llvm/test/Transforms/InstCombine/xor.ll
@@ -1354,7 +1354,7 @@ define <2 x i8> @cttz_pow2(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @cttz_pow2(
; CHECK-NEXT: [[S:%.*]] = shl nuw <2 x i8> <i8 1, i8 1>, [[X:%.*]]
; CHECK-NEXT: [[D:%.*]] = udiv exact <2 x i8> [[S]], [[Y:%.*]]
-; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[D]], i1 true)
+; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[D]], i1 true), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%s = shl <2 x i8> <i8 1, i8 1>, %x
diff --git a/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll b/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll
index e64959a4a7835..1a8a59ee15c7b 100644
--- a/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll
+++ b/llvm/test/Transforms/InstCombine/zeroext-and-reduce.ll
@@ -3,7 +3,7 @@
define i32 @test1(i8 %X) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[TMP1:%.*]] = and i8 %X, 8
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 8
; CHECK-NEXT: [[Z:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[Z]]
;
diff --git a/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll b/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
index de47b22edb7cd..f082873bf7839 100644
--- a/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
+++ b/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
@@ -27,7 +27,7 @@ define i16 @trunc_ctlz_zext_i16_i32(i16 %x) {
define <2 x i8> @trunc_ctlz_zext_v2i8_v2i33(<2 x i8> %x) {
; CHECK-LABEL: @trunc_ctlz_zext_v2i8_v2i33(
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[X:%.*]], i1 true)
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw <2 x i8> [[TMP1]], <i8 25, i8 25>
; CHECK-NEXT: ret <2 x i8> [[ZZ]]
;
@@ -41,7 +41,7 @@ define <2 x i8> @trunc_ctlz_zext_v2i8_v2i33(<2 x i8> %x) {
define <vscale x 2 x i16> @trunc_ctlz_zext_nxv2i16_nxv2i64(<vscale x 2 x i16> %x) {
; CHECK-LABEL: @trunc_ctlz_zext_nxv2i16_nxv2i64(
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> [[X:%.*]], i1 false)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> [[X:%.*]], i1 false), !range [[RNG0]]
; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw <vscale x 2 x i16> [[TMP1]], shufflevector (<vscale x 2 x i16> insertelement (<vscale x 2 x i16> poison, i16 48, i64 0), <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: ret <vscale x 2 x i16> [[ZZ]]
;
@@ -56,7 +56,7 @@ define <vscale x 2 x i16> @trunc_ctlz_zext_nxv2i16_nxv2i64(<vscale x 2 x i16> %x
define <2 x i17> @trunc_ctlz_zext_v2i17_v2i32_multiple_uses(<2 x i17> %x) {
; CHECK-LABEL: @trunc_ctlz_zext_v2i17_v2i32_multiple_uses(
; CHECK-NEXT: [[Z:%.*]] = zext <2 x i17> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[P:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[Z]], i1 false)
+; CHECK-NEXT: [[P:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[Z]], i1 false), !range [[RNG2:![0-9]+]]
; CHECK-NEXT: [[ZZ:%.*]] = trunc <2 x i32> [[P]] to <2 x i17>
; CHECK-NEXT: call void @use(<2 x i32> [[P]])
; CHECK-NEXT: ret <2 x i17> [[ZZ]]
@@ -73,7 +73,7 @@ define <2 x i17> @trunc_ctlz_zext_v2i17_v2i32_multiple_uses(<2 x i17> %x) {
define <vscale x 2 x i16> @trunc_ctlz_zext_nxv2i16_nxv2i63_multiple_uses(<vscale x 2 x i16> %x) {
; CHECK-LABEL: @trunc_ctlz_zext_nxv2i16_nxv2i63_multiple_uses(
; CHECK-NEXT: [[Z:%.*]] = zext <vscale x 2 x i16> [[X:%.*]] to <vscale x 2 x i63>
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> [[X]], i1 true)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.ctlz.nxv2i16(<vscale x 2 x i16> [[X]], i1 true), !range [[RNG0]]
; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw <vscale x 2 x i16> [[TMP1]], shufflevector (<vscale x 2 x i16> insertelement (<vscale x 2 x i16> poison, i16 47, i64 0), <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: call void @use1(<vscale x 2 x i63> [[Z]])
; CHECK-NEXT: ret <vscale x 2 x i16> [[ZZ]]
@@ -90,7 +90,7 @@ define <vscale x 2 x i16> @trunc_ctlz_zext_nxv2i16_nxv2i63_multiple_uses(<vscale
define i16 @trunc_ctlz_zext_i10_i32(i10 %x) {
; CHECK-LABEL: @trunc_ctlz_zext_i10_i32(
; CHECK-NEXT: [[Z:%.*]] = zext i10 [[X:%.*]] to i32
-; CHECK-NEXT: [[P:%.*]] = call i32 @llvm.ctlz.i32(i32 [[Z]], i1 false), !range [[RNG1:![0-9]+]]
+; CHECK-NEXT: [[P:%.*]] = call i32 @llvm.ctlz.i32(i32 [[Z]], i1 false), !range [[RNG3:![0-9]+]]
; CHECK-NEXT: [[ZZ:%.*]] = trunc i32 [[P]] to i16
; CHECK-NEXT: ret i16 [[ZZ]]
;
@@ -108,7 +108,7 @@ define i16 @trunc_ctlz_zext_i10_i32(i10 %x) {
define i3 @trunc_ctlz_zext_i3_i34(i3 %x) {
; CHECK-LABEL: @trunc_ctlz_zext_i3_i34(
; CHECK-NEXT: [[Z:%.*]] = zext i3 [[X:%.*]] to i34
-; CHECK-NEXT: [[P:%.*]] = call i34 @llvm.ctlz.i34(i34 [[Z]], i1 false), !range [[RNG2:![0-9]+]]
+; CHECK-NEXT: [[P:%.*]] = call i34 @llvm.ctlz.i34(i34 [[Z]], i1 false), !range [[RNG4:![0-9]+]]
; CHECK-NEXT: [[T:%.*]] = trunc i34 [[P]] to i3
; CHECK-NEXT: ret i3 [[T]]
;
diff --git a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
index 45b90900f83bf..05759b2ca6db9 100644
--- a/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/zext-or-icmp.ll
@@ -123,8 +123,8 @@ block2:
define i32 @zext_or_eq_ult_add(i32 %i) {
; CHECK-LABEL: @zext_or_eq_ult_add(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -3
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
-; CHECK-NEXT: [[R:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: [[O:%.*]] = icmp ult i32 [[TMP1]], 3
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[O]] to i32
; CHECK-NEXT: ret i32 [[R]]
;
%a = add i32 %i, -3
@@ -138,8 +138,8 @@ define i32 @zext_or_eq_ult_add(i32 %i) {
define i32 @select_zext_or_eq_ult_add(i32 %i) {
; CHECK-LABEL: @select_zext_or_eq_ult_add(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -3
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
-; CHECK-NEXT: [[R:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT: [[NARROW:%.*]] = icmp ult i32 [[TMP1]], 3
+; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32
; CHECK-NEXT: ret i32 [[R]]
;
%a = add i32 %i, -3
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