[PATCH] D147538: [RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM with that comment addressed.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9113
   SDValue N1 = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
----------------
Move `VT` and `DL` inside the ifs since they aren't used until getNode.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147538/new/

https://reviews.llvm.org/D147538