[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11369
+      for (SDValue Op : N->ops().drop_front()) {
+        auto *Ld = dyn_cast<LoadSDNode>(Op);
+        if (!Ld || !Ld->isSimple() || !Op.hasOneUse())
----------------
We need all the input loads to have the same chain input


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11438
+            BaseLd->getMemOperand(), 0, WideVecVT.getStoreSize()));
+    DAG.makeEquivalentMemoryOrdering(BaseLd, StridedLoad);
+    return DAG.getBitcast(
----------------
We have to call makeEquivalentMemoryOrdering for all of the loads that were combined.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713