[llvm] 846712b - [DAG] combineSelect - select(i1,vXi1,vXi1) - only cast <X x i1> constants to iX pre-legalization or if its a legal type
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 6 05:35:58 PDT 2023
Author: Simon Pilgrim
Date: 2023-04-06T13:35:45+01:00
New Revision: 846712b0cb133f0ebfaf5be41818183b4c86f0a1
URL: https://github.com/llvm/llvm-project/commit/846712b0cb133f0ebfaf5be41818183b4c86f0a1
DIFF: https://github.com/llvm/llvm-project/commit/846712b0cb133f0ebfaf5be41818183b4c86f0a1.diff
LOG: [DAG] combineSelect - select(i1,vXi1,vXi1) - only cast <X x i1> constants to iX pre-legalization or if its a legal type
Fixes #61524
Added:
llvm/test/CodeGen/X86/pr61524.ll
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dc07a034b189..88495d8f7fbe 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -46812,27 +46812,27 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
VT.getVectorElementType() == MVT::i1 &&
(DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) {
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getVectorNumElements());
- bool LHSIsConst = ISD::isBuildVectorOfConstantSDNodes(LHS.getNode());
- bool RHSIsConst = ISD::isBuildVectorOfConstantSDNodes(RHS.getNode());
-
- if ((LHSIsConst ||
- (LHS.getOpcode() == ISD::BITCAST &&
- LHS.getOperand(0).getValueType() == IntVT)) &&
- (RHSIsConst ||
- (RHS.getOpcode() == ISD::BITCAST &&
- RHS.getOperand(0).getValueType() == IntVT))) {
- if (LHSIsConst)
- LHS = combinevXi1ConstantToInteger(LHS, DAG);
- else
- LHS = LHS.getOperand(0);
+ if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) {
+ bool LHSIsConst = ISD::isBuildVectorOfConstantSDNodes(LHS.getNode());
+ bool RHSIsConst = ISD::isBuildVectorOfConstantSDNodes(RHS.getNode());
+
+ if ((LHSIsConst || (LHS.getOpcode() == ISD::BITCAST &&
+ LHS.getOperand(0).getValueType() == IntVT)) &&
+ (RHSIsConst || (RHS.getOpcode() == ISD::BITCAST &&
+ RHS.getOperand(0).getValueType() == IntVT))) {
+ if (LHSIsConst)
+ LHS = combinevXi1ConstantToInteger(LHS, DAG);
+ else
+ LHS = LHS.getOperand(0);
- if (RHSIsConst)
- RHS = combinevXi1ConstantToInteger(RHS, DAG);
- else
- RHS = RHS.getOperand(0);
+ if (RHSIsConst)
+ RHS = combinevXi1ConstantToInteger(RHS, DAG);
+ else
+ RHS = RHS.getOperand(0);
- SDValue Select = DAG.getSelect(DL, IntVT, Cond, LHS, RHS);
- return DAG.getBitcast(VT, Select);
+ SDValue Select = DAG.getSelect(DL, IntVT, Cond, LHS, RHS);
+ return DAG.getBitcast(VT, Select);
+ }
}
}
diff --git a/llvm/test/CodeGen/X86/pr61524.ll b/llvm/test/CodeGen/X86/pr61524.ll
new file mode 100644
index 000000000000..0f4ccd6498fe
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr61524.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s --mtriple=x86_64-- -mcpu=cascadelake | FileCheck %s
+
+define <3 x i1> @repro(i1 %cond) {
+; CHECK-LABEL: repro:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: jne .LBB0_1
+; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: kxorw %k0, %k0, %k0
+; CHECK-NEXT: jmp .LBB0_3
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: kxnorw %k0, %k0, %k0
+; CHECK-NEXT: .LBB0_3:
+; CHECK-NEXT: kshiftrb $1, %k0, %k1
+; CHECK-NEXT: kmovd %k1, %edx
+; CHECK-NEXT: kshiftrb $2, %k0, %k1
+; CHECK-NEXT: kmovd %k1, %ecx
+; CHECK-NEXT: kmovd %k0, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: # kill: def $dl killed $dl killed $edx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: retq
+ %select = select i1 %cond, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> zeroinitializer
+ ret <3 x i1> %select
+}
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