[PATCH] D145163: Add support for vectorization of interleaved memory accesses for scalable VF

[Graham Hunter via Phabricator via llvm-commits]

huntergr added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:125-127
+    "enable-sve-interleaved-mem-accesses", cl::init(false), cl::Hidden,
+    cl::desc("Enable vectorization on interleaved memory accesses in a loop "
+             "using sve load/store."));
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mgabka wrote:
> Hi @huntergr ,
> Thanks for your changes to this patch!
> 
> I have one question, the interface you proposed looks clean and nice, however it forces code generation for the deinterleaving/interleaving intrinsics to be implemented before merging this patch, am I correct?
> 
> The reason why I had this option here is that it would allow us to merge this patch before other pieces are implemented.
Hi @mgabka ,

We do have code generation for these intrinsics already, they just get lowered to zips/uzips. See D141924.

D146218 will match to ld2/st2 where possible (which is what we want), and should perhaps land first. The changes to isLegalInterleavedAccessType will also be needed there, so the next version of this patch can just rely on that.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145163/new/

https://reviews.llvm.org/D145163