[PATCH] D147643: [SelectionDAG] Expand VP SDNodes by default.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 5 18:52:42 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf1924d965abb: [SelectionDAG] Expand VP SDNodes by default. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147643/new/
https://reviews.llvm.org/D147643
Files:
llvm/lib/CodeGen/TargetLoweringBase.cpp
Index: llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -875,10 +875,10 @@
// Named vector shuffles default to expand.
setOperationAction(ISD::VECTOR_SPLICE, VT, Expand);
- // VP_SREM/UREM default to expand.
- // TODO: Expand all VP intrinsics.
- setOperationAction(ISD::VP_SREM, VT, Expand);
- setOperationAction(ISD::VP_UREM, VT, Expand);
+ // VP operations default to expand.
+#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
+ setOperationAction(ISD::SDOPC, VT, Expand);
+#include "llvm/IR/VPIntrinsics.def"
}
// Most targets ignore the @llvm.prefetch intrinsic.
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