[llvm] f1924d9 - [SelectionDAG] Expand VP SDNodes by default.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-04-05T18:52:28-07:00
New Revision: f1924d965abb043075fe000ebb7d8ca428fda137

URL: https://github.com/llvm/llvm-project/commit/f1924d965abb043075fe000ebb7d8ca428fda137
DIFF: https://github.com/llvm/llvm-project/commit/f1924d965abb043075fe000ebb7d8ca428fda137.diff

LOG: [SelectionDAG] Expand VP SDNodes by default.

Differential Revision: https://reviews.llvm.org/D147643

Added: 
    

Modified: 
    llvm/lib/CodeGen/TargetLoweringBase.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index ac27168879c6..6d006ff6081b 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -875,10 +875,10 @@ void TargetLoweringBase::initActions() {
     // Named vector shuffles default to expand.
     setOperationAction(ISD::VECTOR_SPLICE, VT, Expand);
 
-    // VP_SREM/UREM default to expand.
-    // TODO: Expand all VP intrinsics.
-    setOperationAction(ISD::VP_SREM, VT, Expand);
-    setOperationAction(ISD::VP_UREM, VT, Expand);
+    // VP operations default to expand.
+#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...)                                   \
+    setOperationAction(ISD::SDOPC, VT, Expand);
+#include "llvm/IR/VPIntrinsics.def"
   }
 
   // Most targets ignore the @llvm.prefetch intrinsic.