[PATCH] D147538: [RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9030
+  // fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
+  // fold (sub 0, (setcc 0, x, setgt)) -> (sra x , xlen - 1)
+  if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
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You can delete the setgt code. It will never exist in that form. Prior to LegalizeDAG we keep constants on the RHS of setcc. LegalizeDAG won't have any reason to change it.

The only case that should have 0 on the left hand side is (setcc 0, x, setlt) which we get from legalizing (setcc x, 0, setgt).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147538/new/

https://reviews.llvm.org/D147538