[PATCH] D147617: [AArch64][SME] Fix LDR and STR asm parser

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
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The LDR and STR instructions must have the same value for imm4(second operand)
and offset(fourth operand).
The disassembly guarantees that happens, but the Asm parser was not checking that.
This patch fixes that by checking if the second operand and fourth operand are
immediate and have the same value.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147617

Files:
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/SME/ldr-diagnostics.s


Index: llvm/test/MC/AArch64/SME/ldr-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ldr-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ldr-diagnostics.s
@@ -51,3 +51,10 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ldr za[w12, #0], [x0, #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Mismatch between offset and immediate
+ldr     za[w14, 6], [x10, #5, mul vl]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, immediate and offset mismatch.
+// CHECK-NEXT: ldr     za[w14, 6], [x10, #5, mul vl]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -5304,6 +5304,14 @@
                            "is also a destination");
     [[fallthrough]];
   }
+  case AArch64::LDR_ZA:
+  case AArch64::STR_ZA: {
+    if (Inst.getOperand(2).isImm() && Inst.getOperand(4).isImm() &&
+        Inst.getOperand(2).getImm() != Inst.getOperand(4).getImm())
+      return Error(Loc[1],
+                   "unpredictable instruction, immediate and offset mismatch.");
+    break;
+  }
   case AArch64::LDPDi:
   case AArch64::LDPQi:
   case AArch64::LDPSi:


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