[PATCH] D147608: [RISCV] Lower scalar_to_vector

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll:15
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    vlse64.v v8, (a0), zero
 ; RV64-NEXT:    ret
----------------
What's the ideal emitted load here?

A single wide element load i.e. `vle64.v v8, (a0)`?
Or multiple lanes with a more precise vl:
```
vsetivil zero, 5, e8, mf2, ta, ma
vle8.v v8, (a0)
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D147608/new/

https://reviews.llvm.org/D147608