[PATCH] D146735: [CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/CodeGen/RegisterClassInfo.cpp:97
   for (const MCPhysReg *I = CSR; *I; ++I)
-    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
-      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
+    CSRHintsForAllocOrder[*I] = STI.ignoreCSRForAllocationOrder(mf, *I);
   if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
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qcolombet wrote:
> Given the only spot where `::ignoreCSRForAllocationOrder` is used is guarded by CalleeSavedAliases and that one is populated with regunits (after your other change), I think we should go through the regunits too here.
How about this brute force approach, calling ignoreCSRForAllocationOrder on every physical register? This is the simplest fastest thing I could come up with for AMDGPU, where ignoreCSRForAllocationOrder is just a virtual call to default implementation that returns false.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146735/new/

https://reviews.llvm.org/D146735