[PATCH] D147518: [DAGCombiner] Fix (shl (ctlz x) n) for non-power-of-two Data

[Sam Elliott via Phabricator via llvm-commits]

lenary edited the summary of this revision.
lenary updated this revision to Diff 511050.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147518/new/

https://reviews.llvm.org/D147518

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/pr61549.ll


Index: llvm/test/CodeGen/AArch64/pr61549.ll
===================================================================
--- llvm/test/CodeGen/AArch64/pr61549.ll
+++ llvm/test/CodeGen/AArch64/pr61549.ll
@@ -9,7 +9,9 @@
 ; CHECK-NEXT:    sbfx x9, x0, #0, #35
 ; CHECK-NEXT:    sdiv x10, x8, x9
 ; CHECK-NEXT:    msub x8, x10, x9, x8
-; CHECK-NEXT:    eor x0, x8, #0x1
+; CHECK-NEXT:    clz x8, x8
+; CHECK-NEXT:    sub x8, x8, #29
+; CHECK-NEXT:    ubfx x0, x8, #5, #30
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: f:
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10308,8 +10308,10 @@
       return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
   }
 
-  // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit).
+  // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit), and x has a power
+  // of two bitwidth. The "5" represents (log2 (bitwidth x)).
   if (N1C && N0.getOpcode() == ISD::CTLZ &&
+      isPowerOf2_32(OpSizeInBits) &&
       N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
     KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D147518.511050.patch
Type: text/x-patch
Size: 1263 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230405/52f7e862/attachment.bin>