[llvm] 215f36f - [gn build] Port 443825c517c8

[Nico Weber via llvm-commits]

Author: Nico Weber
Date: 2023-04-04T21:27:47-04:00
New Revision: 215f36f7917d87f81eeeee0de8ec55d11d83a164

URL: https://github.com/llvm/llvm-project/commit/215f36f7917d87f81eeeee0de8ec55d11d83a164
DIFF: https://github.com/llvm/llvm-project/commit/215f36f7917d87f81eeeee0de8ec55d11d83a164.diff

LOG: [gn build] Port 443825c517c8

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn
index 33342e5d01c7c..af2c6d38d9519 100644
--- a/llvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn
@@ -3,17 +3,23 @@ import("//third-party/unittest/unittest.gni")
 unittest("X86Tests") {
   deps = [
     "//llvm/lib/Analysis",
+    "//llvm/lib/AsmParser",
     "//llvm/lib/CodeGen",
     "//llvm/lib/CodeGen/MIRParser",
     "//llvm/lib/IR",
     "//llvm/lib/MC",
+    "//llvm/lib/Passes",
     "//llvm/lib/Support",
     "//llvm/lib/Target",
     "//llvm/lib/Target/X86:LLVMX86CodeGen",
     "//llvm/lib/Target/X86/MCTargetDesc",
     "//llvm/lib/Target/X86/TargetInfo",
     "//llvm/lib/TargetParser",
+    "//llvm/lib/Transforms/InstCombine",
   ]
   include_dirs = [ "//llvm/lib/Target/X86" ]
-  sources = [ "MachineSizeOptsTest.cpp" ]
+  sources = [
+    "MachineSizeOptsTest.cpp",
+    "TernlogTest.cpp",
+  ]
 }