[PATCH] D147470: [RISCV] Account for LMUL in memory op costs

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll:34
+; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i32, ptr [[P:%.*]], <vscale x 4 x i64> [[TMP12]]
+; CHECK-NEXT:    [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> [[TMP13]], i32 4, <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i32> poison)
+; CHECK-NEXT:    [[TMP14:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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luke wrote:
> Does the gather/scatter lowering pass kick in and transform these to `vlse32`s?
Yes


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D147470/new/

https://reviews.llvm.org/D147470