[PATCH] D147547: [AMDGPU] Add buffer intrinsics that take resources as pointers

Krzysztof Drewniak via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 4 10:21:28 PDT 2023 

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In order to enable the LLVM frontend to better analyze buffer
operations (and to potentially enable more precise analyses on the
backend), define versions of the raw and structured buffer intrinsics
that use `ptr addrspace(8)` instead of `<4 x i32>` to represent their
rsrc arguments.

The new intrinsics are named by replacing `buffer.` with `buffer.ptr`.

One advantage to these intrinsic definitions is that, instead of
specifying that a buffer load/store will read/write some memory, we
can indicate that the memory read or written will be based on the
pointer argument. This means that, for example, a read from a
`noalias` buffer can be pulled out of a loop that is modifying a
distinct buffer.

In the future, we will define custom PseudoSourceValues that will
allow us to package up the (buffer, index, offset) triples that buffer
intrinsics contain and allow for more precise backend analysis.

This work also enables creating address space 7, which represents
manipulation of raw buffers using native LLVM load and store
instructions.

Where tests simply used a buffer intrinsic while testing some other
code path (such as the tests for VGPR spills), they have been updated
to use the new intrinsic form. Tests that are "about" buffer
intrinsics (for instance, those that ensure that they codegen as
expected) have been duplicated, either within existing files or into
new ones.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147547

Files:
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/test/Analysis/DivergenceAnalysis/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.atomic.add.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.atomic.cmpswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.ptr.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.ptr.store.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.ptr.store.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.atomic.add.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.atomic.cmpswap.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.ptr.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
  llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
  llvm/test/CodeGen/AMDGPU/amdpal.ll
  llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
  llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
  llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
  llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
  llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
  llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
  llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
  llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
  llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
  llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
  llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
  llvm/test/CodeGen/AMDGPU/else.ll
  llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
  llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
  llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
  llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
  llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.load.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.load.lds.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.store.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.ptr.load.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.ptr.store.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.load.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.load.format.v3f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.load.lds.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.store.format.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.ptr.load.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.ptr.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.ptr.store.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.ptr.store.ll
  llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
  llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
  llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
  llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
  llvm/test/CodeGen/AMDGPU/mubuf.ll
  llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
  llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
  llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
  llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
  llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
  llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
  llvm/test/CodeGen/AMDGPU/wait.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/AMDGPU/wqm.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
  llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
  llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
  llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
  llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
  llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
  llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
  llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll

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