[llvm] e7c4546 - [X86] combineBitcastvxi1 - peek through bitcast(concat(X,undef,undef,undef)) -> aext(bitcast(X))

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-04-04T15:38:49+01:00
New Revision: e7c454630732c6095406630243cf4f9485ea1ecb

URL: https://github.com/llvm/llvm-project/commit/e7c454630732c6095406630243cf4f9485ea1ecb
DIFF: https://github.com/llvm/llvm-project/commit/e7c454630732c6095406630243cf4f9485ea1ecb.diff

LOG: [X86] combineBitcastvxi1 - peek through bitcast(concat(X,undef,undef,undef)) -> aext(bitcast(X))

Improves fix for #61683 to handle cases where the legalization concatenation isn't just 2 subops.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8353cdaed5c6..119b1261a573 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -44102,17 +44102,21 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
   if (!Subtarget.hasSSE2() || (Subtarget.hasAVX512() && !PreferMovMsk))
     return SDValue();
 
-  // If the upper half of the ops are undef, then try to bitcast the lower half
-  // and extend.
+  // If the upper ops of a concatenation are undef, then try to bitcast the
+  // lower op and extend.
   SmallVector<SDValue, 4> SubSrcOps;
   if (collectConcatOps(Src.getNode(), SubSrcOps, DAG) &&
-      SubSrcOps.size() == 2) {
+      SubSrcOps.size() >= 2) {
     SDValue LowerOp = SubSrcOps[0];
-    SDValue UpperOp = SubSrcOps[1];
-    if (LowerOp.getOpcode() == ISD::SETCC && UpperOp.isUndef()) {
-      EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
-      if (SDValue V = combineBitcastvxi1(DAG, HalfVT, LowerOp, DL, Subtarget))
-        return DAG.getNode(ISD::ANY_EXTEND, DL, VT, V);
+    ArrayRef<SDValue> UpperOps(std::next(SubSrcOps.begin()), SubSrcOps.end());
+    if (LowerOp.getOpcode() == ISD::SETCC &&
+        all_of(UpperOps, [](SDValue Op) { return Op.isUndef(); })) {
+      EVT SubVT = VT.getIntegerVT(
+          *DAG.getContext(), LowerOp.getValueType().getVectorMinNumElements());
+      if (SDValue V = combineBitcastvxi1(DAG, SubVT, LowerOp, DL, Subtarget)) {
+        EVT IntVT = VT.getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
+        return DAG.getBitcast(VT, DAG.getNode(ISD::ANY_EXTEND, DL, IntVT, V));
+      }
     }
   }
 

diff  --git a/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll b/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
index 2ff9dd4d9424..26dea5d386b8 100644
--- a/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
+++ b/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
@@ -910,13 +910,9 @@ define i8 @v2i64_concat_undef(<2 x i64> %vec) {
 ; SSE2-SSSE3:       # %bb.0:
 ; SSE2-SSSE3-NEXT:    pxor %xmm1, %xmm1
 ; SSE2-SSSE3-NEXT:    pcmpeqd %xmm0, %xmm1
-; SSE2-SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,3,3,2]
-; SSE2-SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
-; SSE2-SSSE3-NEXT:    pand %xmm0, %xmm1
-; SSE2-SSSE3-NEXT:    pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-SSSE3-NEXT:    psllw $15, %xmm0
-; SSE2-SSSE3-NEXT:    packsswb %xmm0, %xmm0
-; SSE2-SSSE3-NEXT:    pmovmskb %xmm0, %eax
+; SSE2-SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,0,3,2]
+; SSE2-SSSE3-NEXT:    pand %xmm1, %xmm0
+; SSE2-SSSE3-NEXT:    movmskpd %xmm0, %eax
 ; SSE2-SSSE3-NEXT:    # kill: def $al killed $al killed $eax
 ; SSE2-SSSE3-NEXT:    retq
 ;
@@ -924,11 +920,7 @@ define i8 @v2i64_concat_undef(<2 x i64> %vec) {
 ; AVX12:       # %bb.0:
 ; AVX12-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX12-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0
-; AVX12-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
-; AVX12-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
-; AVX12-NEXT:    vpsllw $15, %xmm0, %xmm0
-; AVX12-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
-; AVX12-NEXT:    vpmovmskb %xmm0, %eax
+; AVX12-NEXT:    vmovmskpd %xmm0, %eax
 ; AVX12-NEXT:    # kill: def $al killed $al killed $eax
 ; AVX12-NEXT:    retq
 ;