[PATCH] D147536: [GlobalISel] Improve stack slot tracking in dbg.values

[Felipe de Azevedo Piovezan via Phabricator via llvm-commits]

fdeazeve created this revision.
fdeazeve added a reviewer: aprantl.
Herald added a subscriber: hiraditya.
Herald added a project: All.
fdeazeve requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

For IR like:

  %alloca = alloca ...
  dbg.value(%alloca, !myvar, OP_deref(<other_ops>))

GlobalISel lowers it to MIR:

  %some_reg = G_FRAME_INDEX <stack_slot>
  DBG_VALUE %some_reg, !myvar, OP_deref(<other_ops>)

In other words, if the value of `!myvar` can be obtained by
dereferencing an alloca, in MIR we say that the _location_ of a variable
is obtained by dereferencing register %some_reg (plus some
`<other_ops>`).

We can instead remove the use of `%some_reg`: the location of `!myvar`
_is_ `<stack_slot>` (plus some `<other_ops>`). This patch implements
this transformation, which improves debug information handling in O0, as
these registers hardly ever survive register allocation.

A note about testing: similar to what was done in D76934 <https://reviews.llvm.org/D76934>
(f24e2e9eebde4b7a1d <https://reviews.llvm.org/rGf24e2e9eebde4b7a1d10b11a2c0acd6fe9905712>), this patch exposed a bug in the Builder class when
using `-debug`, where we tried to print an incomplete instruction. The
changes in `MachineIRBuilder.cpp` address that.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147536

Files:
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll


Index: llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
@@ -28,13 +28,16 @@
 @gv = global i32 zeroinitializer
 
 ; CHECK-LABEL: name: debug_value
+; CHECK: stack:
+; CHECK:    - { id: {{.*}}, name: addr
 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
 define void @debug_value(i32 %in) #0 !dbg !16 {
+; CHECK: G_FRAME_INDEX %[[stack_slot:.*]]
   %addr = alloca i32
 ; CHECK: DBG_VALUE [[IN]](s32), $noreg, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
   store i32 %in, ptr %addr
-; CHECK: DBG_VALUE %1(p0), $noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
+; CHECK: DBG_VALUE %[[stack_slot]], 0, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata ptr %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
 ; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
Index: llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -80,11 +80,11 @@
   assert(
       cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
       "Expected inlined-at fields to agree");
-  return buildInstr(TargetOpcode::DBG_VALUE)
-      .addFrameIndex(FI)
-      .addImm(0)
-      .addMetadata(Variable)
-      .addMetadata(Expr);
+  return insertInstr(buildInstrNoInsert(TargetOpcode::DBG_VALUE)
+                         .addFrameIndex(FI)
+                         .addImm(0)
+                         .addMetadata(Variable)
+                         .addMetadata(Expr));
 }
 
 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
Index: llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1993,6 +1993,17 @@
       MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
     } else if (const auto *CI = dyn_cast<Constant>(V)) {
       MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
+    } else if (auto *AI = dyn_cast<AllocaInst>(V);
+               AI && AI->isStaticAlloca() &&
+               DI.getExpression()->startsWithDeref()) {
+      // If the value is an alloca and the expression starts with a
+      // dereference, track a stack slot instead of a register, as registers
+      // may be clobbered.
+      auto ExprOperands = DI.getExpression()->getElements();
+      auto *ExprDerefRemoved =
+          DIExpression::get(AI->getContext(), ExprOperands.drop_front());
+      MIRBuilder.buildFIDbgValue(getOrCreateFrameIndex(*AI), DI.getVariable(),
+                                 ExprDerefRemoved);
     } else {
       for (Register Reg : getOrCreateVRegs(*V)) {
         // FIXME: This does not handle register-indirect values at offset 0. The


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D147536.510804.patch
Type: text/x-patch
Size: 3318 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230404/ae347c33/attachment.bin>