[PATCH] D147533: [AArch64][CodeGen][SME] Allow vectors large than hardware support to use SVE's load zero/sign-extend for fixed vectors

[Dinar Temirbulatov via Phabricator via llvm-commits]

dtemirbulatov created this revision.
dtemirbulatov added reviewers: david-arm, CarolineConcatto, hassnaa-arm, sdesmalen.
Herald added subscribers: ctetreau, hiraditya, kristof.beyls, tschuett.
Herald added a project: All.
dtemirbulatov requested review of this revision.
Herald added a project: LLVM.

Proposed change improved some tests performance by allowing to fold Load + Extend to SVE's Load zero/sign extend for fixed vectors.


https://reviews.llvm.org/D147533

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll

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