[PATCH] D147523: [ARM] Fix VMOVSR pattern requirements

[Mikhail Maltsev via Phabricator via llvm-commits]

miyuki created this revision.
miyuki added reviewers: SjoerdMeijer, dmgreen, simon_tatham.
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The required target features for VMOVSR instruction (integer -> MVE
FP register copy) are HasFPRegs and UseVMOVSR (see
https://reviews.llvm.org/D60694).

The instruction selection pattern must use the same set of
requirements (i.e., HasFPRegs instead of HasVFP2). The discrepancy
causes a bug in our downstream toolchain in which, due to a custom
position-independence mode, immediate constants can be loaded via a
GPR rather than from a constant pool. Unfortunately, I don't know how to
reproduce this with upstream LLVM, so the patch lacks a test case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147523

Files:
  llvm/lib/Target/ARM/ARMInstrVFP.td


Index: llvm/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -1201,7 +1201,7 @@
   let D = VFPNeonDomain;
 }
 } // isMoveReg
-def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>;
+def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasFPRegs, UseVMOVSR]>;
 
 let hasSideEffects = 0 in {
 def VMOVRRD  : AVConv3I<0b11000101, 0b1011,


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