[llvm] 1e2f878 - [AArch64][GlobalISel] Move the localizer to run before the legalizer, and always localize globals.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 3 20:42:01 PDT 2023
Author: Amara Emerson
Date: 2023-04-03T20:41:54-07:00
New Revision: 1e2f87868f6fb64179b02c1076c6b3cd26576907
URL: https://github.com/llvm/llvm-project/commit/1e2f87868f6fb64179b02c1076c6b3cd26576907
DIFF: https://github.com/llvm/llvm-project/commit/1e2f87868f6fb64179b02c1076c6b3cd26576907.diff
LOG: [AArch64][GlobalISel] Move the localizer to run before the legalizer, and always localize globals.
Our strategy for localizing globals in the entry block breaks down when we have
large functions with high register pressure, using lots of globals. When this
happens, our heuristics say that globals with many uses should not be localized,
leading us to cause excessive spills and stack usage. These situations are also
exacerbated by LTO which tends to generate large functions.
For now, moving to a strategy that's simpler and more akin to SelectionDAG
fixes these issues and makes our codegen more similar. This has an overall
neutral effect on size on CTMark, while showing slight improvements with -Os -flto
on benchmarks. For low level firmware software though we see big improvements.
The reason this is neutral, and not an improvement, is because we give up the
gains from CSE'ing globals in cases where we low register pressure. I think
this can be addressed in future with some better heuristics.
Differential Revision: https://reviews.llvm.org/D147484
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
llvm/test/CodeGen/AArch64/O0-pipeline.ll
llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
llvm/test/CodeGen/AArch64/aarch64-mops.ll
llvm/test/CodeGen/AArch64/popcount.ll
llvm/test/Other/print-changed-machine.ll
Removed:
llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 08ba054078888..00f2964960c6e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -23246,7 +23246,7 @@ bool AArch64TargetLowering::shouldLocalize(
const GlobalValue &GV = *MI.getOperand(1).getGlobal();
if (GV.isThreadLocal() && Subtarget->isTargetMachO())
return false;
- break;
+ return true; // Always localize G_GLOBAL_VALUE to avoid high reg pressure.
}
case TargetOpcode::G_CONSTANT: {
auto *CI = MI.getOperand(1).getCImm();
@@ -23267,6 +23267,8 @@ bool AArch64TargetLowering::shouldLocalize(
// localizable.
case AArch64::ADRP:
case AArch64::G_ADD_LOW:
+ // Need to localize G_PTR_ADD so that G_GLOBAL_VALUE can be localized too.
+ case TargetOpcode::G_PTR_ADD:
return true;
default:
break;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index a8528d0808333..5ccba29f5d430 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -510,7 +510,6 @@ class AArch64PassConfig : public TargetPassConfig {
bool addLegalizeMachineIR() override;
void addPreRegBankSelect() override;
bool addRegBankSelect() override;
- void addPreGlobalInstructionSelect() override;
bool addGlobalInstructionSelect() override;
void addMachineSSAOptimization() override;
bool addILPOpts() override;
@@ -672,10 +671,12 @@ bool AArch64PassConfig::addIRTranslator() {
}
void AArch64PassConfig::addPreLegalizeMachineIR() {
- if (getOptLevel() == CodeGenOpt::None)
+ if (getOptLevel() == CodeGenOpt::None) {
addPass(createAArch64O0PreLegalizerCombiner());
- else {
+ addPass(new Localizer());
+ } else {
addPass(createAArch64PreLegalizerCombiner());
+ addPass(new Localizer());
if (EnableGISelLoadStoreOptPreLegal)
addPass(new LoadStoreOpt());
}
@@ -701,10 +702,6 @@ bool AArch64PassConfig::addRegBankSelect() {
return false;
}
-void AArch64PassConfig::addPreGlobalInstructionSelect() {
- addPass(new Localizer());
-}
-
bool AArch64PassConfig::addGlobalInstructionSelect() {
addPass(new InstructionSelect(getOptLevel()));
if (getOptLevel() != CodeGenOpt::None)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 10d6abc7e8b71..44ef557413067 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -2729,23 +2729,24 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NOLSE-O1-LABEL: cmpxchg_i8:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: mov x8, x0
+; CHECK-NOLSE-O1-NEXT: mov w9, w1
+; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
; CHECK-NOLSE-O1-NEXT: LBB47_1: ; %cmpxchg.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8]
-; CHECK-NOLSE-O1-NEXT: and w9, w0, #0xff
-; CHECK-NOLSE-O1-NEXT: cmp w9, w1, uxtb
+; CHECK-NOLSE-O1-NEXT: and w10, w0, #0xff
+; CHECK-NOLSE-O1-NEXT: cmp w10, w9, uxtb
; CHECK-NOLSE-O1-NEXT: b.ne LBB47_4
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %cmpxchg.trystore
; CHECK-NOLSE-O1-NEXT: ; in Loop: Header=BB47_1 Depth=1
-; CHECK-NOLSE-O1-NEXT: stxrb w9, w2, [x8]
-; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB47_1
+; CHECK-NOLSE-O1-NEXT: stxrb w10, w2, [x8]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB47_1
; CHECK-NOLSE-O1-NEXT: ; %bb.3:
; CHECK-NOLSE-O1-NEXT: mov w1, #1
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret
; CHECK-NOLSE-O1-NEXT: LBB47_4: ; %cmpxchg.nostore
-; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: clrex
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret
@@ -2795,23 +2796,24 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NOLSE-O1-LABEL: cmpxchg_i16:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: mov x8, x0
+; CHECK-NOLSE-O1-NEXT: mov w9, w1
+; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
; CHECK-NOLSE-O1-NEXT: LBB48_1: ; %cmpxchg.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8]
-; CHECK-NOLSE-O1-NEXT: and w9, w0, #0xffff
-; CHECK-NOLSE-O1-NEXT: cmp w9, w1, uxth
+; CHECK-NOLSE-O1-NEXT: and w10, w0, #0xffff
+; CHECK-NOLSE-O1-NEXT: cmp w10, w9, uxth
; CHECK-NOLSE-O1-NEXT: b.ne LBB48_4
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %cmpxchg.trystore
; CHECK-NOLSE-O1-NEXT: ; in Loop: Header=BB48_1 Depth=1
-; CHECK-NOLSE-O1-NEXT: stxrh w9, w2, [x8]
-; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB48_1
+; CHECK-NOLSE-O1-NEXT: stxrh w10, w2, [x8]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB48_1
; CHECK-NOLSE-O1-NEXT: ; %bb.3:
; CHECK-NOLSE-O1-NEXT: mov w1, #1
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret
; CHECK-NOLSE-O1-NEXT: LBB48_4: ; %cmpxchg.nostore
-; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: clrex
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index 647a9ac849f48..21ac5bc697df2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -1248,23 +1248,25 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
+ ; CHECK-NEXT: $w9 = ORRWrs $wzr, $w1, 0
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
+ ; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cmpxchg.start:
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
- ; CHECK-NEXT: liveins: $w1, $x2, $x8
+ ; CHECK-NEXT: liveins: $w1, $w9, $x2, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0
- ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 0, implicit-def $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w0, 7, pcsections !0
+ ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.4, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
- ; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8
+ ; CHECK-NEXT: liveins: $w1, $w9, $x0, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
- ; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
+ ; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: liveins: $x0
@@ -1274,9 +1276,8 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.cmpxchg.nostore:
- ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: CLREX 15, pcsections !0
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
@@ -1291,23 +1292,25 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
+ ; CHECK-NEXT: $w9 = ORRWrs $wzr, $w1, 0
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
+ ; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cmpxchg.start:
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
- ; CHECK-NEXT: liveins: $w1, $x2, $x8
+ ; CHECK-NEXT: liveins: $w1, $w9, $x2, $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
- ; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0
- ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 8, implicit-def $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w0, 15, pcsections !0
+ ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w10, renamable $w9, 8, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.4, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
- ; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8
+ ; CHECK-NEXT: liveins: $w1, $w9, $x0, $x2, $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
- ; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
+ ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
+ ; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: liveins: $x0
@@ -1317,9 +1320,8 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.cmpxchg.nostore:
- ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: CLREX 15, pcsections !0
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
index 156a9333bc008..df8fc178ab4de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
@@ -62,16 +62,15 @@
; ENABLED-O1-NEXT: MachineDominator Tree Construction
; ENABLED-O1-NEXT: Analysis containing CSE Info
; ENABLED-O1-NEXT: PreLegalizerCombiner
+; ENABLED-O1-NEXT: Localizer
; VERIFY-O0-NEXT: AArch64O0PreLegalizerCombiner
; VERIFY-NEXT: Verify generated machine code
; ENABLED-O1-NEXT: LoadStoreOpt
-; VERIFY-O0-NEXT: Analysis containing CSE Info
-; ENABLED-NEXT: Legalizer
+; ENABLED-O1-NEXT: Analysis containing CSE Info
+; ENABLED: Legalizer
; VERIFY-NEXT: Verify generated machine code
; ENABLED: RegBankSelect
; VERIFY-NEXT: Verify generated machine code
-; ENABLED-NEXT: Localizer
-; VERIFY-O0-NEXT: Verify generated machine code
; ENABLED-NEXT: Analysis for ComputingKnownBits
; ENABLED-O1-NEXT: Lazy Branch Probability Analysis
; ENABLED-O1-NEXT: Lazy Block Frequency Analysis
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
index 37c0ea45e8c40..291eb5e22ca14 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
@@ -12,10 +12,10 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: G_STORE [[C1]](s32), [[GV]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
@@ -29,9 +29,10 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
+ ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
@@ -66,10 +67,10 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: G_STORE [[C1]](s32), [[GV]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.ptr)
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ASSERT_ZEXT]](s8)
@@ -85,9 +86,10 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol >
- ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV]](p0) :: (store (s32) into @global_var)
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
+ ; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index fc026b519b7be..5662de4cbdca5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -13,12 +13,10 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
- ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: $w0 = COPY [[C]](s32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
@@ -34,7 +32,9 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot)
+ ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.ehselector.slot)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
@@ -42,7 +42,8 @@ define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.eh.resume:
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (p0) from %ir.exn.slot)
+ ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.exn.slot)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[LOAD]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
index ac4590e6e83b0..cf60df1f4ead4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
@@ -19,34 +19,34 @@ define i32 @foo() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C3]]
- ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.3
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1)
- ; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV4]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
+ ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV5]](p0) :: (store (s32) into @var3)
+ ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C6]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
@@ -77,27 +77,26 @@ define i32 @darwin_tls() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @tls_gv
- ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C1]]
- ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.3
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @tls_gv
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
- ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
+ ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end:
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
@@ -119,36 +118,35 @@ define i32 @imm_cost_too_large_cost_of_2() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 -2228259
- ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C2]]
- ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.4
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2228259
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: G_STORE [[C]](s32), [[GV3]](p0) :: (store (s32) into @var2)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: G_STORE [[C]](s32), [[GV4]](p0) :: (store (s32) into @var1)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
- ; CHECK-NEXT: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
+ ; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: G_STORE [[C]](s32), [[GV5]](p0) :: (store (s32) into @var3)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C3]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
@@ -175,38 +173,36 @@ define i64 @imm_cost_too_large_cost_of_4() {
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 -2228259
- ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2_64
- ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3_64
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1_64
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C3]]
- ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.4
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2228259
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2_64
+ ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: G_STORE [[C]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1_64
+ ; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
; CHECK-NEXT: G_STORE [[C]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end:
- ; CHECK-NEXT: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3_64
+ ; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: G_STORE [[C]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: $x0 = COPY [[C4]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[C3]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, ptr @var1_64, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
deleted file mode 100644
index bfa02814e6b24..0000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
+++ /dev/null
@@ -1,99 +0,0 @@
-# RUN: llc -O0 -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \
-# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPTNONE %s
-# RUN: llc -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \
-# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPT %s
-#
-# Check that we are only running the localizer at O0 and that it runs
-# between the regbankselect pass and the instruction-select.
-# Moreover, check that it does what we expect.
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64-apple-ios"
-
- define float @foo(float %arg, i1 %cond) {
- br i1 %cond, label %true, label %false
-
- true: ; preds = %0
- br label %end
-
- false: ; preds = %0
- br label %end
-
- end: ; preds = %false, %true
- %val = phi float [ 1.000000e+00, %true ], [ 2.000000e+00, %false ]
- %res = fadd float %arg, %val
- ret float %res
- }
-
-...
----
-# CHECK-LABEL: name: foo
-name: foo
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' }
-# The localizer will create two new values to materialize the constants.
-# OPTNONE-NEXT: - { id: 7, class: fpr, preferred-register: '' }
-# OPTNONE-NEXT: - { id: 8, class: fpr, preferred-register: '' }
- - { id: 0, class: fpr }
- - { id: 1, class: gpr }
- - { id: 2, class: fpr }
- - { id: 3, class: fpr }
- - { id: 4, class: fpr }
- - { id: 5, class: fpr }
- - { id: 6, class: gpr }
-
-# First block remains untouched
-# CHECK: body
-# CHECK: %4:fpr(s32) = G_FCONSTANT float 1.000000e+00
-# CHECK: %5:fpr(s32) = G_FCONSTANT float 2.000000e+00
-
-# Second block will get the constant 1.0 when the localizer is enabled.
-# CHECK: bb.1.{{[a-zA-Z0-9]+}}:
-# OPT: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
-# OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
-# CHECK: G_BR %bb.3
-
-# Thrid block will get the constant 2.0 when the localizer is enabled.
-# CHECK: bb.2.{{[a-zA-Z0-9]+}}:
-# OPT: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
-# OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
-
-# CHECK: bb.3.end
-# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
-# OPT: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
-# CHECK-NEXT: G_FADD %0, %2
-body: |
- bb.0 (%ir-block.0):
- liveins: $s0, $w0
-
- %0(s32) = COPY $s0
- %6(s32) = COPY $w0
- %1(s1) = G_TRUNC %6
- %4(s32) = G_FCONSTANT float 1.000000e+00
- %5(s32) = G_FCONSTANT float 2.000000e+00
- G_BRCOND %1(s1), %bb.1
- G_BR %bb.2
-
- bb.1.true:
- G_BR %bb.3
-
- bb.2.false:
-
- bb.3.end:
- %2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
- %3(s32) = G_FADD %0, %2
- $s0 = COPY %3(s32)
- RET_ReallyLR implicit $s0
-
-...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
index e9a2fcabd6298..9fb6a87553a48 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
@@ -21,22 +21,24 @@ body: |
; LOWER-LABEL: name: swap_sextinreg_lhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_sextinreg_lhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg:gpr64all = COPY $x0
- ; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
- ; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT: %cmp_rhs:gpr64sp = COPY $x1
- ; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64all = COPY $x0
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
+ ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
%cmp_rhs:_(s64) = COPY $x1
@@ -58,21 +60,23 @@ body: |
; LOWER-LABEL: name: dont_swap_more_than_one_use
; LOWER: liveins: $x0, $x1
- ; LOWER: %reg0:_(s64) = COPY $x0
- ; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
- ; LOWER: %add:_(s64) = G_ADD %cmp_lhs, %reg0
- ; LOWER: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
- ; LOWER: $w0 = COPY %cmp2(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
+ ; LOWER-NEXT: %add:_(s64) = G_ADD %cmp_lhs, %reg0
+ ; LOWER-NEXT: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
+ ; LOWER-NEXT: $w0 = COPY %cmp2(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_more_than_one_use
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg0:gpr64 = COPY $x0
- ; SELECT: %cmp_lhs:gpr64 = SBFMXri %reg0, 0, 7
- ; SELECT: %add:gpr64 = ADDXrr %cmp_lhs, %reg0
- ; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv
- ; SELECT: %cmp2:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp2
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
+ ; SELECT-NEXT: %cmp_lhs:gpr64 = SBFMXri %reg0, 0, 7
+ ; SELECT-NEXT: %add:gpr64 = ADDXrr %cmp_lhs, %reg0
+ ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp2:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp2
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
%reg1:_(s64) = COPY $x1
@@ -97,20 +101,22 @@ body: |
; LOWER-LABEL: name: dont_swap_legal_arith_immed_on_rhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- ; LOWER: %cmp_rhs:_(s64) = G_CONSTANT i64 12
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 12
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_legal_arith_immed_on_rhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg:gpr64 = COPY $x0
- ; SELECT: %cmp_lhs:gpr64common = SBFMXri %reg, 0, 7
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %cmp_lhs, 12, 0, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64 = COPY $x0
+ ; SELECT-NEXT: %cmp_lhs:gpr64common = SBFMXri %reg, 0, 7
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %cmp_lhs, 12, 0, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
%cmp_rhs:_(s64) = G_CONSTANT i64 12
@@ -131,23 +137,25 @@ body: |
; LOWER-LABEL: name: swap_non_arith_immed_on_rhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
- ; LOWER: %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_non_arith_immed_on_rhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg:gpr64all = COPY $x0
- ; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
- ; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567
- ; SELECT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
- ; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64all = COPY $x0
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
+ ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567
+ ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
%cmp_rhs:_(s64) = G_CONSTANT i64 1234567
@@ -165,23 +173,25 @@ body: |
liveins: $x0, $x1
; LOWER-LABEL: name: swap_and_lhs_0xFF
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %and_lhs:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 255
- ; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 255
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_and_lhs_0xFF
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64sp = COPY $x1
- ; SELECT: %and_lhs:gpr64all = COPY $x0
- ; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
- ; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 0, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
+ ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
+ ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 0, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%and_lhs:_(s64) = COPY $x0
@@ -202,23 +212,25 @@ body: |
liveins: $x0, $x1
; LOWER-LABEL: name: swap_and_lhs_0xFFFF
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 65535
- ; LOWER: %and_lhs:_(s64) = COPY $x0
- ; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 65535
+ ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_and_lhs_0xFFFF
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64sp = COPY $x1
- ; SELECT: %and_lhs:gpr64all = COPY $x0
- ; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
- ; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 8, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
+ ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
+ ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 8, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%cst:_(s64) = G_CONSTANT i64 65535
@@ -239,23 +251,25 @@ body: |
liveins: $x0, $x1
; LOWER-LABEL: name: swap_and_lhs_0xFFFFFFFF
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %and_lhs:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 4294967295
- ; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 4294967295
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_and_lhs_0xFFFFFFFF
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64sp = COPY $x1
- ; SELECT: %and_lhs:gpr64all = COPY $x0
- ; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
- ; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 16, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
+ ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
+ ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 16, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%and_lhs:_(s64) = COPY $x0
@@ -279,22 +293,24 @@ body: |
;
; LOWER-LABEL: name: dont_swap_and_lhs_wrong_mask
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %and_lhs:_(s64) = COPY $x0
- ; LOWER: %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
- ; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_and_lhs_wrong_mask
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %and_lhs:gpr64 = COPY $x0
- ; SELECT: %cmp_lhs:gpr64common = ANDXri %and_lhs, 4098
- ; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %and_lhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: %cmp_lhs:gpr64common = ANDXri %and_lhs, 4098
+ ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%and_lhs:_(s64) = COPY $x0
@@ -316,21 +332,23 @@ body: |
; LOWER-LABEL: name: swap_shl_lhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %shl_lhs:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 1
- ; LOWER: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_shl_lhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %shl_lhs:gpr64 = COPY $x0
- ; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %shl_lhs, 1, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %shl_lhs, 1, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%shl_lhs:_(s64) = COPY $x0
@@ -352,21 +370,23 @@ body: |
; LOWER-LABEL: name: swap_ashr_lhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %ashr_lhs:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 1
- ; LOWER: %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %ashr_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_ashr_lhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %ashr_lhs:gpr64 = COPY $x0
- ; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %ashr_lhs, 129, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %ashr_lhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %ashr_lhs, 129, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%ashr_lhs:_(s64) = COPY $x0
@@ -388,21 +408,23 @@ body: |
; LOWER-LABEL: name: swap_lshr_lhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %lshr_lhs:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 1
- ; LOWER: %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %lshr_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_lshr_lhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %lshr_lhs:gpr64 = COPY $x0
- ; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %lshr_lhs, 65, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %lshr_lhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %lshr_lhs, 65, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%lshr_lhs:_(s64) = COPY $x0
@@ -426,24 +448,26 @@ body: |
; LOWER-LABEL: name: dont_swap_shift_s64_cst_too_large
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %shl_lhs:_(s64) = COPY $x0
- ; LOWER: %too_large:_(s64) = G_CONSTANT i64 64
- ; LOWER: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %too_large:_(s64) = G_CONSTANT i64 64
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_shift_s64_cst_too_large
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %shl_lhs:gpr64 = COPY $x0
- ; SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64
- ; SELECT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
- ; SELECT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large
- ; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64
+ ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+ ; SELECT-NEXT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large
+ ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%shl_lhs:_(s64) = COPY $x0
@@ -468,23 +492,25 @@ body: |
; LOWER-LABEL: name: dont_swap_shift_s32_cst_too_large
; LOWER: liveins: $w0, $w1
- ; LOWER: %cmp_rhs:_(s32) = COPY $w1
- ; LOWER: %shl_lhs:_(s32) = COPY $w0
- ; LOWER: %cst:_(s32) = G_CONSTANT i32 32
- ; LOWER: %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s32) = COPY $w1
+ ; LOWER-NEXT: %shl_lhs:_(s32) = COPY $w0
+ ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 32
+ ; LOWER-NEXT: %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_shift_s32_cst_too_large
; SELECT: liveins: $w0, $w1
- ; SELECT: %cmp_rhs:gpr32 = COPY $w1
- ; SELECT: %shl_lhs:gpr32 = COPY $w0
- ; SELECT: %cst:gpr32 = MOVi32imm 32
- ; SELECT: %cmp_lhs:gpr32 = LSLVWr %shl_lhs, %cst
- ; SELECT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr32 = COPY $w1
+ ; SELECT-NEXT: %shl_lhs:gpr32 = COPY $w0
+ ; SELECT-NEXT: %cst:gpr32 = MOVi32imm 32
+ ; SELECT-NEXT: %cmp_lhs:gpr32 = LSLVWr %shl_lhs, %cst
+ ; SELECT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s32) = COPY $w1
%shl_lhs:_(s32) = COPY $w0
@@ -510,21 +536,23 @@ body: |
; LOWER-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %sub_rhs:_(s64) = COPY $x0
- ; LOWER: %zero:_(s64) = G_CONSTANT i64 0
- ; LOWER: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %sub_rhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %sub_rhs:gpr64 = COPY $x0
- ; SELECT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %sub_rhs, %cmp_rhs, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %sub_rhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %sub_rhs, %cmp_rhs, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%sub_rhs:_(s64) = COPY $x0
@@ -550,23 +578,25 @@ body: |
; LOWER-LABEL: name: swap_cmn_lhs
; LOWER: liveins: $x0, $x1
- ; LOWER: %cmp_rhs:_(s64) = COPY $x1
- ; LOWER: %shl_lhs:_(s64) = COPY $x0
- ; LOWER: %zero:_(s64) = G_CONSTANT i64 0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 63
- ; LOWER: %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
- ; LOWER: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
+ ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
+ ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 63
+ ; LOWER-NEXT: %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_cmn_lhs
; SELECT: liveins: $x0, $x1
- ; SELECT: %cmp_rhs:gpr64 = COPY $x1
- ; SELECT: %shl_lhs:gpr64 = COPY $x0
- ; SELECT: [[ADDSXrs:%[0-9]+]]:gpr64 = ADDSXrs %cmp_rhs, %shl_lhs, 63, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
+ ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[ADDSXrs:%[0-9]+]]:gpr64 = ADDSXrs %cmp_rhs, %shl_lhs, 63, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1
%shl_lhs:_(s64) = COPY $x0
@@ -596,31 +626,33 @@ body: |
; LOWER-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
; LOWER: liveins: $x0, $x1
- ; LOWER: %zero:_(s64) = G_CONSTANT i64 0
- ; LOWER: %reg0:_(s64) = COPY $x0
- ; LOWER: %shl_cst:_(s64) = G_CONSTANT i64 63
- ; LOWER: %shl:_(s64) = G_SHL %reg0, %shl_cst(s64)
- ; LOWER: %cmp_lhs:_(s64) = G_SUB %zero, %shl
- ; LOWER: %reg1:_(s64) = COPY $x1
- ; LOWER: %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
- ; LOWER: %ashr_cst:_(s64) = G_CONSTANT i64 3
- ; LOWER: %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64)
- ; LOWER: %cmp_rhs:_(s64) = G_SUB %zero, %ashr
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
+ ; LOWER-NEXT: %shl_cst:_(s64) = G_CONSTANT i64 63
+ ; LOWER-NEXT: %shl:_(s64) = G_SHL %reg0, %shl_cst(s64)
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %shl
+ ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
+ ; LOWER-NEXT: %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
+ ; LOWER-NEXT: %ashr_cst:_(s64) = G_CONSTANT i64 3
+ ; LOWER-NEXT: %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64)
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = G_SUB %zero, %ashr
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg0:gpr64 = COPY $x0
- ; SELECT: %shl:gpr64 = UBFMXri %reg0, 1, 0
- ; SELECT: %zero:gpr64 = COPY $xzr
- ; SELECT: %reg1:gpr64 = COPY $x1
- ; SELECT: %sext_in_reg:gpr64 = SBFMXri %reg1, 0, 0
- ; SELECT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def $nzcv
- ; SELECT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %shl, %cmp_rhs, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %zero:gpr64 = COPY $xzr
+ ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
+ ; SELECT-NEXT: %shl:gpr64 = UBFMXri %reg0, 1, 0
+ ; SELECT-NEXT: %reg1:gpr64 = COPY $x1
+ ; SELECT-NEXT: %sext_in_reg:gpr64 = SBFMXri %reg1, 0, 0
+ ; SELECT-NEXT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def $nzcv
+ ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %shl, %cmp_rhs, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%zero:_(s64) = G_CONSTANT i64 0
%reg0:_(s64) = COPY $x0
@@ -650,27 +682,29 @@ body: |
; LOWER-LABEL: name: dont_swap_rhs_with_supported_extend
; LOWER: liveins: $x0, $x1
- ; LOWER: %reg0:_(s64) = COPY $x0
- ; LOWER: %lhs_cst:_(s64) = G_CONSTANT i64 1
- ; LOWER: %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
- ; LOWER: %reg1:_(s64) = COPY $x1
- ; LOWER: %and_mask:_(s64) = G_CONSTANT i64 255
- ; LOWER: %and:_(s64) = G_AND %reg1, %and_mask
- ; LOWER: %rhs_cst:_(s64) = G_CONSTANT i64 1
- ; LOWER: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
+ ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
+ ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
+ ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
+ ; LOWER-NEXT: %and:_(s64) = G_AND %reg1, %and_mask
+ ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_rhs_with_supported_extend
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg0:gpr64 = COPY $x0
- ; SELECT: %cmp_lhs:gpr64 = UBFMXri %reg0, 63, 62
- ; SELECT: %reg1:gpr64 = COPY $x1
- ; SELECT: %and:gpr64common = ANDXri %reg1, 4103
- ; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_lhs, %and, 129, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
+ ; SELECT-NEXT: %cmp_lhs:gpr64 = UBFMXri %reg0, 63, 62
+ ; SELECT-NEXT: %reg1:gpr64 = COPY $x1
+ ; SELECT-NEXT: %and:gpr64common = ANDXri %reg1, 4103
+ ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_lhs, %and, 129, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s64) = COPY $x0
%lhs_cst:_(s64) = G_CONSTANT i64 1
%cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
@@ -701,27 +735,29 @@ body: |
; LOWER-LABEL: name: swap_rhs_with_supported_extend
; LOWER: liveins: $x0, $x1
- ; LOWER: %reg0:_(s64) = COPY $x0
- ; LOWER: %and_mask:_(s64) = G_CONSTANT i64 255
- ; LOWER: %and:_(s64) = G_AND %reg0, %and_mask
- ; LOWER: %lhs_cst:_(s64) = G_CONSTANT i64 1
- ; LOWER: %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
- ; LOWER: %rhs_cst:_(s64) = G_CONSTANT i64 5
- ; LOWER: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
+ ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
+ ; LOWER-NEXT: %and:_(s64) = G_AND %reg0, %and_mask
+ ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
+ ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
+ ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 5
+ ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_rhs_with_supported_extend
; SELECT: liveins: $x0, $x1
- ; SELECT: %reg0:gpr64 = COPY $x0
- ; SELECT: %and:gpr64common = ANDXri %reg0, 4103
- ; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg0.sub_32
- ; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT: %cmp_rhs:gpr64common = SBFMXri %and, 5, 63
- ; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 1, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
+ ; SELECT-NEXT: %and:gpr64common = ANDXri %reg0, 4103
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg0.sub_32
+ ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: %cmp_rhs:gpr64common = SBFMXri %and, 5, 63
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 1, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s64) = COPY $x0
%and_mask:_(s64) = G_CONSTANT i64 255
%and:_(s64) = G_AND %reg0, %and_mask(s64)
diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
index 3844da6ed3aba..b04998348dd05 100644
--- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -39,11 +39,12 @@
; CHECK-NEXT: IRTranslator
; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: AArch64O0PreLegalizerCombiner
+; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis containing CSE Info
+; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: Legalizer
; CHECK-NEXT: AArch64PostLegalizerLowering
; CHECK-NEXT: RegBankSelect
-; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: InstructionSelect
; CHECK-NEXT: ResetMachineFunction
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
index 1fe1308d8b351..ad1f4a27d5763 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
@@ -38,9 +38,9 @@ entry:
define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_1_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: mov w8, #1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
@@ -69,9 +69,9 @@ entry:
define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: mov w8, #10
; GISel-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
@@ -100,9 +100,9 @@ entry:
define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10000_zeroval:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: mov w8, #10000
; GISel-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
@@ -158,9 +158,9 @@ entry:
define ptr @memset_tagged_0(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_0:
; GISel-O0: // %bb.0: // %entry
+; GISel-O0-NEXT: mov x8, xzr
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
-; GISel-O0-NEXT: mov x8, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
@@ -192,10 +192,10 @@ entry:
define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_1:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: // implicit-def: $x9
-; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov w8, #1
; GISel-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-O0-NEXT: // implicit-def: $x9
+; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
@@ -227,10 +227,10 @@ entry:
define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: // implicit-def: $x9
-; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov w8, #10
; GISel-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-O0-NEXT: // implicit-def: $x9
+; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
@@ -262,10 +262,10 @@ entry:
define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10000:
; GISel-O0: // %bb.0: // %entry
-; GISel-O0-NEXT: // implicit-def: $x9
-; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov w8, #10000
; GISel-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-O0-NEXT: // implicit-def: $x9
+; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mops.ll b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
index e342f37ebe479..532a41280ce71 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mops.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mops.ll
@@ -92,9 +92,9 @@ define void @memset_10_zeroval_volatile(ptr %dst) {
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
-; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10
; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8
+; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: bl memset
; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O0-NEXT: ret
@@ -112,9 +112,9 @@ define void @memset_10_zeroval_volatile(ptr %dst) {
;
; GISel-MOPS-O0-LABEL: memset_10_zeroval_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry
-; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: mov w8, #10
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
@@ -150,9 +150,9 @@ define void @memset_10000_zeroval(ptr %dst) {
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
-; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10000
; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8
+; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: bl memset
; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O0-NEXT: ret
@@ -170,9 +170,9 @@ define void @memset_10000_zeroval(ptr %dst) {
;
; GISel-MOPS-O0-LABEL: memset_10000_zeroval:
; GISel-MOPS-O0: // %bb.0: // %entry
-; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
@@ -215,9 +215,9 @@ define void @memset_10000_zeroval_volatile(ptr %dst) {
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
-; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10000
; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8
+; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: bl memset
; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O0-NEXT: ret
@@ -235,9 +235,9 @@ define void @memset_10000_zeroval_volatile(ptr %dst) {
;
; GISel-MOPS-O0-LABEL: memset_10000_zeroval_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry
-; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
@@ -511,10 +511,10 @@ define void @memset_10_volatile(ptr %dst, i32 %value) {
;
; GISel-MOPS-O0-LABEL: memset_10_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry
-; GISel-MOPS-O0-NEXT: // implicit-def: $x9
-; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: mov w8, #10
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-MOPS-O0-NEXT: // implicit-def: $x9
+; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
@@ -578,10 +578,10 @@ define void @memset_10000(ptr %dst, i32 %value) {
;
; GISel-MOPS-O0-LABEL: memset_10000:
; GISel-MOPS-O0: // %bb.0: // %entry
-; GISel-MOPS-O0-NEXT: // implicit-def: $x9
-; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-MOPS-O0-NEXT: // implicit-def: $x9
+; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
@@ -644,10 +644,10 @@ define void @memset_10000_volatile(ptr %dst, i32 %value) {
;
; GISel-MOPS-O0-LABEL: memset_10000_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry
-; GISel-MOPS-O0-NEXT: // implicit-def: $x9
-; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
+; GISel-MOPS-O0-NEXT: // implicit-def: $x9
+; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index f3a90035c0b30..1dd282a142193 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -42,8 +42,8 @@ define i16 @popcount256(ptr nocapture nonnull readonly %0) {
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: fmov s1, s2
; CHECK-NEXT: // kill: def $s1 killed $s1 killed $q1
-; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: mov w10, wzr
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: mov w9, w0
; CHECK-NEXT: mov w8, w10
; CHECK-NEXT: bfi x9, x8, #32, #32
@@ -81,8 +81,8 @@ define <1 x i128> @popcount1x128(<1 x i128> %0) {
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w8, wzr
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: // kill: def $x0 killed $w0
; CHECK-NEXT: // kill: def $x8 killed $w8
; CHECK-NEXT: bfi x0, x8, #32, #32
diff --git a/llvm/test/Other/print-changed-machine.ll b/llvm/test/Other/print-changed-machine.ll
index 4e28beff51d1e..98ba95d8af626 100644
--- a/llvm/test/Other/print-changed-machine.ll
+++ b/llvm/test/Other/print-changed-machine.ll
@@ -22,7 +22,7 @@
; QUIET: *** IR Dump After IRTranslator (irtranslator) on foo ***
; QUIET-NOT: ***
-; QUIET: *** IR Dump After Legalizer (legalizer) on foo ***
+; QUIET: *** IR Dump After Localizer (localizer) on foo ***
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-passes=irtranslator,legalizer %s 2>&1 | \
; RUN: FileCheck %s --check-prefixes=VERBOSE-FILTER
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