[PATCH] D147470: [RISCV] Account for LMUL in memory op costs

[Philip Reames via Phabricator via llvm-commits]

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Generally, the cost of a memory op will scale with the number of vector registers accessed.  Machines might exist which have a narrow memory access than vector register width, but machines with a wider memory access width than vector register width seem unlikely.

I noticed this because we were preferring wide loads + deinterleaves on examples where the cost of a short gather (actually a strided load) would be better.  Touching 4 vector registers instead of doing a 4 element gather is not a good tradeoff.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147470

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll
  llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
  llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll

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