[PATCH] D147136: [AArch64][SME] Fix broken intrinsics for ZA STR (vector)

Mon Apr 3 03:41:40 PDT 2023

david-arm requested changes to this revision.
david-arm added a subscriber: rsandifo-arm.
david-arm added a comment.
This revision now requires changes to proceed.

Hi @sdesmalen, really sorry to do this, but following @rsandifo-arm's comment on D127317 <https://reviews.llvm.org/D127317> I realised this patch is still incorrect because in `@str_with_off_15mulvl` it should really look like:

  mov w12, #-15
  str za[w12, 15], [x0, #15, mul vl]

sine the vector select value passed in to the intrinsic was 0. We therefore need to ensure the vector select value in `str` is also 0.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147136/new/

https://reviews.llvm.org/D147136