[PATCH] D145301: Add more efficient vector bitcast for AArch64

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Can we split the store part into a separate patch? As far as I understand they can be treated separately and that would help keep the two parts simpler.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19507
+  EVT BaseVT;
+  if (isChainOfComparesAndLogicalOps(ComparisonResult, BaseVT)) {
+    // If we have a comparison, we can get the original types to work on instead
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Could we use computeNumSignBits to check if all the bits will be the same? It might not work very well at this point in the lowering, but llvm has fairly decent support for NumSignBits.

Or always include the setcc and optimize it away if it is not required, which we might know more clearly after everything has been legalized.


Repository:
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  https://reviews.llvm.org/D145301/new/

https://reviews.llvm.org/D145301