[PATCH] D127317: [AArch64][SME] Add ldr/str (fill/spill) intrinsics

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/SME/sme-intrinsics-loads.ll:280
+  %base = getelementptr i8, i8* %ptr, i64 %mulvl
+  call void @llvm.aarch64.sme.ldr(i32 0, i8* %base)
+  ret void;
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rsandifo-arm wrote:
> I think this is the same as @bryanpkc's comment, but I'm not sure how this can legitimately become:
> ```
> mov w12, wzr
> ldr za[w12, 15], [x0, #15, mul vl]
> ```
> If the intrinsic uses a single argument for the ZA index, shouldn't the register part of the index be adjusted to match the immediate offset?  I.e. shouldn't w12 + 15 == 0, to match the 0 argument to the intrinsic?
Hmm, yes I see your point. The instruction encoding is a little odd in that there is a single offset immediate used for both the vector select and for the address offset. I thought we had a fix for one of the issues with ldr/str in D147136, but I think there might still be a problem with the complex pattern. @rsandifo-arm @bryanpkc  I'll take a look!


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  https://reviews.llvm.org/D127317/new/

https://reviews.llvm.org/D127317