[llvm] a703a9a - [LoongArch] Optimize 32-bit addition with ALSL_W on LoongArch64

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2023-04-03T14:47:23+08:00
New Revision: a703a9ae33a8cc7e999732791d4d2a592eca3897

URL: https://github.com/llvm/llvm-project/commit/a703a9ae33a8cc7e999732791d4d2a592eca3897
DIFF: https://github.com/llvm/llvm-project/commit/a703a9ae33a8cc7e999732791d4d2a592eca3897.diff

LOG: [LoongArch] Optimize 32-bit addition with ALSL_W on LoongArch64

Optimize 32-bit 'x+(y<<i)' to (ALSL_W y, x, i) on LoongArch64,
in which 'i' is in [1, 2, 3, 4].

Reviewed By: xen0n, SixWeining

Differential Revision: https://reviews.llvm.org/D147423

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index db19dd4bdeea..31145ceeb9ab 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -1075,6 +1075,8 @@ def : Pat<(add GPR:$rk, (shl GPR:$rj, uimm2_plus1:$imm2)),
 let Predicates = [IsLA64] in {
 def : Pat<(add GPR:$rk, (shl GPR:$rj, uimm2_plus1:$imm2)),
           (ALSL_D GPR:$rj, GPR:$rk, uimm2_plus1:$imm2)>;
+def : Pat<(sext_inreg (add GPR:$rk, (shl GPR:$rj, uimm2_plus1:$imm2)), i32),
+          (ALSL_W GPR:$rj, GPR:$rk, uimm2_plus1:$imm2)>;
 def : Pat<(loongarch_bstrpick (add GPR:$rk, (shl GPR:$rj, uimm2_plus1:$imm2)),
                               (i64 31), (i64 0)),
           (ALSL_WU GPR:$rj, GPR:$rk, uimm2_plus1:$imm2)>;

diff  --git a/llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
index c84fe1a7666f..0dc37eebe853 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
@@ -1029,9 +1029,8 @@ define signext i32 @mul_i32_4098(i32 %a) {
 ;
 ; LA64-LABEL: mul_i32_4098:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    slli.d $a1, $a0, 1
-; LA64-NEXT:    slli.d $a0, $a0, 12
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.w $a0, $a0, $a1, 1
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4098
   ret i32 %b
@@ -1046,9 +1045,8 @@ define signext i32 @mul_i32_4100(i32 %a) {
 ;
 ; LA64-LABEL: mul_i32_4100:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    slli.d $a1, $a0, 2
-; LA64-NEXT:    slli.d $a0, $a0, 12
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.w $a0, $a0, $a1, 2
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4100
   ret i32 %b
@@ -1063,9 +1061,8 @@ define signext i32 @mul_i32_4104(i32 %a) {
 ;
 ; LA64-LABEL: mul_i32_4104:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    slli.d $a1, $a0, 3
-; LA64-NEXT:    slli.d $a0, $a0, 12
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.w $a0, $a0, $a1, 3
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4104
   ret i32 %b
@@ -1080,9 +1077,8 @@ define signext i32 @mul_i32_4112(i32 %a) {
 ;
 ; LA64-LABEL: mul_i32_4112:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    slli.d $a1, $a0, 4
-; LA64-NEXT:    slli.d $a0, $a0, 12
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    slli.d $a1, $a0, 12
+; LA64-NEXT:    alsl.w $a0, $a0, $a1, 4
 ; LA64-NEXT:    ret
   %b = mul i32 %a, 4112
   ret i32 %b