[PATCH] D145085: [RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN

[Luke Lau via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb95913e8c3a3: [RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN (authored by luke).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145085/new/

https://reviews.llvm.org/D145085

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

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