[PATCH] D147368: [LoongArch] Optimize bitwise and with immediates
Lu Weining via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 2 06:03:32 PDT 2023
SixWeining added inline comments.
================
Comment at: llvm/test/CodeGen/LoongArch/ir-instruction/and.ll:348-352
; LA64-NEXT: lu12i.w $a2, 15
; LA64-NEXT: ori $a2, $a2, 4080
; LA64-NEXT: and $a1, $a1, $a2
; LA64-NEXT: and $a0, $a0, $a2
; LA64-NEXT: mul.d $a0, $a0, $a1
----------------
It's also a win if optimized to `bstrpick + slli` since we can save a register `$a2`. Right?
```
; LA64-NEXT: bstrpick.d $a0, $a0, 15, 4
; LA64-NEXT: slli.d $a0, $a0, 4
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 4
; LA64-NEXT: slli.d $a1, $a1, 4
; LA64-NEXT: mul.d $a0, $a0, $a1
```
But if the immediate `0xfff0` is used 3 times, we have 2 choices:
1. Use less registers but one more instruction.
2. Use less instructions but one more register.
I'm not sure how to balance this.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147368/new/
https://reviews.llvm.org/D147368
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