[llvm] 241ad16 - [RISCV] Add special case for i32 uaddo X, -1 on RV64.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-04-01T18:54:03-07:00
New Revision: 241ad16eb012ed75d1ff2d8eed8db9464b5c7787

URL: https://github.com/llvm/llvm-project/commit/241ad16eb012ed75d1ff2d8eed8db9464b5c7787
DIFF: https://github.com/llvm/llvm-project/commit/241ad16eb012ed75d1ff2d8eed8db9464b5c7787.diff

LOG: [RISCV] Add special case for i32 uaddo X, -1 on RV64.

uaddo X, -1 over flows if X is non-zero.

Matches what we do i32 uaddo X, -1 on RV32.

Fixes #61891.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 057ecf9c7bc6c..6fff811d8eb49 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8405,6 +8405,10 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       // no compare with constant and branch instructions.
       Overflow = DAG.getSetCC(DL, N->getValueType(1), Res,
                               DAG.getConstant(0, DL, MVT::i64), ISD::SETEQ);
+    } else if (IsAdd && isAllOnesConstant(RHS)) {
+      // Special case uaddo X, -1 overflowed if X != 0.
+      Overflow = DAG.getSetCC(DL, N->getValueType(1), N->getOperand(0),
+                              DAG.getConstant(0, DL, MVT::i32), ISD::SETNE);
     } else {
       // Sign extend the LHS and perform an unsigned compare with the ADDW
       // result. Since the inputs are sign extended from i32, this is equivalent

diff  --git a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
index 3aa65dff6d153..dcaca2da146db 100644
--- a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
@@ -671,9 +671,10 @@ define i1 @uaddo_i32_decrement_alt(i32 signext %x, ptr %p) {
 ;
 ; RV64-LABEL: uaddo_i32_decrement_alt:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addiw a2, a0, -1
-; RV64-NEXT:    sltu a0, a2, a0
-; RV64-NEXT:    sw a2, 0(a1)
+; RV64-NEXT:    snez a2, a0
+; RV64-NEXT:    addiw a0, a0, -1
+; RV64-NEXT:    sw a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
   %a = add i32 %x, -1
   store i32 %a, ptr %p