[PATCH] D147335: WIP: [AMDGPU] Don't define _SGPR forms of Real SMEM instructions on GFX10+

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SMInstructions.td:978
+  def _IMM_gfx10 : SMEM_Real_Load_gfx10<op, ps#"_IMM"> {
+    let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset_null:$offset, CPol:$cpol);
+  }
----------------
I am unhappy that there is so much repetition here. Every GFX10 Real instruction has to refine the whole `InOperandList` just so it can use a different operand type for `$offset` to get the disassembler to print it in the right way.

I would love to hear ideas for a better way to do this.


================
Comment at: llvm/test/MC/AMDGPU/gfx10_asm_smem.s:1365
 s_load_dword s1, s[2:3] glc
-// GFX10: s_load_dword s1, s[2:3], 0x0 glc ; encoding: [0x41,0x00,0x01,0xf4,0x00,0x00,0x00,0xfa]
+// GFX10: s_load_dword s1, s[2:3], null glc ; encoding: [0x41,0x00,0x01,0xf4,0x00,0x00,0x00,0xfa]
 
----------------
These assembler changes are intentional and (I think) desirable. Previously these two GFX10 instructions would be assembled to identical binary, but the assembler would print them differently:
```
s_load_dword s1, s[2:3], 0x0
s_load_dword s1, s[2:3], null
```
Output of `llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding`:
```
	s_load_dword s1, s[2:3], 0x0            ; encoding: [0x41,0x00,0x00,0xf4,0x00,0x00,0x00,0xfa]
	s_load_dword s1, s[2:3], null           ; encoding: [0x41,0x00,0x00,0xf4,0x00,0x00,0x00,0xfa]
```
I claim that this is wrong, and the assembler should always print them in the same way that a disassembly of the assembled binary would.

Unfortunately this causes a lot of churn in codegen tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147335/new/

https://reviews.llvm.org/D147335