[PATCH] D139732: [AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin marked an inline comment as done.
vpykhtin added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:91
+  /// Map OldSubReg -> { RC, NewSubReg }. Used as in/out container.
+  typedef SmallDenseMap<unsigned, SubRegInfo> SubRegMap;
+
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arsenm wrote:
> vpykhtin wrote:
> > arsenm wrote:
> > > Shouldn't this be a static table?
> > I agree, but sometime ago I was warned about avoiding static data-members to reduce library memory footprint.
> This wouldn't even be that big of a table. Tablegen could emit it. The concern would be static constructors, a simple static constexpr table wouldn't have that issue.
Sorry this isn't constant map, I was thinking about cashed tables. This map is only valid for a specific combination of subregs used: for example, if we use only sub3, we can shift it to sub0, but if we use sub2_sub3, sub2 and sub3 - sub3 can only be sub1.


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  https://reviews.llvm.org/D139732/new/

https://reviews.llvm.org/D139732