[PATCH] D145329: AMDGPU: Always split blocks for si_end_cf

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D145329#4236105 <https://reviews.llvm.org/D145329#4236105>, @nhaehnle wrote:

> Yes, what I'm thinking of as a clean story would require changing the register allocator a little.

OK, so we'll leave things broken for at least 5 more years. Terminators and phis are the only insertion points we can reasonably expect to work today so I think we just need to do this. We could explore better options whenever we get to trying to explicit track both CFGs in the IR at the same time. Right now I think it's a lower barrier of entry to teaching more passes to understand consecutive fall through blocks


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https://reviews.llvm.org/D145329