[PATCH] D147158: [AMDGPU] Do not reserve 16-bit registers

Fri Mar 31 06:15:46 PDT 2023

foad added a comment.

In D147158#4234470 <https://reviews.llvm.org/D147158#4234470>, @rampitec wrote:

> Here is the thing:
>
>   v_mov_b16 v0.h, vcc_lo.h
>       0xd59c4800
>       0x0000006a
>   v_mov_b16 v0.l, vcc_hi.l
>       0x7e00386b
>
> So this all seems legal.

Right, VALU instructions can access 16-bit SGPRs, and the assembler/disassembler has to accept that. The tricky question is whether we want to expose that to codegen. and I think it will be hard to do that because there is no S_MOV_B16 instruction and in general no way to //write// to a 16-bit SGPR; you can only read from them.

Thanks for the review.

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https://reviews.llvm.org/D147158