[PATCH] D127317: [AArch64][SME] Add ldr/str (fill/spill) intrinsics

[Richard Sandiford via Phabricator via llvm-commits]

rsandifo-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/SME/sme-intrinsics-loads.ll:280
+  %base = getelementptr i8, i8* %ptr, i64 %mulvl
+  call void @llvm.aarch64.sme.ldr(i32 0, i8* %base)
+  ret void;
----------------
I think this is the same as @bryanpkc's comment, but I'm not sure how this can legitimately become:
```
mov w12, wzr
ldr za[w12, 15], [x0, #15, mul vl]
```
If the intrinsic uses a single argument for the ZA index, shouldn't the register part of the index be adjusted to match the immediate offset?  I.e. shouldn't w12 + 15 == 0, to match the 0 argument to the intrinsic?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127317/new/

https://reviews.llvm.org/D127317