[llvm] c538353 - [ARM] Handle generating SEH unwind info for t2STR_PRE/t2LDR_POST
Martin Storsjö via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 31 00:27:42 PDT 2023
Author: Martin Storsjö
Date: 2023-03-31T10:22:28+03:00
New Revision: c5383536cb6824391f99f8f5963fc1427dd1673f
URL: https://github.com/llvm/llvm-project/commit/c5383536cb6824391f99f8f5963fc1427dd1673f
DIFF: https://github.com/llvm/llvm-project/commit/c5383536cb6824391f99f8f5963fc1427dd1673f.diff
LOG: [ARM] Handle generating SEH unwind info for t2STR_PRE/t2LDR_POST
This fixes compiling some uncommon cases.
Differential Revision: https://reviews.llvm.org/D147212
Added:
Modified:
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 5fa7068c89eb7..ae5a45ff5985a 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -357,6 +357,34 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
.setMIFlags(Flags);
break;
+ case ARM::t2STR_PRE:
+ if (MBBI->getOperand(0).getReg() == ARM::SP &&
+ MBBI->getOperand(2).getReg() == ARM::SP &&
+ MBBI->getOperand(3).getImm() == -4) {
+ unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
+ MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
+ .addImm(1 << Reg)
+ .addImm(/*Wide=*/1)
+ .setMIFlags(Flags);
+ } else {
+ report_fatal_error("No matching SEH Opcode for t2STR_PRE");
+ }
+ break;
+
+ case ARM::t2LDR_POST:
+ if (MBBI->getOperand(1).getReg() == ARM::SP &&
+ MBBI->getOperand(2).getReg() == ARM::SP &&
+ MBBI->getOperand(3).getImm() == 4) {
+ unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
+ MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
+ .addImm(1 << Reg)
+ .addImm(/*Wide=*/1)
+ .setMIFlags(Flags);
+ } else {
+ report_fatal_error("No matching SEH Opcode for t2LDR_POST");
+ }
+ break;
+
case ARM::t2LDMIA_RET:
case ARM::t2LDMIA_UPD:
case ARM::t2STMDB_UPD: {
diff --git a/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll b/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
index e97da669d65aa..1756d93052811 100644
--- a/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
+++ b/llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
@@ -311,3 +311,31 @@ entry:
}
declare arm_aapcs_vfpcc void @useptr(ptr noundef)
+
+; CHECK-LABEL: func_fp:
+; CHECK-NEXT: .seh_proc func_fp
+; CHECK-NEXT: @ %bb.0: @ %entry
+; CHECK-NEXT: str r11, [sp, #-4]!
+; CHECK-NEXT: .seh_save_regs_w {r11}
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .seh_save_sp r11
+; CHECK-NEXT: .seh_endprologue
+
+; CHECK-NEXT: mov r0, r11
+
+; CHECK-NEXT: .seh_startepilogue
+; CHECK-NEXT: ldr r11, [sp], #4
+; CHECK-NEXT: .seh_save_regs_w {r11}
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .seh_nop
+; CHECK-NEXT: .seh_endepilogue
+; CHECK-NEXT: .seh_endproc
+
+define arm_aapcs_vfpcc i32 @func_fp() {
+entry:
+ %0 = tail call ptr @llvm.frameaddress.p0(i32 0)
+ %1 = ptrtoint ptr %0 to i32
+ ret i32 %1
+}
+
+declare ptr @llvm.frameaddress.p0(i32 immarg)
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