[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG96a7e057567d: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147261/new/

https://reviews.llvm.org/D147261

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td

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