[PATCH] D147236: [AArch64][Combine]: combine <2xi64> Mul-Add.

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17815
 
+static SDValue performAddMulCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() == ISD::ADD) {
----------------
Maybe add a comment of what is your combination about.
add v1 ,  ( mul v2, v3 ) -> mla  v1, v2, v3


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17816
+static SDValue performAddMulCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() == ISD::ADD) {
+    SDValue MulValue, ConstValue;
----------------
Maybe replace this :
 if (N->getOpcode() == ISD::ADD) 
by this:
if (N->getOpcode() != ISD::ADD)
   return SDValue();

and then you can remove all the rest from the brackets.


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Comment at: llvm/test/CodeGen/AArch64/aarch64-combine-mul-add.ll:30
+  %mul = mul <1 x i64> %b, %c
+  %add = add <1 x i64> %a, %mul
+  ret <1 x i64> %add
----------------
Can you add a test changing the order of the add.
 %add = add <1 x i64> %mul, %a


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147236/new/

https://reviews.llvm.org/D147236