[PATCH] D146287: [AMDGPU][GISel] Add inverse ballot intrinsic
Nicolai Hähnle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 30 04:26:40 PDT 2023
nhaehnle added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4502-4523
+ for (unsigned i = 0; i < NumParts; ++i) {
+ Register DstPart = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
+ // 64-bit masks need to be split into two 32-bit parts.
+ // We need to address the subregs for the readfirstlanes
+ int SubReg = Is32Mask ? 0 : (AMDGPU::sub0 + i * 8);
+ BuildMI(*BB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
+ Is32Mask ? DstReg : DstPart)
----------------
OutOfCache wrote:
> nhaehnle wrote:
> > This entire sequence could probably be replaced by just calling SIInstrInfo::readlaneVGPRToSGPR.
> Good call. Would it make sense to also use this method for other pseudos that generate readfirstlanes here? Like `S_ADD_CO_PSEUDO`. In another change, of course.
I think so, yes. And yes, it should be a separate change.
Repository:
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https://reviews.llvm.org/D146287/new/
https://reviews.llvm.org/D146287
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