[PATCH] D147158: [AMDGPU] Do not reserve 16-bit registers

Wed Mar 29 12:53:19 PDT 2023

Joe_Nash added a comment.

SGPR_HI16 is already marked as not allocatable. So L611 was partially redundant with that. But this patch does appear to remove a barrier to allocating into the hi or lo half of TMA_LO or some other non-GPR SReg.
I guess there is other code somewhere preventing allocating to those non-GPR SReg? If so, this patch can be marked NFC and the commit reworded to say it skips redundant reservations.

In D147158#4231480 <https://reviews.llvm.org/D147158#4231480>, @rampitec wrote:

> I am not so sure about SGPRs. I believe it is legal to use SGPR halves.

It appears that this patch does not change anything about the legality of allocating registers in class SGPR_LO16.

Repository:
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  https://reviews.llvm.org/D147158/new/

https://reviews.llvm.org/D147158