[PATCH] D147113: [DAG][RISCV] Allow scalable vector ISD::STRICT_FP_ROUND and support vector ISD::STRICT_FP_ROUND for RISC-V.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5413
   // RVV can only widen fp to types double the size as the source, so it needs
   // two vfwcvt to achieve extending fp16 to fp64.
+  if ((VT.getVectorElementType() == MVT::f64 &&
----------------
comment is stale


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll:61
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfncvt.f.f.w v10, v8
+; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
----------------
Doesn't this need to be vfncvt.rod.f.f.w?


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  https://reviews.llvm.org/D147113/new/

https://reviews.llvm.org/D147113