[PATCH] D147108: [InstCombine] Add transforms for `(rem (shl Y, X), (shl Z, X))`

[Noah Goldstein via Phabricator via llvm-commits]

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This is just filling in a missing case from D144225 <https://reviews.llvm.org/D144225>.

We treat `(shl Y, X)` and `(shl Z, X)` as `(mul Z, 1 << X)` and `(mul
Y, 1 << X)` then reuse the same transformations that already exist.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147108

Files:
  llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
  llvm/test/Transforms/InstCombine/rem-mul-shl.ll


Index: llvm/test/Transforms/InstCombine/rem-mul-shl.ll
===================================================================
--- llvm/test/Transforms/InstCombine/rem-mul-shl.ll
+++ llvm/test/Transforms/InstCombine/rem-mul-shl.ll
@@ -51,10 +51,7 @@
 
 define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0_with_shl(i8 %X) {
 ; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0_with_shl(
-; CHECK-NEXT:    [[BO0:%.*]] = shl nuw i8 15, [[X:%.*]]
-; CHECK-NEXT:    [[BO1:%.*]] = shl i8 5, [[X]]
-; CHECK-NEXT:    [[R:%.*]] = urem i8 [[BO0]], [[BO1]]
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    ret i8 0
 ;
   %BO0 = shl nuw i8 15, %X
   %BO1 = shl i8 5, %X
@@ -88,9 +85,7 @@
 
 define i8 @urem_XY_XZ_with_CY_lt_CZ_with_shl(i8 %X) {
 ; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_with_shl(
-; CHECK-NEXT:    [[BO0:%.*]] = shl i8 3, [[X:%.*]]
-; CHECK-NEXT:    [[BO1:%.*]] = shl nuw i8 12, [[X]]
-; CHECK-NEXT:    [[R:%.*]] = urem i8 [[BO0]], [[BO1]]
+; CHECK-NEXT:    [[R:%.*]] = shl nuw i8 3, [[X:%.*]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %BO0 = shl i8 3, %X
@@ -309,9 +304,7 @@
 
 define <2 x i8> @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out_with_shl(<2 x i8> %X) {
 ; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out_with_shl(
-; CHECK-NEXT:    [[BO0:%.*]] = shl nuw <2 x i8> <i8 3, i8 3>, [[X:%.*]]
-; CHECK-NEXT:    [[BO1:%.*]] = shl nsw <2 x i8> <i8 15, i8 15>, [[X]]
-; CHECK-NEXT:    [[R:%.*]] = srem <2 x i8> [[BO0]], [[BO1]]
+; CHECK-NEXT:    [[R:%.*]] = shl nuw nsw <2 x i8> <i8 3, i8 3>, [[X:%.*]]
 ; CHECK-NEXT:    ret <2 x i8> [[R]]
 ;
   %BO0 = shl nuw <2 x i8> <i8 3, i8 3>, %X
Index: llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -1703,6 +1703,7 @@
                                        InstCombinerImpl &IC) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1), *X;
   const APInt *Y, *Z;
+  bool ShiftX = false;
 
   APInt AdjustedY, AdjustedZ;
   // Just treat the shifts as mul, we may end up returning a mul by power
@@ -1729,6 +1730,11 @@
              match(Op1, m_Shl(m_Specific(X), m_APInt(Z)))) {
     AdjustedY = GetShiftedAPInt(Y);
     AdjustedZ = GetShiftedAPInt(Z);
+  } else if (match(Op0, m_Shl(m_APInt(Y), m_Value(X))) &&
+             match(Op1, m_Shl(m_APInt(Z), m_Specific(X)))) {
+    AdjustedY = *Y;
+    AdjustedZ = *Z;
+    ShiftX = true;
   } else {
     return nullptr;
   }
@@ -1749,6 +1755,11 @@
   if (RemYZ.isZero() && BO0NoWrap)
     return IC.replaceInstUsesWith(I, ConstantInt::getNullValue(I.getType()));
 
+  auto GetBinOpOut = [&](Value *RemSimplification) -> BinaryOperator * {
+    return ShiftX ? BinaryOperator::CreateShl(RemSimplification, X)
+                  : BinaryOperator::CreateMul(X, RemSimplification);
+  };
+
   OverflowingBinaryOperator *BO1 = cast<OverflowingBinaryOperator>(Op1);
   bool BO1HasNSW = BO1->hasNoSignedWrap();
   bool BO1HasNUW = BO1->hasNoUnsignedWrap();
@@ -1757,8 +1768,7 @@
   //      if (rem Y, Z) == Y
   //          -> (mul nuw/nsw X, Y)
   if (RemYZ == AdjustedY && BO1NoWrap) {
-    BinaryOperator *BO =
-        BinaryOperator::CreateMul(X, ConstantInt::get(I.getType(), AdjustedY));
+    BinaryOperator *BO = GetBinOpOut(ConstantInt::get(I.getType(), AdjustedY));
     // Copy any overflow flags from Op0.
     BO->setHasNoSignedWrap(IsSRem || BO0HasNSW);
     BO->setHasNoUnsignedWrap(!IsSRem || BO0HasNUW);
@@ -1770,8 +1780,7 @@
   //          -> (mul {nuw} nsw X, (rem Y, Z))
   if (AdjustedY.uge(AdjustedZ) &&
       (IsSRem ? (BO0HasNSW && BO1HasNSW) : BO0HasNUW)) {
-    BinaryOperator *BO =
-        BinaryOperator::CreateMul(X, ConstantInt::get(I.getType(), RemYZ));
+    BinaryOperator *BO = GetBinOpOut(ConstantInt::get(I.getType(), RemYZ));
     BO->setHasNoSignedWrap();
     BO->setHasNoUnsignedWrap(BO0HasNUW);
     return BO;


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