[PATCH] D147096: AMDGPU: Created a sub-register class for the return address operand in the tail call return instruction

[Changpeng Fang via Phabricator via llvm-commits]

cfang created this revision.
cfang added reviewers: arsenm, cdevadas, bcahoon.
Herald added subscribers: kosarev, foad, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl, qcolombet, MatzeB.
Herald added a project: All.
cfang requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

This is to avoid using the callee saved registers for the return address of the tail call return instruction.


https://reviews.llvm.org/D147096

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D147096.509174.patch
Type: text/x-patch
Size: 24406 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230328/2e716757/attachment.bin>