[PATCH] D147079: InlineSpiller: Consider if all subranges are the same when avoiding redundant spills

[Matt Arsenault via Phabricator via llvm-commits]

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This avoids some redundant spills of subranges, and avoids a compile failure.
This greatly reduces the numbers of spills in a loop.

      

The main range is not informative when multiple instructions are needed to fully define
a register. A common scenario is a lowered reg_sequence where every subregister
is sequentially defined, but each def changes the main range's value number. If
we look at specific lanes at the use index, we can see the value is actually the
same.

In this testcase, there are a large number of materialized 64-bit constant defs
which are hoisted outside of the loop by MachineLICM. These are feeding REG_SEQUENCES,
which is not considered rematerializable inside the loop. After coalescing, the split
constant defs produce main ranges with an apparent phi def. There's no phi def if you look
at each individual subrange, and only half of the register is really redefined to a constant.

      

Fixes: SWDEV-380865


https://reviews.llvm.org/D147079

Files:
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/AMDGPU/swdev380865.ll
  llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
  llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll

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