[llvm] d10866e - [AMDGPU] Avoid duplicated work in SIRegisterInfo::getReservedRegs

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-03-28T16:54:52+01:00
New Revision: d10866e8bde815c69f48474ea34ebb4396e52287

URL: https://github.com/llvm/llvm-project/commit/d10866e8bde815c69f48474ea34ebb4396e52287
DIFF: https://github.com/llvm/llvm-project/commit/d10866e8bde815c69f48474ea34ebb4396e52287.diff

LOG: [AMDGPU] Avoid duplicated work in SIRegisterInfo::getReservedRegs

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 3bb93b72c3473..c281e3655e474 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -380,9 +380,7 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
 
 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,
                                            MCRegister Reg) const {
-  MCRegAliasIterator R(Reg, this, true);
-
-  for (; R.isValid(); ++R)
+  for (MCRegAliasIterator R(Reg, this, true); R.isValid(); ++R)
     Reserved.set(*R);
 }
 
@@ -652,13 +650,6 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   unsigned MaxNumAGPRs = MaxNumVGPRs;
   unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
 
-  // Reserve all the AGPRs if there are no instructions to use it.
-  if (!ST.hasMAIInsts()) {
-    for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
-      reserveRegisterTuples(Reserved, Reg);
-    }
-  }
-
   for (auto Reg : AMDGPU::AGPR_32RegClass) {
     Reserved.set(getSubReg(Reg, AMDGPU::hi16));
   }
@@ -689,9 +680,15 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     reserveRegisterTuples(Reserved, Reg);
   }
 
-  for (unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
-    unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
-    reserveRegisterTuples(Reserved, Reg);
+  if (ST.hasMAIInsts()) {
+    for (unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
+      unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
+      reserveRegisterTuples(Reserved, Reg);
+    }
+  } else {
+    // Reserve all the AGPRs if there are no instructions to use it.
+    for (MCRegister Reg : AMDGPU::AGPR_32RegClass)
+      reserveRegisterTuples(Reserved, Reg);
   }
 
   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch