[llvm] 4b7b612 - [RISCV][TTI] Extract getConstantPoolLoadCost helper routine [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 28 07:48:55 PDT 2023
Author: Philip Reames
Date: 2023-03-28T07:48:09-07:00
New Revision: 4b7b612c5d34e5be2a5190fd144e49336b142bf1
URL: https://github.com/llvm/llvm-project/commit/4b7b612c5d34e5be2a5190fd144e49336b142bf1
DIFF: https://github.com/llvm/llvm-project/commit/4b7b612c5d34e5be2a5190fd144e49336b142bf1.diff
LOG: [RISCV][TTI] Extract getConstantPoolLoadCost helper routine [nfc]
We had 3 copies of this code, and I am about to add a fourth.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 3b04a9abede2..20379b1f22b7 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -243,6 +243,16 @@ RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
llvm_unreachable("Unsupported register kind");
}
+InstructionCost
+RISCVTTIImpl::getConstantPoolLoadCost(Type *Ty, TTI::TargetCostKind CostKind) {
+ // Add a cost of address generation + the cost of the load. The address
+ // is expected to be a PC relative offset to a constant pool entry
+ // using auipc/addi.
+ return 2 + getMemoryOpCost(Instruction::Load, Ty, DL.getABITypeAlign(Ty),
+ /*AddressSpace=*/0, CostKind);
+}
+
+
InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
VectorType *Tp, ArrayRef<int> Mask,
TTI::TargetCostKind CostKind,
@@ -288,9 +298,7 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
LT.second.getVectorNumElements() <= 256)) {
VectorType *IdxTy = VectorType::get(IntegerType::getInt8Ty(Tp->getContext()),
Tp->getElementCount());
- InstructionCost IndexCost =
- 2 + getMemoryOpCost(Instruction::Load, IdxTy, DL.getABITypeAlign(IdxTy),
- /*AddressSpace=*/0, CostKind);
+ InstructionCost IndexCost = getConstantPoolLoadCost(IdxTy, CostKind);
return IndexCost + getLMULCost(LT.second);
}
}
@@ -1210,11 +1218,7 @@ InstructionCost RISCVTTIImpl::getStoreImmCost(Type *Ty,
// with how we treat scalar constants themselves just above.
return 1;
- // Add a cost of address generation + the cost of the vector load. The
- // address is expected to be a PC relative offset to a constant pool entry
- // using auipc/addi.
- return 2 + getMemoryOpCost(Instruction::Load, Ty, DL.getABITypeAlign(Ty),
- /*AddressSpace=*/0, CostKind);
+ return getConstantPoolLoadCost(Ty, CostKind);
}
@@ -1447,11 +1451,7 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
// scalar constants in GPRs.
return 0;
- // Add a cost of address generation + the cost of the vector load. The
- // address is expected to be a PC relative offset to a constant pool entry
- // using auipc/addi.
- return 2 + getMemoryOpCost(Instruction::Load, Ty, DL.getABITypeAlign(Ty),
- /*AddressSpace=*/0, CostKind);
+ return getConstantPoolLoadCost(Ty, CostKind);
};
// Add the cost of materializing any constant vectors required.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index b713b0629058..9df45abe110b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -51,6 +51,10 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
/// Return the cost of LMUL. The larger the LMUL, the higher the cost.
InstructionCost getLMULCost(MVT VT);
+ /// Return the cost of accessing a constant pool entry of the specified
+ /// type.
+ InstructionCost getConstantPoolLoadCost(Type *Ty,
+ TTI::TargetCostKind CostKind);
public:
explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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