[llvm] dc5679d - [RISCV] Rename FeatureExtZc* to FeatureStdExtZc*. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 27 13:19:19 PDT 2023
Author: Craig Topper
Date: 2023-03-27T13:19:01-07:00
New Revision: dc5679df71d2f633c594dba0441889e519257626
URL: https://github.com/llvm/llvm-project/commit/dc5679df71d2f633c594dba0441889e519257626
DIFF: https://github.com/llvm/llvm-project/commit/dc5679df71d2f633c594dba0441889e519257626.diff
LOG: [RISCV] Rename FeatureExtZc* to FeatureStdExtZc*. NFC
Even for experimental extensions, I think we always include "Std"
in the feature name.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146997
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7b6da038ce397..03e97f9cb669f 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2393,7 +2393,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionNoRVC();
clearFeatureBits(RISCV::FeatureStdExtC, "c");
- clearFeatureBits(RISCV::FeatureExtZca, "+experimental-zca");
+ clearFeatureBits(RISCV::FeatureStdExtZca, "+experimental-zca");
return false;
}
@@ -2568,7 +2568,7 @@ bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
return Error(ErrorLoc, "expected instruction format");
bool AllowC = getSTI().hasFeature(RISCV::FeatureStdExtC) ||
- getSTI().hasFeature(RISCV::FeatureExtZca);
+ getSTI().hasFeature(RISCV::FeatureStdExtZca);
if (!isValidInsnFormat(Format, AllowC))
return Error(ErrorLoc, "invalid instruction format");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 1232b32be6754..8ec2ae918335c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -375,7 +375,7 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
}
bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
- STI->hasFeature(RISCV::FeatureExtZca);
+ STI->hasFeature(RISCV::FeatureStdExtZca);
// The canonical nop on RVC is c.nop.
if (Count % 4 == 2) {
OS.write(UseCompressedNop ? "\x01\0" : "\0\0", 2);
@@ -606,7 +606,7 @@ bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
return false;
bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
- STI->hasFeature(RISCV::FeatureExtZca);
+ STI->hasFeature(RISCV::FeatureStdExtZca);
unsigned MinNopLen = UseCompressedNop ? 2 : 4;
if (AF.getAlignment() <= MinNopLen) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 9adb9efe08dc1..b79ed11412e68 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -216,7 +216,7 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS,
bool UseCompressedBr = false;
if (IsEqTest && (STI.hasFeature(RISCV::FeatureStdExtC) ||
- STI.hasFeature(RISCV::FeatureExtZca))) {
+ STI.hasFeature(RISCV::FeatureStdExtZca))) {
if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
SrcReg2.id() == RISCV::X0) {
UseCompressedBr = true;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
index b29c4978b090f..6118d0ddb836b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
@@ -20,7 +20,7 @@ using namespace llvm;
unsigned RISCVMCObjectFileInfo::getTextSectionAlignment() const {
const MCSubtargetInfo *STI = getContext().getSubtargetInfo();
return (STI->hasFeature(RISCV::FeatureStdExtC) ||
- STI->hasFeature(RISCV::FeatureExtZca))
+ STI->hasFeature(RISCV::FeatureStdExtZca))
? 2
: 4;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index f4e227cc6c554..95c8098829a65 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -375,7 +375,7 @@ int getIntMatCost(const APInt &Val, unsigned Size,
const FeatureBitset &ActiveFeatures, bool CompressionCost) {
bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
bool HasRVC = CompressionCost && (ActiveFeatures[RISCV::FeatureStdExtC] ||
- ActiveFeatures[RISCV::FeatureExtZca]);
+ ActiveFeatures[RISCV::FeatureStdExtZca]);
int PlatRegSize = IsRV64 ? 64 : 32;
// Split the constant into platform register sized chunks, and calculate cost
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 201e11e70d1aa..9a87fcefe803c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -309,43 +309,43 @@ def FeatureStdExtZk
FeatureStdExtZkr,
FeatureStdExtZkt]>;
-def FeatureExtZca
+def FeatureStdExtZca
: SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
"'Zca' (part of the C extension, excluding compressed "
"floating point loads/stores)">;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
"'C' (Compressed Instructions) or "
"'Zca' (part of the C extension, excluding "
"compressed floating point loads/stores)">;
-def FeatureExtZcb
+def FeatureStdExtZcb
: SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
"'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureExtZca]>;
+ [FeatureStdExtZca]>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
- AssemblerPredicate<(all_of FeatureExtZcb),
+ AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
-def FeatureExtZcd
+def FeatureStdExtZcd
: SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd),
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
"'C' (Compressed Instructions) or "
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
-def FeatureExtZcf
+def FeatureStdExtZcf
: SubtargetFeature<"experimental-zcf", "HasStdExtZcf", "true",
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
def HasStdExtCOrZcf
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
- AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcf),
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf),
"'C' (Compressed Instructions) or "
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
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