[llvm] 876980a - [M68k] Add support for lowering i1 SIGN_EXTEND_INREG

[Min-Yih Hsu via llvm-commits]

Author: Min-Yih Hsu
Date: 2023-03-27T12:26:51-07:00
New Revision: 876980a59ca08751336b64522ab9b85c32ff49ef

URL: https://github.com/llvm/llvm-project/commit/876980a59ca08751336b64522ab9b85c32ff49ef
DIFF: https://github.com/llvm/llvm-project/commit/876980a59ca08751336b64522ab9b85c32ff49ef.diff

LOG: [M68k] Add support for lowering i1 SIGN_EXTEND_INREG

Lowering i1 (inreg) sext with `(NEG (AND %val, 1))`.

Added: 
    llvm/test/CodeGen/M68k/Arith/sext-i1.ll

Modified: 
    llvm/lib/Target/M68k/M68kInstrArithmetic.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
index 2339e3caa517e..d4c10466558cd 100644
--- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -790,6 +790,12 @@ foreach S = [8, 16, 32] in {
 def : Pat<(MxSub 0, i8 :$src), (NEG8d  MxDRD8 :$src)>;
 def : Pat<(MxSub 0, i16:$src), (NEG16d MxDRD16:$src)>;
 def : Pat<(MxSub 0, i32:$src), (NEG32d MxDRD32:$src)>;
+// SExt of i1 values.
+// Although we specify `ZeroOrOneBooleanContent` for boolean content,
+// we're still adding an AND here as we don't know the origin of the i1 value.
+def : Pat<(sext_inreg i8:$src,  i1), (NEG8d  (AND8di  MxDRD8:$src,  1))>;
+def : Pat<(sext_inreg i16:$src, i1), (NEG16d (AND16di MxDRD16:$src, 1))>;
+def : Pat<(sext_inreg i32:$src, i1), (NEG32d (AND32di MxDRD32:$src, 1))>;
 
 //===----------------------------------------------------------------------===//
 // no-CCR Patterns

diff  --git a/llvm/test/CodeGen/M68k/Arith/sext-i1.ll b/llvm/test/CodeGen/M68k/Arith/sext-i1.ll
new file mode 100644
index 0000000000000..2be5224f6beb6
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/Arith/sext-i1.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=m68k < %s | FileCheck %s
+
+define void @sext_inreg_i1_to_i8(i1 %val, ptr %ptr) {
+; CHECK-LABEL: sext_inreg_i1_to_i8:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    move.b (7,%sp), %d0
+; CHECK-NEXT:    and.b #1, %d0
+; CHECK-NEXT:    neg.b %d0
+; CHECK-NEXT:    move.l (8,%sp), %a0
+; CHECK-NEXT:    move.b %d0, (%a0)
+; CHECK-NEXT:    rts
+entry:
+  %cond = select i1 %val, i8 -1, i8 0
+  store i8 %cond, ptr %ptr
+  ret void
+}
+
+define void @sext_inreg_i1_to_i16(i1 %val, ptr %ptr) {
+; CHECK-LABEL: sext_inreg_i1_to_i16:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    move.b (7,%sp), %d0
+; CHECK-NEXT:    and.l #255, %d0
+; CHECK-NEXT:    and.w #1, %d0
+; CHECK-NEXT:    neg.w %d0
+; CHECK-NEXT:    move.l (8,%sp), %a0
+; CHECK-NEXT:    move.w %d0, (%a0)
+; CHECK-NEXT:    rts
+entry:
+  %cond = select i1 %val, i16 -1, i16 0
+  store i16 %cond, ptr %ptr
+  ret void
+}
+
+define void @sext_inreg_i1_to_i32(i1 %val, ptr %ptr) {
+; CHECK-LABEL: sext_inreg_i1_to_i32:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    move.b (7,%sp), %d0
+; CHECK-NEXT:    and.l #255, %d0
+; CHECK-NEXT:    and.l #1, %d0
+; CHECK-NEXT:    neg.l %d0
+; CHECK-NEXT:    move.l (8,%sp), %a0
+; CHECK-NEXT:    move.l %d0, (%a0)
+; CHECK-NEXT:    rts
+entry:
+  %cond = select i1 %val, i32 -1, i32 0
+  store i32 %cond, ptr %ptr
+  ret void
+}
+