[llvm] 1edde1c - Recommit "[RISCV] Relax opcode restriction for .insn."

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-27T11:14:12-07:00
New Revision: 1edde1c1f80347e2560dda340697ff1c2c05a424

URL: https://github.com/llvm/llvm-project/commit/1edde1c1f80347e2560dda340697ff1c2c05a424
DIFF: https://github.com/llvm/llvm-project/commit/1edde1c1f80347e2560dda340697ff1c2c05a424.diff

LOG: Recommit "[RISCV] Relax opcode restriction for .insn."

Original commit message:
I recently added a check to make sure the lower 2 bits of the opcode
were 0x3. A post commit comment pointed out this would be allowed
for a custom extension when C is not supported.

Note, binutils does have this restriction.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/test/MC/RISCV/insn-invalid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 07728c7c2d130..108ecf806c6f0 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1505,7 +1505,7 @@ RISCVAsmParser::parseInsnDirectiveOpcode(OperandVector &Operands) {
     auto *CE = dyn_cast<MCConstantExpr>(Res);
     if (CE) {
       int64_t Imm = CE->getValue();
-      if (isUInt<7>(Imm) && (Imm & 3) == 3) {
+      if (isUInt<7>(Imm)) {
         Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
         return MatchOperand_Success;
       }
@@ -1534,8 +1534,8 @@ RISCVAsmParser::parseInsnDirectiveOpcode(OperandVector &Operands) {
     break;
   }
 
-  Error(S, "opcode must be in the range [0, 127] and the lower 2 bits must be "
-           "0x3");
+  Error(S, "opcode must be a valid opcode name or an immediate in the range "
+           "[0, 127]");
   return MatchOperand_ParseFail;
 }
 

diff  --git a/llvm/test/MC/RISCV/insn-invalid.s b/llvm/test/MC/RISCV/insn-invalid.s
index ab41f07ef567f..e9fdc4042c1dc 100644
--- a/llvm/test/MC/RISCV/insn-invalid.s
+++ b/llvm/test/MC/RISCV/insn-invalid.s
@@ -14,13 +14,12 @@
 .insn q  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format
 
 # Invalid immediate
-.insn i  0x99,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
-.insn i  0,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
+.insn i  0x99,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be a valid opcode name or an immediate in the range [0, 127]
 .insn r  0x33,  8,  0, a0, a1, a2 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7]
 .insn r4 0x43,  0,  4, fa0, fa1, fa2, fa3 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]
 
 # Unrecognized opcode name
-.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
+.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: opcode must be a valid opcode name or an immediate in the range [0, 127]
 
 # Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed.
 .insn_i  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive