[llvm] c9e4d9a - [LegalizeTypes][TargetLowering][RISCV] Fix regressions from D146786.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-27T09:58:51-07:00
New Revision: c9e4d9a8ea46e6106d248bdc99d8a07ae3ba5dc2

URL: https://github.com/llvm/llvm-project/commit/c9e4d9a8ea46e6106d248bdc99d8a07ae3ba5dc2
DIFF: https://github.com/llvm/llvm-project/commit/c9e4d9a8ea46e6106d248bdc99d8a07ae3ba5dc2.diff

LOG: [LegalizeTypes][TargetLowering][RISCV] Fix regressions from D146786.

Add some special cases for UADDO to recover codegen after D146786.

Reviewed By: reames, liaolucy

Differential Revision: https://reviews.llvm.org/D146789

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index c4f2fbc90e3eb..a5bf863055a48 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -3166,6 +3166,11 @@ void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
       SDValue Or = DAG.getNode(ISD::OR, dl, Lo.getValueType(), Lo, Hi);
       Ovf = DAG.getSetCC(dl, N->getValueType(1), Or,
                          DAG.getConstant(0, dl, Lo.getValueType()), ISD::SETEQ);
+    } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(RHS)) {
+      // Special case: uaddo X, -1 overflows if X == 0.
+      Ovf =
+          DAG.getSetCC(dl, N->getValueType(1), LHS,
+                       DAG.getConstant(0, dl, LHS.getValueType()), ISD::SETNE);
     } else {
       // Calculate the overflow: addition overflows iff a + b < a, and
       // subtraction overflows iff a - b > a.

diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b7b67a20bc9e9..f8eaa997ed356 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9968,6 +9968,11 @@ void TargetLowering::expandUADDSUBO(
     SetCC =
         DAG.getSetCC(dl, SetCCType, Result,
                      DAG.getConstant(0, dl, Node->getValueType(0)), ISD::SETEQ);
+  } else if (IsAdd && isAllOnesConstant(RHS)) {
+    // Special case: uaddo X, -1 overflows if X != 0.
+    SetCC =
+        DAG.getSetCC(dl, SetCCType, LHS,
+                     DAG.getConstant(0, dl, Node->getValueType(0)), ISD::SETNE);
   } else {
     ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
     SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC);

diff  --git a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
index d6fd69ff254fa..57bf64ece7909 100644
--- a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
@@ -663,25 +663,22 @@ define i1 @uaddo_i64_increment_alt_dom(i64 %x, ptr %p) {
 define i1 @uaddo_i64_decrement_alt(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a3, a0, -1
+; RV32-NEXT:    or a3, a0, a1
+; RV32-NEXT:    snez a3, a3
 ; RV32-NEXT:    seqz a4, a0
-; RV32-NEXT:    sub a4, a1, a4
-; RV32-NEXT:    bnez a0, .LBB18_2
-; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    sltu a0, a4, a1
-; RV32-NEXT:    j .LBB18_3
-; RV32-NEXT:  .LBB18_2:
-; RV32-NEXT:    sltu a0, a3, a0
-; RV32-NEXT:  .LBB18_3:
-; RV32-NEXT:    sw a3, 0(a2)
-; RV32-NEXT:    sw a4, 4(a2)
+; RV32-NEXT:    sub a1, a1, a4
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    sw a0, 0(a2)
+; RV32-NEXT:    sw a1, 4(a2)
+; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo_i64_decrement_alt:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addi a2, a0, -1
-; RV64-NEXT:    sltu a0, a2, a0
-; RV64-NEXT:    sd a2, 0(a1)
+; RV64-NEXT:    snez a2, a0
+; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    sd a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
   %a = add i64 %x, -1
   store i64 %a, ptr %p
@@ -694,25 +691,22 @@ define i1 @uaddo_i64_decrement_alt(i64 %x, ptr %p) {
 define i1 @uaddo_i64_decrement_alt_dom(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt_dom:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a3, a0, -1
+; RV32-NEXT:    or a3, a0, a1
+; RV32-NEXT:    snez a3, a3
 ; RV32-NEXT:    seqz a4, a0
-; RV32-NEXT:    sub a4, a1, a4
-; RV32-NEXT:    bnez a0, .LBB19_2
-; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    sltu a0, a4, a1
-; RV32-NEXT:    j .LBB19_3
-; RV32-NEXT:  .LBB19_2:
-; RV32-NEXT:    sltu a0, a3, a0
-; RV32-NEXT:  .LBB19_3:
-; RV32-NEXT:    sw a3, 0(a2)
-; RV32-NEXT:    sw a4, 4(a2)
+; RV32-NEXT:    sub a1, a1, a4
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    sw a0, 0(a2)
+; RV32-NEXT:    sw a1, 4(a2)
+; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo_i64_decrement_alt_dom:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addi a2, a0, -1
-; RV64-NEXT:    sltu a0, a2, a0
-; RV64-NEXT:    sd a2, 0(a1)
+; RV64-NEXT:    snez a2, a0
+; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    sd a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
   %ov = icmp ne i64 %x, 0
   %a = add i64 %x, -1