[llvm] 1d1b3c4 - [RISCV] Remove isCall instruction flag from JAL/JALR

[Job Noorman via llvm-commits]

Author: Job Noorman
Date: 2023-03-27T16:11:14+02:00
New Revision: 1d1b3c49531bb80bcd28870d4eafb71d97049e02

URL: https://github.com/llvm/llvm-project/commit/1d1b3c49531bb80bcd28870d4eafb71d97049e02
DIFF: https://github.com/llvm/llvm-project/commit/1d1b3c49531bb80bcd28870d4eafb71d97049e02.diff

LOG: [RISCV] Remove isCall instruction flag from JAL/JALR

As far as I can tell, the instruction flags set in the various
RISCVInstrInfo*.td files are always under-approximations. That is,
something like isTerminator will only be set for opcodes that are
*always* terminators.

The exception seems to be isCall; this is set for JAL/JALR while these
instruction are not always calls. This patch proposes to remove isCall
from JAL/JALR for consistency.

A follow-up patch will add more detailed analysis of some instruction
properties based on MCInstrAnalysis.

Reviewed By: asb, craig.topper

Differential Revision: https://reviews.llvm.org/D146437

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 70f5622bc339..bddafd2bd23b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -620,11 +620,9 @@ def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
 def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
                     "auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
 
-let isCall = 1 in
 def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
                   "jal", "$rd, $imm20">, Sched<[WriteJal]>;
 
-let isCall = 1 in
 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
                    (ins GPR:$rs1, simm12:$imm12),
                    "jalr", "$rd, ${imm12}(${rs1})">,